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2
H'D0EF: I
C Bus Mode Register ICMR0: I
7
Bit
:
MLS
Initial value
:
0
R/W
:
R/W
MSB-first/LSB-first select
0 MSB-first
1 LSB-first
Note: * See bit 6 in the serial timer control register (STCR)
6
5
WAIT
CKS2
0
0
R/W
R/W
Transfer clock select bits
IICX* CKS2 CKS1 CKS0 Clock
Wait insertion bit
0 Data and acknowledge bits transferred consecutively
1 Wait inserted between data and acknowledge bits
(Initial value)
2
C Bus Interface
4
3
CKS1
CKS0
0
0
R/W
R/W
Bit counter
BC2 BC1 BC0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
1
1
0
1
2
1
BC2
BC1
0
0
R/W
R/W
Bit/frame
Clock sync
serial format
0
0
8
1
1
1
0
2
1
3
0
0
4
1
5
1
0
6
1
7
Transfer rate
φ=8 MHz
φ=10 MHz
φ/28
286 kHz
357 kHz
φ/40
200 kHz
250 kHz
φ/48
167 kHz
208 kHz
φ/64
125 kHz
156 kHz
φ/80
100 kHz
125 kHz
φ/100
80.0 kHz
100 kHz
φ/112
71.4 kHz
89.3 kHz
φ/128
62.5 kHz
78.1 kHz
φ/56
143 kHz
179 kHz
φ/80
100 kHz
125 kHz
φ/96
83.3 kHz
104 kHz
φ/128
62.5 kHz
78.1 kHz
φ/160
50.0 kHz
62.5 kHz
φ/200
40.0 kHz
50.0 kHz
φ/224
35.7 kHz
44.6 kHz
φ/256
31.3 kHz
39.1 kHz
(Initial value)
Rev. 1.0, 02/00, page 1035 of 1141
0
BC0
0
R/W
2
I
C bus format
9 (Initial value)
2
3
4
5
6
7
8
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