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24.2.5
Trigger Select Register (ADTSR)
Bit :
Initial value :
R/W :
The trigger select register (ADTSR) selects hardware- or external-triggered A/D conversion start
factor.
ADTSR is an 8-bit readable/writable register that is initialized to H'FC by a reset, and in module
stop mode, standby mode, watch mode, subactive mode and subsleep mode.
Bits 7 to 2 Reserved: These bits cannot be modified and are always read as 1.
Bits 1 and 0 Trigger Select (TRGS1, TRGS0): These bits select hardware- or external-
triggered A/D conversion start factor. Set these bits when A/D conversion is not in progress.
Bit 1
Bit 0
TRGS1
TRGS0
0
0
1
1
0
1
24.2.6
Port Mode Register 0 (PMR0)
Bit :
PMR07
Initial value :
R/W :
R/W
Port mode register 0 (PMR0) controls switching of each pin function of port 0. Switching is
specified for each bit.
PMR0 is an 8-bit readable/writable register and is initialized to H'00 by a reset.
Rev. 1.0, 02/00, page 524 of 1141
7
6
—
—
1
1
—
—
Description
Hardware- or external-triggered A/D conversion is disabled
Hardware-triggered (ADTRG) A/D conversion is selected
Hardware-triggered (DFG) A/D conversion is selected
External-triggered ($'75*) A/D conversion is selected
7
6
PMR06
PMR05
0
0
R/W
R/W
5
4
—
—
1
1
—
—
5
4
PMR04
PMR03
0
0
R/W
R/W
3
2
—
—
TRGS1
1
1
R/W
—
—
3
2
PMR02
PMR01
0
0
R/W
R/W
1
0
TRGS0
0
0
R/W
(Initial value)
1
0
PMR00
0
0
R/W
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