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Hitachi H8S/2199 Hardware Manual

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ADE-602-191
Rev 1.0
2/15/00
Hitachi, Ltd.
Hitachi Single-Chip Microcomputer
H8S/2199 Series
H8S/2199
HD6432199
H8S/2198
HD6432198
H8S/2197
HD6432197
H8S/2196
HD6432196
H8S/2199F-ZTAT
HD64F2199
Hardware Manual

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  Summary of Contents for Hitachi H8S/2199

  • Page 1 Hitachi Single-Chip Microcomputer H8S/2199 Series H8S/2199 HD6432199 H8S/2198 HD6432198 H8S/2197 HD6432197 H8S/2196 HD6432196 ™ H8S/2199F-ZTAT HD64F2199 Hardware Manual ADE-602-191 Rev 1.0 2/15/00 Hitachi, Ltd.
  • Page 2 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
  • Page 3: Table Of Contents

    Contents Section 1 Overview ......................Overview........................... Internal Block Diagram..................... Pin Arrangement and Functions..................1.3.1 Pin Arrangement....................1.3.2 Pin Functions ....................Section 2 ........................17 Overview........................... 17 2.1.1 Features......................17 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU ....... 18 2.1.3 Differences from H8/300 CPU .................
  • Page 4 2.9.1 Overview ......................59 2.9.2 On-Chip Memory (ROM, RAM)..............59 2.9.3 On-Chip Supporting Module Access Timing ........... 60 Section 3 MCU Operating Modes ................61 Overview........................... 61 3.1.1 Operating Mode Selection ................61 3.1.2 Register Configuration..................61 Register Descriptions ......................62 3.2.1 Mode Control Register (MDCR) ..............
  • Page 5 Section 5 Exception Handling ..................87 Overview........................... 87 5.1.1 Exception Handling Types and Priority............87 5.1.2 Exception Handling Operation ................. 88 5.1.3 Exception Sources and Vector Table..............88 Reset..........................90 5.2.1 Overview ......................90 5.2.2 Reset Sequence ....................90 5.2.3 Interrupts after Reset..................
  • Page 6 Section 7 ........................123 Overview........................... 123 7.1.1 Block Diagram....................123 Overview of Flash Memory ....................124 7.2.1 Features......................124 7.2.2 Block Diagram....................125 7.2.3 Flash Memory Operating Modes ..............126 7.2.4 Pin Configuration ..................... 130 7.2.5 Register Configuration..................130 Flash Memory Register Descriptions................131 7.3.1 Flash Memory Control Register 1 (FLMCR1) ..........
  • Page 7 Notes when Converting the F–ZTAT Application Software to the Mask-ROM Versions ..........................169 Section 8 ........................171 Overview........................... 171 8.1.1 Block Diagram....................171 Section 9 Clock Pulse Generator .................. 173 Overview........................... 173 9.1.1 Block Diagram....................173 9.1.2 Register Configuration..................173 Register Descriptions ......................
  • Page 8 10.4.2 Register Configuration..................198 10.4.3 Pin Functions ....................201 10.4.4 Pin States ......................203 10.5 Port 3..........................204 10.5.1 Overview ......................204 10.5.2 Register Configuration..................204 10.5.3 Pin Functions ....................208 10.5.4 Pin States ......................211 10.6 Port 4..........................212 10.6.1 Overview ......................
  • Page 9 11.3.3 Initializing the Counts..................252 Section 12 Timer B ......................253 12.1 Overview........................... 253 12.1.1 Features......................253 12.1.2 Block Diagram....................253 12.1.3 Pin Configuration ..................... 254 12.1.4 Register Configuration..................254 12.2 Register Descriptions ......................255 12.2.1 Timer Mode Register B (TMB) ................ 255 12.2.2 Timer Counter B (TCB)..................
  • Page 10 14.1.2 Block Diagram....................280 14.1.3 Register Configuration..................281 14.2 Register Descriptions ......................282 14.2.1 Timer L Mode Register (LMR) ................ 282 14.2.2 Linear Time Counter (LTC) ................284 14.2.3 Reload/Compare Match Register (RCR) ............284 14.2.4 Module Stop Control Register (MSTPCR)............285 14.3 Operation ..........................
  • Page 11 16.1.1 Features......................313 16.1.2 Block Diagram....................314 16.1.3 Pin Configuration ..................... 315 16.1.4 Register Configuration..................316 16.2 Register Descriptions ......................317 16.2.1 Free Running Counter (FRC) ................317 16.2.2 Output Comparing Registers A and B (OCRA and OCRB) ......318 16.2.3 Input Capture Registers A Through D (ICRA Through ICRD)......
  • Page 12 17.3.2 Interval Timer Operation .................. 356 17.3.3 Timing of Setting of Overflow Flag (OVF)............357 17.4 Interrupts........................... 358 17.5 Usage Notes ........................358 17.5.1 Contention between Watchdog Timer Counter (WTCNT) Write and Increment ..................358 17.5.2 Changing Value of CKS2 to CKS0 ..............359 17.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode ....
  • Page 13 20.2.3 Module Stop Control Register (MSTPCR)............384 20.3 14-Bit PWM Operation..................... 385 Section 21 Prescalar Unit ....................387 21.1 Overview........................... 387 21.1.1 Features......................387 21.1.2 Block Diagram....................388 21.1.3 Pin Configuration ..................... 389 21.1.4 Register Configuration..................389 21.2 Registers..........................390 21.2.1 Input Capture Register 1 (ICR1)...............
  • Page 14 22.3.4 Operation in Synchronous Mode ..............442 22.4 SCI Interrupts........................450 22.5 Usage Notes ........................451 Section 23 I C Bus Interface (IIC) ................. 459 23.1 Overview........................... 459 23.1.1 Features......................459 23.1.2 Block Diagram....................460 23.1.3 Pin Configuration ..................... 461 23.1.4 Register Configuration..................
  • Page 15 24.2.3 A/D Control Register (ADCR) ................. 518 24.2.4 A/D Control/Status Register (ADCSR) ............521 24.2.5 Trigger Select Register (ADTSR)..............524 24.2.6 Port Mode Register 0 (PMR0) ................524 24.2.7 Module Stop Control Register (MSTPCR)............525 24.3 Interface to Bus Master ..................... 526 24.4 Operation ..........................
  • Page 16 26.3.2 Block Diagram....................566 26.3.3 Register Configuration..................568 26.3.4 Register Description ..................569 26.3.5 Operation ......................574 26.4 HSW (Head-switch) Timing Generator ................589 26.4.1 Overview ......................589 26.4.2 Block Diagram....................589 26.4.3 HSW Timing Generator Configuration ............591 26.4.4 Register Configuration..................
  • Page 17 26.9.5 Operation ......................654 26.10 X-Value and Tracking Adjustment Circuit ............... 656 26.10.1 Overview ......................656 26.10.2 Block Diagram....................656 26.10.3 Register Description ..................658 26.11 Digital Filters ........................661 26.11.1 Overview ......................661 26.11.2 Block Diagram....................662 26.11.3 Arithmetic Buffer ..................... 664 26.11.4 Register Configuration..................
  • Page 18 26.15.6 Noise Detection ....................744 26.15.7 Activation of the Sync Signal Detector ............747 26.16 Servo Interrupt ........................748 26.16.1 Overview ......................748 26.16.2 Register Configuration..................748 26.16.3 Register Description ..................748 Section 27 Sync Separator for OSD and Data Slicer ..........
  • Page 19 28.2.2 Slice Line Setting Registers 1 to 4 (SLINE1 to SLINE4)......... 807 28.2.3 Slice Detection Registers 1 to 4 (SDTCT1 to SDTCT4) ........808 28.2.4 Slice Data Registers 1 to 4 (SDATA1 to SDATA4)......... 811 28.2.5 Module Stop Control Register (MSTPCR)............812 28.2.6 Monitor Output Setting Register (DOUT) ............
  • Page 20 29.5.9 Screen Control Register (DCNTL) ..............850 29.6 Other Settings........................855 29.6.1 TV Format ......................855 29.6.2 Display Data RAM Control ................855 29.6.3 Timing of OSD Display Updates Using Register Rewriting ......855 29.6.4 4fsc/2fsc......................855 29.6.5 OSDV Interrupts....................855 29.6.6 OSD Format Register (DFORM)..............
  • Page 21: Overview

    30.2.7 OSD Electrical Characteristics of HD6432199, HD6432198, HD6432197, and HD6432196....................896 30.3 Electrical Characteristics of HD64F2199 ................. 900 30.3.1 DC Characteristics of HD64F2199..............900 30.3.2 Allowable Output Currents of HD64F2199............907 30.3.3 AC Characteristics of HD64F2199..............908 30.3.4 Serial Interface Timing of HD64F2199............911 30.3.5 A/D Converter Characteristics of HD64F2199..........
  • Page 22: Section 1 Overview

    CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series. The H8S/2199 Series is equipped with a digital servo circuit, sync separator, OSD, data slicer, ROM, RAM, seven types of timers, three types of PWM, two types of serial communication interface, an I C bus interface, A/D converter, and I/O port as on-chip supporting modules.
  • Page 23 Table 1.1 Features of the H8S/2199 Series Item Specifications • General-register architecture  Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • High-speed operation suitable for real-time control  Maximum operating frequency: 10 MHz/4 to 5.5 V ...
  • Page 24 Item Specifications  Timer L Timer • 8-bit up/down counter • Clock source can be selected among 2 types of internal clock, CFG frequency division signal, and PB and REC-CTL (control pulse) • Compare-match clearing function/auto reload function  Timer R •...
  • Page 25 Item Specifications  Asynchronous mode or synchronous mode selectable Serial communication  Desired bit rate selectable with built-in baud rate generator interface (SCI)  Multiprocessor communication function  Conforms to Phillips I C bus interface C bus interface standard (2 channels) ...
  • Page 26  Sampling clock generated by AFC  Slice interrupt  Error detection  Flash memory or mask ROM (Refer to the product line-up) Memory  High-speed static RAM Product Name H8S/2199 128 k bytes 3 k bytes H8S/2198 112 k bytes 3 k bytes H8S/2197...
  • Page 27  Subclock pulse generator: 32.768 kHz  112-pin plastic QFP (FP-112) Packages Product lineup Product Code ROM/RAM Mask ROM F-ZTAT Series (bytes) Packages Versions Versions H8S/2199 HD6432199 HD64F2199 128 k/3 k FP-112 (256 k*/ 8 k*)  HD6432198 112 k/3 k FP-112  HD6432197...
  • Page 28: Internal Block Diagram

    Internal Block Diagram Figure 1.1 shows an internal block diagram of the H8S/2199 Series. P37/TMO P27/SYNCI P36/BUZZ P26/SCL0 P35/PWM3 P25/SDA0 H8S/2000 CPU P34/PWM2 P24/SCL1 P33/PWM1 P23/SDA1 P32/PWM0 P22/SCK1 P31/SV2 Internal data bus P21/SO1 P30/SV1 P20/SI1 R O M Internal address bus...
  • Page 29: Pin Arrangement And Functions

    Pin Arrangement and Functions 1.3.1 Pin Arrangement Figure 1.2 shows the pin arrangement of the H8S/2199 Series. P32/PWM0 P31/SV2 P35/PWM3 P30/SV1 P36/BUZZ P70/PPG0 P37/TMO P71/PPG1 P60/RP0 P72/PPG2 P61/RP1 P73/PPG3 P62/RP2 P74/PPG4/RP8 P63/RP3 P75/PPG5/RP9 P64/RP4 P76/PPG6/RPA P65/RP5 P77/PPG7/RPB P66/RP6/ P80/YCO P67/RP7/TMBI...
  • Page 30: Pin Functions

    1.3.2 Pin Functions Table 1.2 summarizes the functions of the H8S/2199 Series pins. Table 1.2 Pin Functions Type Symbol Pin No. Name and Function Power 56, 112 Input Power supply: supply All Vcc pins should be connected to the system...
  • Page 31 Type Symbol Pin No. Name and Function Operating Input Mode pin: mode This pin sets the operating mode. This pin control should not be changed while the MCU is in operation System Input Reset input: control When this pin is driven low, the chip is reset Input Flash memory enable: Enables/disables flash memory programming.
  • Page 32 Type Symbol Pin No. Name and Function ,546 Timers Input Timer R input capture: Input pin for input capture of Timer R TMRU-1 or TMRU-2 FTOA Output Timer X1 output compare A and B output: FTOB Output pin for output compare A and B of Timer FTIA Input Timer X1 input capture A, B, C and D input:...
  • Page 33 Type Symbol Pin No. Name and Function AN7 to 28 to 35 Input Analog input channels 7 to 0: converter Analog data input pins. A/D conversion is started by a software triggering Input Analog input channels 8, 9, A and B: Analog data input pins.
  • Page 34 Type Symbol Pin No. Name and Function Servo CTL Amp Output CTL amp output: circuits Output pin for CTL amp CTL SMT Input CTL Schmitt amp input: Input pin for CTL Schmitt amp CTLFB Input CLT feedback input: Input pin for CTL amp high-range characteristics control CTLREF Output...
  • Page 35 Type Symbol Pin No. Name and Function Sync Csync/ Input/ Sync signal input/output: separator Hsync output Composite sync signal input/output or horizontal sync signal input VLPF/ Input Sync signal input: Vsync Pin for connecting external LPF for vertical sync signal or input pin for vertical sync signal AFC pc Input/ AFC oscillation:...
  • Page 36 Type Symbol Pin No. Name and Function Output OSD digital output: Character data output Output OSD digital output: Character display position output Data CVin2 Input Composite video input: slicer Composite video signal input. Input 2-Vp-p composite video signal, and the sync tip of the signal is clamped to about 2.0 V.
  • Page 37: Cpu

    Section 2 CPU Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16- bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control.
  • Page 38: Differences Between H8S/2600 Cpu And H8S/2000 Cpu

    16 ÷ 8-bit register-register divide: 1200 ns 16 × 16-bit register-register multiply: 2000 ns 32 ÷ 16-bit register-register divide: 2000 ns • Two CPU operating modes Normal mode*/Advanced mode • Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection Note: * Normal mode is not available for this LSI.
  • Page 39: Differences From H8/300H Cpu

    • Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. • Enhanced addressing mode The addressing modes have been enhanced to make effective use of the 16-Mbyte address space.
  • Page 40: Cpu Operating Modes

    CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally the maximum total address space is 4 Gbytes, with a maximum of 16 Mbytes for the program area and a maximum of 4 Gbytes for the data area).
  • Page 41 (d) Exception Vector Table and Memory Indirect Branch Addresses In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The configuration of the exception vector table in normal mode is shown in figure 2.2.
  • Page 42 (e) Stack Structure When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.3. The extended control register (EXR) is not pushed onto the stack.
  • Page 43 (d) Exception Vector Table and Memory Indirect Branch Addresses In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.4).
  • Page 44 (e) Stack Structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.5. The extended control register (EXR) is not pushed onto the stack.
  • Page 45: Address Space

    Address Space Figure 2.6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'0000 H'00000000 H'FFFF Program area H'00FFFFFF...
  • Page 46: Register Configuration

    Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2.7. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) ER7 (SP) Control Registers (CR) 7 6 5 4 3 2 1 0 T –...
  • Page 47: General Registers

    2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
  • Page 48: Control Registers

    Free area SP (ER7) Stack area Figure 2.9 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored.
  • Page 49: Initial Register Values

    Bit 6: User Bit or Interrupt Mask Bit (UI) Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. For details, see section 6, Interrupt Controller.
  • Page 50: Data Formats

    Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
  • Page 51 Data Type General Register Data format Word data Word data Longword data [Legend] : General register ER : General register E : General register R : General register RH : General register RL : Most significant bit : Least significant bit Figure 2.11 General Register Data Formats (2) Rev.
  • Page 52: Memory Data Formats

    2.5.2 Memory Data Formats Figure 2.12 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address.
  • Page 53: Instruction Set

    Instruction Set 2.6.1 Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Size Types Data transfer , PUSH LDM, STM MOVFPE, MOVTPE Arithmetic ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS...
  • Page 54: Instructions And Addressing Modes

    2.6.2 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2000 CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes Addressing Modes Instruction — — — — — POP, PUSH — —...
  • Page 55: Table Of Instructions Classified By Function

    2.6.3 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the functions of the instructions. The notation used in table 2.3 is defined below. Operation Notation General register (destination)* General register (source)* General register* General register (32-bit register) (EAd) Destination operand (EAs)
  • Page 56 Table 2.3 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register MOVFPE Cannot be used in this LSI MOVTPE Cannot be used in this LSI @SP+ →...
  • Page 57 Table 2.4 Arithmetic Instructions Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register.
  • Page 58 Instruction Size* Function Rd ÷ Rs → Rd DIVXS Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder B/W/L Rd - Rs, Rd - #IMM Compares data in a general register with data in another general...
  • Page 59 Table 2.5 Logic Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data...
  • Page 60 Table 2.7 Bit Manipulation Instructions Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register 0 →...
  • Page 61 Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BOXR Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag C ⊕ [~ (<bit-No.> of <EAd>)] → C BIXOR Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in...
  • Page 62 Table 2.8 Branch Instructions Instruction Size* Function  Branches to a specified address if a specified condition is true The branching conditions are listed below Mnemonic Description Condition BRA (BT) Always (True) Always BRN (BF) Never (False) Never HIgh CVZ = 0 Low of Same CVZ = 1 BCC (BHS)
  • Page 63 Table 2.9 System Control Instructions Instruction Size* Function  TRAPA Starts trap-instruction exception handling  Returns from an exception-handling routine  SLEEP Causes a transition to a power-down state (EAs) → CCR, (EAs) → EXR Moves contents of a general register or memory or immediate data to CCR or EXR.
  • Page 64 Table 2.10 Block Data Transfer Instructions Instruction Size* Function  if R4L ≠ 0 then EEPMOV.B Repeat @ER5+→@er6+ R4L−1→R4L Until R4L = 0 else next;  if R4 ≠ 0 then EEPMOV.W Repeat @ER5+→@er6+ R4−1→R4 Until R4 = 0 else next; Transfers a data block according to parameters set in general registers R4L or R4, ER5, and ER6 R4L or R4: size of block (bytes)
  • Page 65: Basic Instruction Formats

    2.6.4 Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.13 shows examples of instruction formats. (1) Operation field only NOP, RTS, etc.
  • Page 66: Notes On Use Of Bit-Manipulation Instructions

    2.6.5 Notes on Use of Bit-Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, carry out bit manipulation, then write back the byte of data. Caution is therefore required when using these instructions on a register containing write-only bits, or a port. The BCLR instruction can be used to clear internal I/O register flags to 0.
  • Page 67: Addressing Modes And Effective Address Calculation

    Addressing Modes and Effective Address Calculation 2.7.1 Addressing Mode The CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program- counter relative and memory indirect.
  • Page 68 (4) Register Indirect with Post-Increment or Pre-Decrement–@ERn+ or @-ERn (a) Register indirect with post-increment–@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register.
  • Page 69 (6) Immediate–#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number.
  • Page 70: Effective Address Calculation

    If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or an instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation...
  • Page 71 Table 2.13 Effective Address Calculation Addressing Mode and Effective Address Instruction Format Calculation Effective Address (EA) Register direct (Rn) Operand is general register contents rm rn Register indirect (@ERn) 24 23 Don’t General register contents care Register indirect with displacement @(d:16, ERn) or @(d:32, ERn) General register contents 24 23...
  • Page 72 Addressing Mode and Effective Address Instruction Format Calculation Effective Address (EA) Absolute address @aa:8 24 23 Don’t H'FFFF care @aa:16 24 23 16 15 Sign Don’t exten- care sion @aa:24 24 23 Don’t care @aa:32 24 23 Don’t care Immediate #xx:8/#xx:16/#xx:32 Operand is immediate data Program-counter relative @(d:8, PC)/@(d:16, PC)
  • Page 73 Addressing Mode and Effective Address Instruction Format Calculation Effective Address (EA) Memory indirect @@aa:8 • Normal mode H'000000 24 23 16 15 Don’t H'00 care Memory contents • Advanced mode H'000000 24 23 Don’t Memory contents care Rev. 1.0, 02/00, page 53 of 1141...
  • Page 74: Processing States

    Processing States 2.8.1 Overview The CPU has four main processing states: the reset state, exception-handling state, program execution state, and power-down state. Figure 2.15 shows a diagram of the processing states. Figure 2.16 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped. Exception-handling state A transient state in which the CPU changes the normal processing flow in response...
  • Page 75: Reset State

    Program execution state Sleep mode External interrupt request Exception-handling state Standby mode Power-down state = High Reset state Notes: From any state, a transition to the reset state occurs whenever goes low. A transition can also be made to the reset state when the watchdog timer overflows. The power-down state also includes a watch mode, subactive mode, subsleep mode, etc.
  • Page 76: Exception-Handling State

    2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for resets, interrupts, and trap instructions.
  • Page 77: Program Execution State

    Figure 2.17 shows the stack after exception handling ends. Normal Mode Advanced Mode (24 bits) (16 bits) Notes: 1. Ignored when returning. 2. Normal mode is not available for this LSI. Figure 2.17 Stack Structure after Exception Handling (Examples) 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence.
  • Page 78: Power-Down State

    2.8.5 Power-Down State The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode, standby mode, subsleep mode, and watch mode. There are also three other power-down modes: medium-speed mode, module stop mode, and subactive mode.
  • Page 79: Basic Timing

    Basic Timing 2.9.1 Overview The CPU is driven by a system clock, denoted by the symbol φ. The period from one rising edge of φ to the next is referred to as a “state.” The memory cycle or bus cycle consists of one or two states.
  • Page 80: On-Chip Supporting Module Access Timing

    2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.19 shows the access timing for the on-chip supporting modules. Bus cycle φ...
  • Page 81: Mcu Operating Modes

    Section 3 MCU Operating Modes Overview 3.1.1 Operating Mode Selection This LSI has one operating mode (mode 1). This mode is selected depending on settings of the mode pin (MD0). Table 3.1 lists the MCU operating modes. Table 3.1 MCU Operating Mode Selection MCU Operating Mode CPU Operating Mode Description...
  • Page 82: Register Descriptions

    Register Descriptions 3.2.1 Mode Control Register (MDCR) Bit : — — — — — — — MDS0 Initial value : —* — R/W : — — — — — — Note: * Determined by MD0 pin MDCR is an 8-bit read-only register monitors the current operating mode of this LSI. Bit 7 to 1: Reserved.
  • Page 83: Operating Mode (Mode 1)

    Bits 5 and 4    Interrupt control modes 1 and 0 (INTM1, INTM0) These bits are for selecting the interrupt control mode of the interrupt controller. For details of the interrupt control modes, see section 6.4.1, Interrupt Control Modes and Interrupt Operation. Bit 5 Bit 4 Interrupt...
  • Page 84: Address Map In Each Operating Mode

    Address Map in Each Operating Mode H8S/2196 H8S/2197 H'000000 H'000000 Vector area Vector area H'0000FF On-chip ROM On-chip ROM (96 kbytes) (80 kbytes) H'007FFF H'013FFF H'017FFF H'040000 H'040000 OSD ROM OSD ROM (24 kbytes) (24 kbytes) H'045FFF H'045FFF H'FF8000 H'FFD000 H'FFD000 Internal I/O register Internal I/O register...
  • Page 85 H8S/2198 H8S/2199 H'000000 H'000000 Vector area Vector area On-chip ROM On-chip ROM (112 kbytes) (128 kbytes) H'01BFFF H'040000 H'01FFFF OSD ROM (24 kbytes) H'040000 H'045FFF OSD ROM (24 kbytes) H'045FFF H'FFD000 H'FFD000 Internal I/O register Internal I/O register H'FFD2FF H'FFD2FF...
  • Page 86: Power-Down State

    Section 4 Power-Down State Overview In addition to the normal program execution state, this LSI has a power-down state in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on.
  • Page 87 Table 4.1 H8S/2199 Series Internal States in Each Mode Medium- Module Function High-Speed Speed Sleep Stop Watch Sub-active Sub-sleep Standby System clock Functioning Functioning Functioning Functioning Halted Halted Halted Halted Subclock pulse generator Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning...
  • Page 88 4. In the power-down mode, the analog section of the servo circuits are not turned off, therefore Vcc (Servo) current does not go low. When power-down is needed, externally shut down the analog system power. *1 The SCI1 status differs from the internal register. For details, refer to section 22, Serial Communication Interface 1.
  • Page 89 Table 4.2 Power-Down Mode Transition Conditions Control Bit States at Time of Transition State before State after Transition State after Return Transition SSBY TMA3 LSON DTON by SLEEP Instruction by Interrupt High-speed/ Sleep High-speed/ medium- medium-speed speed   Standby High-speed/ medium-speed ...
  • Page 90: Register Configuration

    4.1.1 Register Configuration The power-down state is controlled by the SBYCR, LPWRCR, TMA (Timer A), and MSTPCR registers. Table 4.3 summarizes these registers. Table 4.3 Power-Down State Registers Name Abbreviation Initial Value Address* Standby control register SBYCR H'00 H'FFEA Low-power control register LPWRCR H'00 H'FFEB...
  • Page 91 Register Descriptions 4.2.1 Standby Control Register (SBYCR) Bit : SSBY STS2 STS1 STS0 — — SCK1 SCK0 Initial value : R/W : — — SBYCR is an 8-bit readable/writable register that performs power-down mode control. SBYCR is initialized to H'00 by a reset. Bit 7...
  • Page 92 Bits 6 to 4    Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the time the MCU waits for the clock to stabilize when standby mode, watch mode, or subactive mode is cleared and a transition is made to high-speed mode or medium-speed mode by means of a specific interrupt or instruction.
  • Page 93: Low-Power Control Register (Lpwrcr)

    4.2.2 Low-Power Control Register (LPWRCR) Bit : DTON LSON NESEL — — — Initial value : R/W : — — — LPWRCR is an 8-bit readable/writable register that performs power-down mode control. LPWRCR is initialized to H'00 by a reset. Bit 7...
  • Page 94 Bit 6    Low-Speed on Flag (LSON): Determines the operating mode in combination with other control bits when making a power-down transition by executing a SLEEP instruction. Also controls whether a transition is made to high-speed mode or to subactive mode when watch mode is cleared.
  • Page 95: Timer Register A (Tma)

    4.2.3 Timer Register A (TMA) Bit : — — TMAOV TMAIE TMA3 TMA2 TMA1 TMA0 Initial value : R/W : R/(W)* Note: * Only 0 can be written, to clear the flag. The timer register A (TMA) controls timer A interrupts and selects input clock. Only bit 3 is explained here.
  • Page 96: Module Stop Control Register (Mstpcr)

    4.2.4 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : MSTPCR comprises two 8-bit readable/writable registers that perform module stop mode control. MSTPCR is initialized to H'FFFF by a reset.
  • Page 97: Medium-Speed Mode

    Medium-Speed Mode When the SCK1 and SCK0 bits in SBYCR are set to 1 in high-speed mode, the operating mode changes to medium-speed mode at the end of the bus cycle. In medium-speed mode, the CPU operates on the operating clock (φ16, φ32 or φ64) specified by the SCK1 and SCK0 bits. The on- chip supporting modules other than the CPU always operate on the high-speed clock (φ).
  • Page 98: Sleep Mode

    Sleep Mode 4.4.1 Sleep Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in LPWRCR are both cleared to 0, the CPU will enter sleep mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are retained.
  • Page 99: Module Stop Mode

    Module Stop Mode 4.5.1 Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently.
  • Page 100: Standby Mode

    Standby Mode 4.6.1 Standby Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, the LSON bit in LPWRCR is cleared to 0, and the TMA3 bit in TMA (Timer A) is cleared to 0, standby mode will be entered.
  • Page 101 Table 4.5 Oscillation Settling Time Settings STS2 STS1 STS0 Standby Time 10 MHz 8 MHz Unit 8192 states 16384 states 32768 states 65536 states 131072 states 13.1 16.4 262144 states 26.2 32.8   µs Reserved Notes: * Don't care 1.
  • Page 102: Watch Mode

    Watch Mode 4.7.1 Watch Mode If a SLEEP instruction is executed in high-speed mode, medium-speed mode or subactive mode when the SSBY in SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the TMA3 bit in TMA (Timer A) is set to 1, the CPU will make a transition to watch mode.
  • Page 103: Subsleep Mode

    Subsleep Mode 4.8.1 Subsleep Mode If a SLEEP instruction is executed in subactive mode when the SSBY in SBYCR is cleared to 0, the LSON bit in LPWRCR is set to 1, and the TMA3 bit in TMA (Timer A) is set to 1, the CPU will make a transition to subsleep mode.
  • Page 104: Subactive Mode

    Subactive Mode 4.9.1 Subactive Mode If a SLEEP instruction is executed in high-speed mode when the SSBY bit in SBYCR, the DTON bit in LPWRCR, and the TMA3 bit in TMA (timer A) are all set to 1, the CPU will make a transition to subactive mode.
  • Page 105: Direct Transition

    4.10 Direct Transition 4.10.1 Overview of Direct Transition There are three operating modes in which the CPU executes programs: high-speed mode, medium-speed mode, and subactive mode. A transition between high-speed mode and subactive mode without halting the program* is called a direct transition. A direct transition can be carried out by setting the DTON bit in LPWRCR to 1 and executing a SLEEP instruction.
  • Page 106: Exception Handling

    Section 5 Exception Handling Overview 5.1.1 Exception Handling Types and Priority As table 5.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 5.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
  • Page 107: Exception Handling Operation

    5.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC) and condition-code register (CCR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3.
  • Page 108 Table 5.2 Exception Vector Table Exception Source Vector Number Vector Address Reset H'0000 to H'0003 Reserved for system use H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 Direct transition H'0018 to H001B External interrupt H'001C to H'001F Trap instruction (4 sources) H'0020 to H'0023...
  • Page 109: Reset

    Reset 5.2.1 Overview A reset has the highest exception priority. When the 5(6 pin goes low, all processing halts and the LSI enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set. Reset exception handling begins when the 5(6 pin changes from low to high.
  • Page 110: Interrupts After Reset

    Vector Internal Fetch of first program fetch processing instruction φ Internal address bus Internal read signal Internal write signal High level Internal data bus : Reset exception vector address ((1) = H'0000 or H'000000) : Start address (contents of reset exception vector address) : Start address ((3) = (2)) : First program instruction Figure 5.2 Reset Sequence (Mode 1)
  • Page 111: Interrupts

    Interrupts Interrupt exception handling can be requested by six external sources (,548 to ,543) and internal sources in the on-chip supporting modules. Figure 5.3 shows the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), prescaler unit (PSU), Timers A, B, J, L, R and X1 (TMR), serial communication interface (SCI), A/D converter (ADC), I C bus interface (IIC), servo circuits, sync detection, data slicer, OSD,...
  • Page 112: Trap Instruction

    Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code.
  • Page 113: Stack Status After Exception Handling

    Stack Status after Exception Handling Figures 5.4 and 5.5 show the stack after completion of trap instruction exception handling and interrupt exception handling. SP→ CCR* (16 bits) Interrupt control modes 0 and 1 Note: * Ignored on return. Figure 5.4 Stack Status after Exception Handling (Normal Mode)* Note: * Normal mode is not available for this LSI.
  • Page 114: Notes On Use Of The Stack

    Notes on Use of the Stack When accessing word data or longword data, this chip assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W (or MOV.W Rn, @-SP)
  • Page 115: Section 6 Interrupt Controller

    Section 6 Interrupt Controller Overview 6.1.1 Features This LSI controls interrupts by means of an interrupt controller. The interrupt controller has the following features: • Two Interrupt Control Modes  Either of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR).
  • Page 116: Block Diagram

    6.1.2 Block Diagram Figure 6.1 shows a block diagram of the interrupt controller. INTM1, INTM0 SYSCR Interrupt request Vector number IRQ input IRQ input unit IRQR Priority determina- tion I, UI IEGR IENR Internal interrupt requests Interrupt controller [Legend] IEGR : IRQ edge select register IENR : IRQ enable register...
  • Page 117: Pin Configuration

    6.1.3 Pin Configuration Table 6.1 summarizes the pins of the interrupt controller. Table 6.1 Interrupt Controller Pins Name Symbol Function ,543 External interrupt Input Maskable external interrupts; rising, falling, or both request 0 edges can be selected ,544 to External interrupt Input Maskable external interrupts: rising, or falling ,548...
  • Page 118 Register Descriptions 6.2.1 System Control Register (SYSCR) Bit : — — — INTM1 INTM0 XRST — — Initial value : — — — — — R/W : SYSCR is an 8-bit readable register that selects the interrupt control mode. Only bits 5, 4, 2 and 1 are described here; for details on the other bits, see section 3.2.2, System Control Register (SYSCR).
  • Page 119: Interrupt Control Registers A To D (Icra To Icrd)

    6.2.2 Interrupt Control Registers A to D (ICRA to ICRD) Bit : ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0 Initial value : R/W : The ICR registers are four 8-bit readable/writable registers that set the interrupt control level for interrupts other than NMI.
  • Page 120: Irq Enable Register (Ienr)

    6.2.3 IRQ Enable Register (IENR) Bit : IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E — — Initial value : — — R/W : IENR is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ5 to IRQ0. IENR is initialized to H'00 by a reset. Bits 7 and 6...
  • Page 121: Irq Edge Select Registers (Iegr)

    6.2.4 IRQ Edge Select Registers (IEGR) Bit : — IRQ5EG IRQ4EG IRQ3EG IRQ2EG IRQ1EG IRQ0EG1 IRQ0EG0 Initial value : R/W : — IEGR is an 8-bit readable/writable register that selects detected edge of the input at pins ,548 to ,543. IEGR register is initialized to H'00 by a reset.
  • Page 122: Irq Status Register (Irqr)

    6.2.5 IRQ Status Register (IRQR) Bit : IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F — — Initial value : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/W : — — Note: * Only 0 can be written, to clear the flag. IRQR is an 8-bit readable/writable register that indicates the status of I RQ 5 t o I RQ 0 i nt er r upt requests.
  • Page 123: Port Mode Register (Pmr1)

    6.2.6 Port Mode Register (PMR1) Bit : PMR17 PMR16 PMR15 PMR14 PMR13 PMR12 PMR11 PMR10 Initial value : R/W : Port Mode Register 1 (PMR1) controls pin function switching-over of port 1. Switching is specified for each bit. PMR1 is an 8-bit readable/writable register and is initialized to H'00 by a reset. Only bits 5 to 0 are explained here.
  • Page 124: Interrupt Sources

    Interrupt Sources I nt er r upt s our ces com pr i s e ext er nal i nt er r upt s ( I RQ 5 t o I RQ 0) and i nt er nal i nt er r upt s . 6.3.1 External Interrupts Ther e ar e s i x ext er nal i nt er r upt s our ces ;...
  • Page 125: Internal Interrupts

    Figure 6.3 shows the timing of IRQnF setting. Internal φ IRQn input pin IRQnF Figure 6.3 Timing of IRQnF Setting The vector num ber s f or I RQ 5 t o I RQ 0 i nt er r upt except i on handl i ng ar e 21 t o 26. U pon det ect i on of I RQ 5 t o I RQ 0 i nt er r upt s , t he appl i cabl e pi n i s s et i n t he por t r egi s t er 1 ( PM R1) as ,54Q pi n.
  • Page 126: Interrupt Exception Vector Table

    6.3.3 Interrupt Exception Vector Table Table 6.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Priorities among modules can be set by means of ICR. The situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 6.4.
  • Page 127 Origin of Vector Priority Interrupt Source Interrupt Source Vector Address Remarks  High Address trap H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F ICRA6 HSW1 Servo circuit H'0050 to H'0053 ICRA5 IRQ0 External pin H'0054 to H'0057 ICRA4 IRQ1 H'0058 to H'005B...
  • Page 128 Origin of Vector Priority Interrupt Source Interrupt Source Vector Address Remarks High ICXA Timer X1 H'00B0 to H'00B3 ICRC7 ICXB H'00B4 to H'00B7 ICXC H'00B8 to H'00BB ICXD H'00BC to H'00BF OCX1 H'00C0 to H'00C3 OCX2 H'00C4 to H'00C7 OVFX H'00C8 to H'00CB VD interrupts Sync signal...
  • Page 129: Interrupt Operation

    Interrupt Operation 6.4.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in this LSI differ depending on the interrupt control mode. NMI* interrupts and address trap interrupts are accepted at all times except in the reset state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt.
  • Page 130 Figure 6.4 shows a block diagram of the priority decision circuit. I C R Interrupt acceptance Default priority control and 3-level Vector number Interrupt source determination mask control Interrupt control modes 0 and 1 Figure 6.4 Block Diagram of Interrupt Priority Determination Operation •...
  • Page 131: Interrupt Control Mode 0

    Table 6.7 Operations and Control Signal Functions in Each Interrupt Control Mode Interrupt Acceptance Control, Interrupt Setting 3-Level Control Control Default Priority Mode INTM1 INTM0 Determination  ¡ ¡ ¡ ¡ Legend: ¡ : Interrupt operation control performed Used as interrupt mask bit Sets priority : Not used...
  • Page 132: Interrupt Control Mode 1

    Program execution state Interrupt generated? Address trap interrupt? Hold pending Control level 1 interrupt? H S W 1 H S W 1 H S W 2 H S W 2 I = 0 Save PC and CCR I ← 1 Read vector address Branch to interrupt handling routine Figure 6.5 Flowchart of Procedure Up to Interrupt Acceptance in...
  • Page 133 6.4.3 Interrupt Control Mode 1 Three-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by means of the I and UI bits in the CPU’s CCR and ICR. • Control level 0 interrupt requests are enabled when the I bit is cleared to 0, and disabled when set to 1.
  • Page 134 (1) If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. (2) When interrupt requests are sent to the interrupt controller, a control level 1 interrupt, according to the control level set in ICR, has priority for selection, and other interrupt requests are held pending.
  • Page 135 Program execution state Interrupt generated? Address trap interrupt? Hold pending Control level 1 interrupt? H S W 1 H S W 1 H S W 2 H S W 2 I = 0 I = 0 UI = 0 Save PC and CCR I ←...
  • Page 136: Interrupt Exception Handling Sequence

    6.4.4 Interrupt Exception Handling Sequence Figure 6.8 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control 0 is set in advanced mode, and the program area and stack area are in on- chip memory. Figure 6.8 Interrupt Exception Handling Rev.
  • Page 137: Interrupt Response Times

    6.4.5 Interrupt Response Times Table 6.8 shows interrupt response times-the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The symbols used in table 6.8 are explained in table 6.9. Table 6.8 Interrupt Response Times Number of States Advanced Mode...
  • Page 138: Usage Notes

    Usage Notes 6.5.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction.
  • Page 139: Instructions That Disable Interrupts

    6.5.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends.
  • Page 140: Rom

    Section 7 ROM Overview The H8S/2199 has 128 kbytes of on-chip ROM (flash memory or mask ROM), the H8S/2198 has 112 kbytes, the H8S/2197 has 96 kbytes, and the H8S/2196 has 80 kbytes*. The ROM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte and word data in one state, enabling faster instruction fetches and higher processing speed.
  • Page 141: Overview Of Flash Memory

    Overview of Flash Memory 7.2.1 Features The features of the flash memory are summarized below. • Four flash memory operating modes  Program mode  Erase mode  Program-verify mode  Erase-verify mode • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erasing is performed by block erase (in single-block units).
  • Page 142: Block Diagram

    : Flash memory control register 1 FLMCR2 : Flash memory control register 2 EBR1 : Erase block register 1 EBR2 : Erase block register 2 Figure 7.2 Block Diagram of Flash Memory (H8S/2199 Only) Rev. 1.0, 02/00, page 125 of 1141...
  • Page 143: Flash Memory Operating Modes

    7.2.3 Flash Memory Operating Modes Mode Transitions When each mode pin and the FWE pin are set in the reset state and a reset-start is executed, the MCU enters one of the operating modes shown in figure 7.3. In user mode, flash memory can be read but not programmed or erased.
  • Page 144 On-Board Programming Modes • Boot mode 2. Writing control program transfer 1. Initial state The flash memory is in the erased state when the When boot mode is entered, the boot program in device is shipped. The description here applies to this LSI chip (originally incorporated in the chip) is the case where the old program version or data is started, and SCI communication check is carried...
  • Page 145 • User program mode 1. Initial state 2. Programming/erase control program transfer When the FWE pin is driven high, user software (1) The FWE assessment program that confirms that confirms this fact, executes the transfer program in the the FWE pin has been driven high, and (2) the flash memory, and transfers the programming/erase program that will transfer the programming/erase control program to RAM.
  • Page 146 Differences between Boot Mode and User Program Mode Boot Mode User Program Mode Entire memory erase Block erase Programming control program* Program/program-verify Erase/erase-verify Program/program-verify Note: * To be provided by the user, in accordance with the recommended algorithm. Block Configuration The main ROM area is divided into three 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks.
  • Page 147: Pin Configuration

    7.2.4 Pin Configuration The flash memory is controlled by means of the pins shown in table 7.1. Table 7.1 Flash Memory Pins Pin Name Abbreviation Function Reset Input Reset Flash write enable Input Flash program/erase protection by hardware Mode 0 Input Sets this LSI operating mode Port 12...
  • Page 148: Flash Memory Register Descriptions

    Flash Memory Register Descriptions 7.3.1 Flash Memory Control Register 1 (FLMCR1) SWE1 ESU1 PSU1 Initial value —* Note: * Determined by the state of the FWE pin. FLMCR1 is an 8-bit register used for flash memory operating mode control. With addresses H'00000 to H'3FFFF, program-verify mode or erase-verify mode is entered by setting SWE to 1 when FWE = 1, then setting the PV1 bit and EV1 bit.
  • Page 149 Bit 6    Software Write Enable (SWE): Enables or disables flash memory programming. SWE should be set before setting bits 5 to 0, bits 7 to 0 in EBR1, and bits 3 to 0 in EBR2. Bit 6 SWE1 Description Writes are disabled...
  • Page 150 Bit 3    Erase-Verify (EV1): Selects erase-verify mode transition or clearing. Do not set the SWE1, ESU1, PSU1, PV1, E1, or P1 bit at the same time. Bit 3 Description Erase-verify mode cleared (Initial value) Transition to erase-verify mode [Setting condition] Setting is available when FWE = 1 and SWE = 1 are selected Bit 2...
  • Page 151: Flash Memory Control Register 2 (Flmcr2)

    7.3.2 Flash Memory Control Register 2 (FLMCR2) FLER SWE2 ESU2 PSU2 Initial value FLMCR2 is an 8-bit register used for flash memory operating control mode. With addresses H'40000 to H'47FFF, program-verify mode and erase-verify mode is entered by setting SWE2 when FWE (FLMCR1) = 1, then setting the EV2 bit and the PV2 bit. Program mode is entered by setting SWE2 when FWE (FLMCR1) = 1, then setting the SWE2 bit and PSU2 bit, and finally setting the P2 bit.
  • Page 152 Bit 6    Software Write Enable 2 (SWE2): Enables or disables flash memory programming (target address range: H'40000 to H'47FFF). SW2 should be set when setting bits 5 to 0 and bits 7 to 4 in EBR2. Bit 6 SWE2 Description Writes are disabled...
  • Page 153 Bit 2    Program-Verify 2 (PV2): Selects program-verify mode transition or clearing (target address range: H'40000 to H'47FFF). Do not set the ESU2, PSU2, EV2, E2, and P2 bits at the same time. Bit 2 Description Program-verify mode cleared Transition to program-verify mode [Setting condition] Setting is available when FWE=1 and SWE2=1 are selected...
  • Page 154: Erase Block Register 1 (Ebr1)

    7.3.3 Erase Block Register 1 (EBR1) EBR2 Initial value EBR1 is an 8-bit register that specify the flash memory erase area block by block. EBR1 is initialized to H'00 by a reset, in standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE1 bit in FLMCR1 is not set.
  • Page 155: Serial/Timer Control Register (Stcr)

    Table 7.3 Flash Memory Erase Blocks Block (Size) Address EB0 (4 kbytes) H'000000 to H'000FFF EB1 (4 kbytes) H'001000 to H'001FFF EB2 (4 kbytes) H'002000 to H'002FFF EB3 (4 kbytes) H'003000 to H'003FFF EB4 (4 kbytes) H'004000 to H'004FFF EB5 (4 kbytes) H'005000 to H'005FFF EB6 (4 kbytes) H'006000 to H'006FFF...
  • Page 156 Bit 3    Flash Memory Control Register Enable (FLSHE): Setting the FLSHE bit to 1 enables read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash memory control registers are deselected. In this case, the flash memory control register contents are retained.
  • Page 157: On-Board Programming Modes

    On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 7.4.
  • Page 158: Boot Mode

    7.4.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. When a reset-start is executed after the LSI’s pins have been set to boot mode, the boot program built into the MCU is started and the programming control program prepared in the host is serially transmitted to the LSI via the SCI.
  • Page 159 Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate This LSI measures low period of H'00 data transmitted by host This LSI calculates bit rate and sets value in bit rate register After bit rate adjustment, transmits one H'00 data byte to host to indicate end of adjustment...
  • Page 160 Automatic SCI Bit Rate Adjustment Start Stop Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 7.9 Automatic SCI Bit Rate Adjustment When boot mode is initiated, the LSI measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host.
  • Page 161 On-Chip RAM Area Divisions in Boot Mode: In boot mode, the TBD-byte area from TBD to TBD is reserved for use by the boot program, as shown in figure 7.10. The area to which the programming control program is transferred is TBD to TBD (TBD bytes). The boot program area can be used when the programming control program transferred into RAM enters the execution state.
  • Page 162 Notes on Use of Boot Mode: 1. When the chip comes out of reset in boot mode, it measures the low period of the input at the SCI's SI1 pin. The reset should end with SI1 pin high. After the reset ends, it takes about 100 states for the chip to get ready to measure the low period of the SI1 pin input.
  • Page 163: User Program Mode

    7.4.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of FWE control and supply of programming data, and storing a program/erase control program in part of the program area as necessary.
  • Page 164: Programming/Erasing Flash Memory

    Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. With addresses H'00000 to H'3FFFF, transitions to these modes can be made by setting the PSU1, ESU1, P1, E1, PV1 and EV1 bits in FLMCR1.
  • Page 165: Program-Verify Mode

    which the Pn bit is set is the flash memory programming time. Make a program setting for one programming operation using the table in the programming flowchart. 7.5.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory.
  • Page 166 Start Set SWE1 (2) bit in FLMCR(2) Wait 1 µs Store 128-byte program data in program data area and reprogram data area Programming pulse apply subroutine Enable WDT n= 1 m= 0 Set PSU1 (2) bit in FLMCR1 (2) Wait 50 µs Write 128-byte program data in RAM reprogram data area consecutevely to flash memory Set P1 (2) bit in FLMCR1 (2)
  • Page 167: Erase Mode (N = 1 When The Target Address Range Is H'00000 To H'3Ffff And N = 2 When The Target Address Range Is H'40000 To H'47Fff)

    7.5.3 Erase Mode (n = 1 when the target address range is H'00000 to H'3FFFF and n = 2 when the target address range is H'40000 to H'47FFF) Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 7.13.
  • Page 168 START Set SWE bit in FLMCR1 Wait 1 µs n = 1 Set EBR1 (2) Enable WDT Set ESU1 (2) bit in FLMCR1 (2) Wait 100 µs Start of erase Set E1 (2) bit in FLMCR1 (2) Wait 10 ms Halt erase Clear E1 (2) bit in FLMCR1 (2) Wait 10 µs...
  • Page 169: Erase-Verify Mode (N = 1 When The Target Address Range Is H'00000 To H'3Ffff And N = 2 When The Target Address Range Is H'40000 To H'47Fff)

    7.5.4 Erase-Verify Mode (n = 1 when the target address range is H'00000 to H'3FFFF and n = 2 when the target address range is H'40000 to H'47FFF) In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased.
  • Page 170: Flash Memory Protection

    Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 7.6.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2).
  • Page 171: Software Protection

    7.6.2 Software Protection Software protection can be implemented by setting the SWE1 bit in FLMCR1 and SWE2 bit in FLMCR2 and erase block registers 1 and 2 (EBR1, EBR2). When software protection is in effect, setting the P1 or E1 bit in flash memory control register 1 (FLMCR1) or P2 or E2 bit in flash memory control register 2 (FLMCR2) does not cause a transition to program mode or erase mode.
  • Page 172: Error Protection

    7.6.3 Error Protection In error protection, an error is detected when MCU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered.
  • Page 173: Interrupt Handling When Programming/Erasing Flash Memory

    Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI input is disabled when flash memory is being programmed or erased (when the P1 or E1 bit is set in FLMCR1, or the P2 or E2 bit is set in FLMR2), and while the boot program is executing in boot mode , to give priority to the program or erase operation.
  • Page 174: Flash Memory Writer Mode

    Figure 7.15 shows the memory map in writer mode. Table 7.8 Socket Adapter Product Codes Product Codes Package Socket Adapter Product Code HD64F2199 112-pin QFP H8S/2199 MCU mode Writer mode H'000000 H'00000 On-chip ROM area H'47FFF H'47FFF Figure 7.15 Memory Map in Writer Mode...
  • Page 175: Writer Mode Operation

    7.8.3 Writer Mode Operation Table 7.9 shows how the different operating modes are set when using writer mode, and table 7.10 lists the commands used in writer mode. Details of each mode are given below. • Memory Read Mode: Memory read mode supports byte reads. •...
  • Page 176: Memory Read Mode

    7.8.4 Memory Read Mode • After the end of an auto-program, auto-erase, or status read operation, the command wait state is entered. To read memory contents, a transition must be made to memory read mode by means of a command write before the read is executed. •...
  • Page 177 Table 7.12 AC Characteristics when Entering Another Mode from Memory Read Mode − − − − Preliminary − − − − = 5.0 V ±10%, V = 0 V, Ta = 25°C ±5°C Conditions: V Item Symbol Unit Notes  µs Command write cycle nxtc...
  • Page 178 − − − − Preliminary − − − − Table 7.13 AC Characteristics in Memory Read Mode (2) = 5.0 V ±10%, V = 0 V, Ta = 25°C ±5°C Conditions: V Item Symbol Unit Notes  µs Access time ...
  • Page 179: Auto-Program Mode

    7.8.5 Auto-Program Mode AC Characteristics − − − − Preliminary − − − − Table 7.14 AC Characteristics in Auto-Program = 5.0 V ±10%, V = 0 V, Ta = 25°C ±5°C Conditions: V Item Symbol Unit Notes  µs Command write cycle nxtc ...
  • Page 180 A18 to A0 ADDRESS STABLE nxtc nxtc Data transfer wsts 1 byte to 128 bytes (1 to 3,000 ms) write Programming operation end identification signal Programming normal end identification signal Programming wait H'40 DATA DATA IO5 to IO0 H'00 Figure 7.20 Auto-Program Mode Timing Waveforms Notes on Use of Auto-Program Mode •...
  • Page 181: Auto-Erase Mode

    7.8.6 Auto-Erase Mode AC Characteristics − − − − Preliminary − − − − Table 7.15 AC Characteristics in Auto-Erase Mode = 5.0 V ±10%, V = 0 V, Ta = 25°C ±5°C Conditions: V Item Symbol Unit Notes  µs Command write cycle nxtc...
  • Page 182: Status Read Mode

    Notes on Use of Erase-Program Mode • Auto-erase mode supports only entire memory erasing. • Do not perform a command write during auto-erasing. • Confirm normal end of auto-erasing by checking IO6. Alternatively, status read mode can also be used for this purpose (IO7 status polling uses the auto-erase operation end identification pin).
  • Page 183 A18 to A0 nxtc nxtc nxtc H'71 H'71 IO7 to IO0 DATA Note: IO2 and IO3 are undefined. Figure 7.22 Status Read Mode Timing Waveforms Table 7.17 Status Read Mode Return Commands Pin Name IO3 IO2 IO1   Attribute Normal end Command Programming...
  • Page 184: Status Polling

    7.8.8 Status Polling The IO7 status polling flag indicates the operating status in auto-program or auto-erase mode. The IO6 status polling flag indicates a normal or abnormal end in auto-program or auto-erase mode. Table 7.18 Status Polling Output Truth Table Internal Operation ...
  • Page 185: Writer Mode Transition Time

    Notes: 1. The flash memory is initially in the erased state when the device is shipped by Hitachi. For other chips for which the erasure history is unknown, it is recommended that auto- erasing be executed to check and supplement the initialization (erase) level.
  • Page 186: Notes When Converting The F-Ztat Application Software To The Mask-Rom Versions

    Notes when Converting the F–ZTAT Application Software to the Mask-ROM Versions Please note the following when converting the F-ZTAT application software to the mask-ROM versions. The values read from the internal registers for the flash ROM of the mask-ROM version and F–ZTAT version differ as follows.
  • Page 187: Ram

    The H8S/2199, H8S/2198, H8S/2197, and H8S/2196 have 3 kbytes of on-chip high-speed static RAM, and the H8S/2199 F-ZTAT has 8 kbytes. The on-chip RAM is connected to the CPU by a 16-bit data bus, enabling both byte data and word data to be accessed in one state. This makes it possible to perform fast word data transfer.
  • Page 188: Clock Pulse Generator

    Section 9 Clock Pulse Generator Overview This LSI has a built-in clock pulse generator (CPG) that generates the system clock (φ), the bus master clock, and internal clocks. The clock pulse generator consists of a system clock oscillator, a duty adjustment circuit, clock selection circuit, medium-speed clock divider, subclock oscillator, and subclock division circuit.
  • Page 189: Register Descriptions

    Register Descriptions 9.2.1 Standby Control Register (SBYCR) SSBY STS2 STS1 STS0 — — SCK1 SCK0 Initial value — — SBYCR is an 8-bit readable/writable register that performs power-down mode control. Only bits 0 and 1 are described here. For a description of the other bits, see section 4.2.1, Standby Control Register (SBYCR).
  • Page 190: Low-Power Control Register (Lpwrcr)

    9.2.2 Low-Power Control Register (LPWRCR) DTON LSON NESEL — — — Initial value — — — LPWRCR is an 8-bit readable/writable register that performs power-down mode control. Only bit 1 and 0 is described here. For a description of the other bits, see section 4.2.2, Low- Power Control Register (LPWRCR).
  • Page 191: Oscillator

    Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 9.3.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as shown in the example in figure 9.2. An AT-cut parallel-resonance crystal should be used. OSC1 = 10 to 22pF L1 =...
  • Page 192 Note on Board Design: When a crystal resonator is connected, the following points should be noted. Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 9.4. When designing the board, place the crystal resonator and its load capacitors as close as possible to the OSC1 and OSC2 pins.
  • Page 193: External Clock Input

    9.3.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 9.5. If the OSC2 pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode, subactive mode, subsleep mode, and watch mode.
  • Page 194 External Clock: The external clock signal should have the same frequency as the system clock (φ). Table 9.3 and figure 9.6 show the input conditions for the external clock. Table 9.3 External Clock Input Conditions = 4.0 to 5.5 V Item Symbol Unit...
  • Page 195 Table 9.4 External Clock Output Settling Delay Time Conditions: V = 4.0 V to 5.5 V, AV = 4.0 V to 5.5 V, V = AV = 0 V Item Symbol Unit Notes  µs External clock output settling Figure 9.7 DEXT delay time of 5(6 pulse width (t...
  • Page 196: Duty Adjustment Circuit

    Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (φ). Medium-Speed Clock Divider The medium-speed divider divides the system clock to generate φ/16, φ/32, and φ/64 clocks. Bus Master Clock Selection Circuit The bus master clock selection circuit selects the system clock (φ) or one of the medium-speed clocks (φ/16, φ/32 or φ/64) to be supplied to the bus master (CPU), according to the settings of bits...
  • Page 197: Subclock Oscillator Circuit

    Subclock Oscillator Circuit 9.7.1 Connecting 32.768 kHz Crystal Resonator When using a subclock, connect a 32.768 kHz crystal resonator to X1 and X2 pins as shown in figure 9.8. For precautions on connecting, see Note on Board Design, in section 9.3.1 Connecting a Crystal Resonator.
  • Page 198: When Subclock Is Not Needed

    9.7.2 When Subclock is not Needed Connect X1 pin to V , and X2 pin should remain open as shown in figure 9.10. Open Figure 9.10 Terminal When Subclock is not Needed Subclock Waveform Shaping Circuit To eliminate noise in the subclock input from the X1 pin, this circuit samples the clock using a clock obtained by dividing the φ...
  • Page 199: Section 10 I/O Port

    Section 10 I/O Port 10.1 Overview 10.1.1 Port Functions This LSI has seven 8-bit I/O ports (including one CMOS high-current port), and one 8-bit input port. Table 10.1 shows the functions of each port. Each I/O part a port control register (PCR) that controls an input and output and a port data register (PDR) for storing output data.
  • Page 200 Table 10.1 Port Functions Function Switching Port Description Pins Alternative Functions Register Port 0 P07 to P00 input- P07/AN7 to Analog data input channels 7 to 0 PMR0 only ports P00/AN0 Port 1 P17 to P10 I/O ports P17/TMOW Prescalar unit frequency division clock PMR1 (Built-in MOS pull-up output...
  • Page 201 Function Switching Port Description Pins Alternative Functions Register Port 8 P87 to P80 I/O ports P87/DPG PMR8 DPG signal input PMRC P86/EXTTRG External trigger signal input P85/COMP/B Pre-amplifier output result signal input Color signal output (B) P84/H.AMP Pre-amplifier output select signal SW/G input Color signal output (G)
  • Page 202: Mos Pull-Up Transistors

    10.1.3 MOS Pull-Up Transistors The MOS pull-up transistors in ports 1 to 3 can be switched on or off by the MOS pull-up select registers 1 to 3 (PUR1 to PUR3) in units of bits. Settings in PUR1 to PUR3 are valid when the pin function is set to an input by PCR1 to PCR3.
  • Page 203: Port 0

    10.2 Port 0 10.2.1 Overview Port 0 is an 8-bit input-only port. Table 10.2 shows the port 0 configuration. Port 0 consists of pins that are used both as standard input ports (P07 to P00) and analog input channels (AN7 to AN0). It is switched by port mode register 0 (PMR0). Table 10.2 Port 0 Configuration Port Function...
  • Page 204: Register Configuration

    10.2.2 Register Configuration Table 10.3 shows the port 0 register configuration. Table 10.3 Port 0 Register Configuration Name Abbrev. Size Initial Value Address* Port mode register 0 PMR0 Byte H'00 H'FFCD  Port data register 0 PDR0 Byte H'FFC0 Note: * Lower 16 bits of the address. (1) Port Mode Register 0 (PMR0) Bit : PMR07...
  • Page 205: Pin Functions

    (2) Port Data Register 0 (PDR0) PDR07 PDR06 PDR05 PDR04 PDR03 PDR02 PDR01 PDR00 Initial value : — — — — — — — — R/W : Port data register 0 (PDR0) reads the port states. When the corresponding bit of PMR0 is 0 (general input port), the pin state is read if PDR0 is read.
  • Page 206: Port 1

    10.3 Port 1 10.3.1 Overview Port 1 is an 8-bit I/O port. Table 10.5 shows the port 1 configuration. Port 1 consists of pins that are used both as standard I/O ports (P17 to P10) and frequency division clock output (TMOW), input capture input (,&), or external interrupt request inputs (,548 to ,543).
  • Page 207 Port Mode Register 1 (PMR1) Bit : PMR17 PMR16 PMR15 PMR14 PMR13 PMR12 PMR11 PMR10 Initial value : R/W : Port mode register 1 (PMR1) controls switching of each pin function of port 1. The switching is specified in a unit of bit. PMR1 is an 8-bit read/write enable register.
  • Page 208 Bit 7    P17/TMOW Pin Switching (PMR17): PMR17 sets whether the P17/TMOW pin is used as a P17 I/O pin or a TMOW pin for the frequency division clock output. Bit 7 PMR17 Description The P17/TMOW pin functions as a P17 I/O pin (Initial value) The P17/TMOW pin functions as a TMOW output pin Bit 6...
  • Page 209 Bits 7 to 0    P17 to P10 Pin Switching (PCR17 toPCR10) Bit n PCR1n Description The P1n pin functions as an input pin (Initial value) The P1n pin functions as an output pin (n = 7 to 0) Port Data Register 1 (PDR1) Bit : PDR17...
  • Page 210: Pin Functions

    10.3.3 Pin Functions This section describes the port 1 pin functions and their selection methods. P17/TMOW: P17/TMOW is switched as shown below according to the PMR17 bit in PMR1 and the PCR17 bit in PCR1. PMR17 PCR17 Pin Function P17 input pin P17 output pin TMOW output pin Note: * Don’t care...
  • Page 211 10.3.4 Pin States Table 10.7 shows the port 1 pin states in each operation mode. Table 10.7 Port 1 Pin States Pins Reset Active Sleep Standby Watch Subactive Subsleep P17/TMOW High- Operation Holding High- High- Operation Holding P16/,& impedance impedance impedance P15/,548 P10/,543...
  • Page 212: Port 3

    10.4 Port 2 10.4.1 Overview Port 2 is an 8-bit I/O port. Table 10.8 shows the port 2 configuration. Port 2 consists of pins that are used both as standard I/O ports (P27 to P20) and SCI clock I/O (SCK1), receive data input (SI1), send data output (SO1), I C bus interface clock I/O (SCL0, SCL1), or data I/O (SDA0, SDA1).
  • Page 213 Port Control Register 2 (PCR2) Bit : PCR27 PCR26 PCR25 PCR24 PCR23 PCR22 PCR21 PCR20 Initial value : R/W : Port control register 2 (PCR2) controls the I/Os of pins P27 to P20 of port 2 in a unit of bit. When PCR2 is set to 1, the corresponding P27 to P20 pins become output pins, and when it is set to 0, they become input pins.
  • Page 214 MOS Pull-Up Select Register 2 (PUR2) Bit : PUR27 PUR26 PUR25 PUR24 PUR23 PUR22 PUR21 PUR20 Initial value : R/W : MOS pull-up selector register 2 (PUR2) controls the ON and OFF of the MOS pull-up transistor of port 2. Only the pin whose corresponding bit of PCR2 was set to 0 (input) becomes valid. If the corresponding bit of PCR2 is set to 1 (output), the corresponding bit of PUR2 becomes invalid and the MOS pull-up transistor is turned off.
  • Page 215: Pin Functions

    10.4.3 Pin Functions This section describes the port 2 pin functions and their selection methods. P27/SYNCI: P27/SYNCI is switched as shown below according to the PCR27 bit in PCR2. Pin Function P27 input pin P27 output pin Note: Because the SYNCI always functions, the alternative pin need always be set to the high or low level regardless of active mode or low power consumption mode.
  • Page 216 P23/SDA1: P23/SDA1 is switched as shown below according to the PCR23 bit in PCR2 and the II1CE bit in the I C Bus control register (ICCR1). II1CE PCR23 Pin Function P23 input pin P23 output pin SDA1 I/O pin Note: * Don’t care P22/SCK1: P22/SCK1 is switched as shown below according to the PCR22 bit in PCR2, the C/$ bit in SMR, and the CKE1 and CKE0 bits in SCR.
  • Page 217: Pin States

    10.4.4 Pin States Table 10.10 shows the port 2 pin states in each operation mode. Table 10.10 Port 2 Pin States Pins Reset Active Sleep Standby Watch Subactive Subsleep P27/SYNCI High- Operation Holding High- High- Operation Holding P26/SCL0 impedance impedance impedance P25/SDA0 P24/SCL1...
  • Page 218: Port 4

    10.5 Port 3 10.5.1 Overview Port 3 is an 8-bit I/O port. Table 10.11 shows the port 3 configuration. Port 3 consists of pins that are used both as standard I/O ports (P37 to P30) and timer J timer output (TMO), buzzer output (BUZZ), 8-bit PWM outputs (PWM3 to PWM0), SCI2 strobe output (STRB), or chip select input (&6).
  • Page 219 Port Mode Register 3 (PMR3) Bit : PMR37 PMR36 PMR35 PMR34 PMR33 PMR32 PMR31 PMR30 Initial value : R/W : Port mode register 3 (PMR3) controls switching of each pin function of port 3. The switching is specified in a unit of bit. PMR3 is an 8-bit read/write enable register.
  • Page 220 Bits 5 to 2    P35/PWM3 to P32/PWM0 Pin Switching (PMR35 to PMR32): PMR35 to PMR32 set whether the P3n/PWMm pin is used as a P3n I/O pin or a PWMm pin for the 8-bit PWM output. Bit n PMR3n Description The P3n/PWMm pin functions as a P3n I/O pin...
  • Page 221 Port Control Register 3 (PCR3) Bit : PCR37 PCR36 PCR35 PCR34 PCR33 PCR32 PCR31 PCR30 Initial value : R/W : Port control register 3 (PCR3) controls the I/Os of pins P37 to P30 of port 3 in a unit of bit. When PCR3 is set to 1, the corresponding P37 to P30 pins become output pins, and when it is set to 0, they become input pins.
  • Page 222: Pin Functions

    MOS Pull-Up Select Register 3 (PUR3) Bit : PUR37 PUR36 PUR35 PUR34 PUR33 PUR32 PUR31 PUR30 Initial value : R/W : MOS pull-up selector register 3 (PUR3) controls the ON and OFF of the MOS pull-up transistor of port 3. Only the pin whose corresponding bit of PCR3 was set to 0 (input) becomes valid. If the corresponding bit of PCR3 is set to 1 (output), the corresponding bit of PUR3 becomes invalid and the MOS pull-up transistor is turned off.
  • Page 223 P36/BUZZ: P36/BUZZ is switched as shown below according to the PMR36 bit in PMR3 and the PCR36 bit in PCR3. PMR36 PCR36 Pin Function P36 input pin P36 output pin BUZZ output pin Note: * Don’t care P35/PWM3: P35/PWM3 is switched as shown below according to the PMR3n bit in PMR3 and the PCR3n bit in PCR3.
  • Page 224 P32/PWM0: P32/PWM0 is switched as shown below according to the PMR32 bit in PMR3 and the PCR32 bit in PCR. PMR32 PCR32 Pin Function P32 input pin P32 output pin PWM0 output pin P31/SV2: P31/SV2 is switched as shown below according to the PMR31 bit in PMR3 and the PCR31 bit in PCR3.
  • Page 225: Pin States

    10.5.4 Pin States Table 10.13 shows the port 3 pin states in each operation mode. Table 10.13 Port 3 Pin States Pins Reset Active Sleep Standby Watch Subactive Subsleep P37/TMO High- Operation Holding High- High- Operation Holding P36/BUZZ impedance impedance impedance P35/PWM3 P32/PWM0...
  • Page 226 10.6 Port 4 10.6.1 Overview Port 4 is an 8-bit I/O port. Table 10.14 shows the port 4 configuration. Port 4 consists of pins that are used both as standard I/O ports (P47 to P40) and output compare output (FTOA, FTOB), input capture input (FTIA, FTIB, FTIC, FTID) or 14-bit PWM output (PWM14).
  • Page 227 Port Mode Register 4 (PMR4) Bit : PMR40 PMR47 — — — — — — Initial value : R/W : — — — — — — Port mode register 4 (PMR4) controls switching of the P47/RPTRG pin and the P40/PWM14 pin function.
  • Page 228 Port Control Register 4 (PCR4) Bit : PCR47 PCR46 PCR45 PCR44 PCR43 PCR42 PCR41 PCR40 Initial value : R/W : Port control register 4 (PCR4) controls the I/Os of pins P47 to P40 of port 4 in a unit of bit. When PCR4 is set to 1, the corresponding P47 to P40 pins become output pins, and when it is set to 0, they become input pins.
  • Page 229 10.6.3 Pin Functions This section describes the port 4 pin functions and their selection methods. P47/RPTRG: P47/RPTRG is switched as shown below according to the PMR47 bit in PMR4 and the PMR47 bit in PMR4 and the PCR47 bit in PCR4. PMR47 PCR47 Pin Function...
  • Page 230 P43/FTIC: P43/FTIC is switched as shown below according to the PCR43 bit in PCR4. PCR43 Pin Function P43 input pin FTIC input pin P43 output pin P42/FTIB: P42/FTIB is switched as shown below according to the PCR42 bit in PCR4. PCR42 Pin Function P42 input pin...
  • Page 231 10.6.4 Pin States Table 10.16 shows the port 4 pin states in each operation mode. Table 10.16 Port 4 Pin States Pins Reset Active Sleep Standby Watch Subactive Subsleep High- Operation Holding High- High- Operation Holding P46/FTOB impedance impedance impedance P45/FTOA P44/FTID P43/FTIC...
  • Page 232: Port 6

    10.7 Port 6 10.7.1 Overview Port 6 is an 8-bit I/O port. Table 10.17 shows the port 6 configuration. Port 6 is a large current I/O port. The synchronous current is 20 mA maximum (VOL=1.5 V) and four pins can be turned on at the same time.
  • Page 233: Register Configuration

    10.7.2 Register Configuration Table 10.18 shows the port 6 register configuration. Table 10.18 Port 6 Register Configuration Name Abbrev. Size Initial Value Address* Port mode register 6 PMR6 Byte H'00 H'FFDD Port mode register A PMRA Byte H'3F H'FFD9 Port control register 6 PCR6 Byte H'00...
  • Page 234 Port Mode Register A (PMRA) Bit : PMRA7 PMRA6 — — — — — — Initial value : R/W : — — — — — — Port mode register A (PMRA) switches the pin functions in port 6. Switching is specified in a unit of bit.
  • Page 235 Port Control Register 6 (PCR6) Bit : PCR67 PCR66 PCR65 PCR64 PCR63 PCR62 PCR61 PCR60 Initial value : R/W : Port control register 6 (PCR6) selects the general I/O of port 6 and controls the realtime output in a unit of bit together with PMR6. When PMR6 = 0, the corresponding P67 to P60 pins become general output pins if PCR6 is set to 1, and they become general input pins if it is set to 0.
  • Page 236 Realtime Output Trigger Select Register (RTPSR1) Bit : RTPSR17 RTPSR16 RTPSR15 RTPSR14 RTPSR13 RTPSR12 RTPSR11 RTPSR10 Initial value : R/W : The realtime output trigger select register (RTPSR1) sets whether the external trigger (RPTRG pin input) or the internal trigger (HSW) is used as an trigger input for the realtime output in a unit of bit.
  • Page 237 Real Time Output Trigger Edge Select Register (RTPEGR) Bit : — — — — — — RTPEGR1 RTPEGR0 Initial value : R/W : — — — — — — The realtime output trigger edge select register (RTPEGR) specifies the edge sense of the external or internal trigger input for the realtime output.
  • Page 238 10.7.3 Pin Functions This section describes the port 6 pin functions and their selection methods. P67/RP7/TMBI: P67/RP7/TMBI is switched as shown below according to the PMRA7 bit in PMRA, PMR67 bit in PMR6, and PCR67 bit in PCR6. Value When PDR6n PMRA7 PMR67 PCR67...
  • Page 239: Pin Functions

    P65/RP5 to P60/RPD: P65/RP5 to P60/RPD are switched below according to the PMRAn bit in PMRA, PMR6n bit in PMR6, and PCR6n bit in PCR6. PMR6n PCR6n Pin Function Output Value Value When PDR6n Was Read  P6n input pin P6n pin P6n output pin PDR6n...
  • Page 240: Operation

    10.7.4 Operation Port 6 can be used as a realtime output port or general I/O output port by PMR6. Port 6 functions as a realtime output port when PMR6 = 1 and as a general I/O port when PMR6 = 0. The operation per port 6 function is shown below.
  • Page 241: Pin States

    • Operation of the Realtime Output Port (PMR6 = 1) When PMR6 is 1, it operates as a realtime output port. When a trigger is input, the PDR6 data is transferred to PDRS6 and the PCR6 is transferred data to PCRS6, respectively. In this case, when PCRS6 is 1, the PDRS6 data of the corresponding bit is output to the RP pin.
  • Page 242: Port 7

    10.8 Port 7 10.8.1 Overview Port 7 is an 8-bit I/O port. Table 10.20 shows the port 7 configuration. Port 7 consists of pins that are used both as standard I/O ports (P77 to P70) and HSW timing generation circuit (programmable pattern generator: PPG) outputs (PPG7 to PPG0). It is switched by port mode register 7 (PMR7) and port control register 7 (PCR7).
  • Page 243: Register Configuration

    10.8.2 Register Configuration Table 10.21 shows the port 7 register configuration. Table 10.21 Port 7 Register Configuration Name Abbrev. Size Initial Value Address* Port mode register 7 PMR7 Byte H'00 H'FFDE Port mode register B PMRB Byte H'0F H'FFDA Port control register 7 PCR7 Byte H'00...
  • Page 244 Port Mode Register 7 (PMR7) Bit : PMR77 PMR76 PMR75 PMR74 PMR73 PMR72 PMR71 PMR70 Initial value : R/W : Port mode register 7 (PMR7) controls switching of each pin function of port 7. The switching is specified in a unit of bit. PMR7 is an 8-bit read/write enable register.
  • Page 245 Bits 7 to 4    P77/RP7B to P74/RP8 Pin Switching (PMRB7 to PMRB4): P77/RP7B to P74/RP8 set whether the P7n/RPm pin is used as a P7n I/O pin or a RPm pin for the realtime output port. (n= 7 to 4 and m= B, A, 9, or 8) Bit n PMRBn Description...
  • Page 246 Port Data Register 7 (PDR7) Bit : PDR77 PDR76 PDR75 PDR74 PDR73 PDR72 PDR71 PDR70 Initial value : R/W : Port data register 7 (PDR7) stores the data for the pins P77 to P70 of port 7. If PCR7 is 1 (output) when PMRB=0, the PDR7 values are directly read when port 7 is read. Accordingly, the pin states are not affected.
  • Page 247 Bits 7 to 4    RPB to RP8 Pin Trigger Switching (RTPSR27 to RTPSR24) Bit7 RTPSR2n Description Selects external trigger (RPTRG pin input) for trigger input (Initial value) Selects internal trigger (HSW) for trigger input (n = 7 to 4) Realtime Output Trigger Edge Selection Register (RTPEGR) Bit : —...
  • Page 248: Pin Functions

    10.8.3 Pin Functions This section describes the port 7 pin functions and their selection methods. P77/PPG7/RPB to P74/PPG4/RP8: P77/PPG7/RPB to P74/PPG4/RP8 are switched as shown below according to the PMRBn bit in PMRB and the PCR7n bit in PCR7. Value Returned when PMRBn PMR7n PCR7n...
  • Page 249: Operation

    10.8.4 Operation Port 7 can be used by the PMRB as a realtime output port or an I/O port. Port 7 functions as a realtime output port when PMRB=1 and functions as an I/O port when PMRB=0. Figure 10.3 show the block diagram of port 7. Internal trigger HSW RTPEGR write...
  • Page 250: Pin States

    Port 7 functions as follows: 1. Realtime output port function (PMRB=1) Port function as a realtime output port when PMRB is 1. After a trigger input, the PDR7 data is transferred to PDRS7 and PCR7 data is transferred to PCRS7. In this case, when PCRS7 is 1, the PDRS7 data of the corresponding bit is output from the RP pin.
  • Page 251: Port 8

    10.9 Port 8 10.9.1 Overview Port 8 is an 8-bit I/O port. Table 10.23 shows the port 8 configuration. Port 8 consists of pins that are used both as standard-current I/O ports (P87 to P80) and an external CTL signal input (EXCTL), a pre-amplifier output result signal input (COMP), color signal outputs (R, G, and B), a pre-amplifier output selection signal output (H.Amp SW), a control signal output for processing color signal (C.Rotary), a DPG signal input (DPG), a capstan external sync signal input (EXCAP), an OSD character display position output (YB0), an OSD character data...
  • Page 252: Register Configuration

    10.9.2 Register Configuration Table 10.24 shows the port 8 register configuration. Table 10.24 Port 8 Register Configuration Name Abbrev. Size Initial Value Address* Port mode register 8 PMR8 Byte H'00 H'FFDF Port mode register C PMRC Byte H'C5 H'FFE0 Port control register 8 PCR8 Byte H'00...
  • Page 253 Port Mode Register 8 (PMR8) Bit : PMR87 PMR86 PMR85 PMR84 PMR83 PMR82 PMR81 PMR80 Initial value : R/W : Port mode register 8 (PMR8) controls switching of each pin function of port 8. The switching is specified in a unit of bit. PMR8 is an 8-bit read/write enable register.
  • Page 254 Bit 4    P84/H.Amp SW Pin Switching (PMR84): PMR84 sets whether the P84/H.Amp SW pin is used as a P84 I/O pin or H.Amp SW pin of the preamplifier output select signal output. Bit 4 PMR84 Description P84/H.Amp SW pin functions as a P84 I/O pin (Initial value) P84/H.Amp SW pin functions as a H.Amp SW output pin Bit 3...
  • Page 255 Port Mode Register C (PMRC) Bit : — — PMRC5 PMRC4 PMRC3 — PMRC1 — Initial value : R/W : — — — — Port mode register C (PMRC) controls switching of each pin function of port 8. The switching is specified in a unit of a bit.
  • Page 256 Bit 1    P81/YB0 Pin Switching (PMRC1): PMRC1 sets whether to use the P81/YB0 pin as a P81 I/O pin or a YB0 pin of the OSD character display position output. Bit7 PMR1 Description P81/YB0 pin functions as a P81 I/O pin (Initial value) P81/YB0 pin functions as a YB0 output pin Port Control Register 8 (PCR8)
  • Page 257 Port Data Register 8 (PDR8) Bit : PDR87 PDR86 PDR85 PDR784 PDR83 PDR82 PDR81 PDR80 Initial value : R/W : Port data register 8 (PDR8) stores the data of pins P87 to P80 port 8. When PCR is 1 (output), the pin states are read is port 8 is read.
  • Page 258: Pin Functions

    10.9.3 Pin Functions This section describes the port 8 pin functions and their selection methods. P87/DPG: P87/DPG is switched as shown below according to the PMR87 bit in PMR8 and PCR87 bit in PCR8. PMR87 PCR87 Pin Function P87 input pin P87 output pin DPG input pin P86/EXTTRG: P86/EXTTRG is switched as shown below according to the PMR86 bit in PMR8...
  • Page 259 P83/C.Rotary/R: P83/C.Rotary/R is switched as shown below according to the PMR83bit in PMR8, PMRC3 bit in PMRC, and PCR83 bit in PCR8. PMRC3 PMR83 PCR83 Pin Function P83 input pin P83 output pin C.Rotary output pin R output pin P82/EXCTL: P82/EXCTL is switched as shown below according to the PMR82 bit in PMR8 and PCR82 bit in PCR8.
  • Page 260: Pin States

    10.9.4 Pin States Table 10.25 shows the port 8 pin states in each operation mode. Table 10.25 Port 8 Pin States Pins Reset Active Sleep Standby Watch Subactive Subsleep P87/DPG High- Operation Holding High- High- Operation Holding P86/ impedance impedance impedance EXTTRG P85/COMP/...
  • Page 261: Section 11 Timer A

    Section 11 Timer A 11.1 Overview Timer A is an 8-bit interval timer. It can be used as a clock timer when connected to a 32.768 kHz crystal oscillator. 11.1.1 Features Features of timer A are as follows: • Choices of eight different types of internal clocks (φ/16384, φ/8192, φ/4096, φ/1024, φ/512, φ/256, φ/64 and φ/16) are available for your selection.
  • Page 262: Block Diagram

    11.1.2 Block Diagram Figure 11.1 shows a block diagram of timer A. 32 kHz Prescaler W φw Crystal oscillator (PSW) φw/128 Overflowing of φ/16384, φ/8192, the interval timer φ/4096, φ/1024, φ/512, φ/256, φ/64, φ/16 Prescaler S System φ Interrupting (PSS) clock Interrupt circuit...
  • Page 263: Register Descriptions

    11.2 Register Descriptions 11.2.1 Timer Mode Register A (TMA) Bit : — — TMAOV TMAIE TMA3 TMA2 TMA1 TMA0 Initial value : — — R/W : R/(W)* Note: * Only 0 can be written to clear the flag. The timer mode register A (TMA) works to control the interrupts of timer A and to select the input clock.
  • Page 264 Bit 3    Selection of the Clock Source and Prescaler (TMA3): This bit works to select the PSS or PSW as the clock source for the Timer A. Bit 3 TMA3 Description Selects the PSS as the clock source for the Timer A (Initial value) Selects the PSW as the clock source for the Timer A Bits 2 to 0...
  • Page 265: Timer Counter A (Tca)

    11.2.2 Timer Counter A (TCA) Bit : TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initial value : R/W : The timer counter A (TCA) is an 8-bit up-counter that counts up on inputs from the internal clock. The inputting clock can be selected by TMA3 to TMA0 bits of the TMA When the TCA overflows, the TMAOV bit of the TMA is set to 1.
  • Page 266: Operation

    11.3 Operation Timer A is an 8-bit interval timer. It can be used as a clock timer when connected to a 32.768 kHz crystal oscillator. 11.3.1 Operation as the Interval Timer When the TMA3 bit of the TMA is cleared to 0, timer A works as an 8-bit interval timer. After reset, the TCA is cleared to H'00 and as the TMA3 bit is cleared to 0, the Timer A continues counting up as the interval counter without interrupts right after resetting.
  • Page 267: Section 12 Timer B

    Section 12 Timer B 12.1 Overview Timer B is an 8-bit up-counter. Timer B is equipped with two different types of functions namely, the interval function and the auto reloading function. 12.1.1 Features • Seven different types of internal clocks (φ/16384, φ/4096, φ/1024, φ/512, φ/128, φ/32 and φ/8) or an of external clock can be selected.
  • Page 268: Pin Configuration

    12.1.3 Pin Configuration Table 12.1 shows the pin configuration of timer B. Table 12.1 Pin Configuration Name Abbrev. Function Event inputs to timer B TMBI Input Event input pin for inputs to the TCB 12.1.4 Register Configuration Table 12.2 shows the register configuration of timer B. The TCB and TLB are being allocated to the same address.
  • Page 269 12.2 Register Descriptions 12.2.1 Timer Mode Register B (TMB) Bit : — — TMB17 TMBIF TMBIE TMB12 TMB11 TMB10 Initial value : R/W : R/(W)* — — Note: * Only 0 can be written to clear the flag. The TMB is an 8-bit read/write register which works to control the interrupts, to select the auto reloading function and to select the input clock.
  • Page 270 Bit 5    Enabling Interrupt of the Timer B (TMBIE): This bit works to permit/prohibit occurrence of interrupt of timer B when the TCB overflows and when the TMBIF is set to 1. Bit 5 TMBIE Description Prohibits interrupt of timer B (Initial value) Permits interrupt of timer B Bits 4 and 3...
  • Page 271: Timer Counter B (Tcb)

    12.2.2 Timer Counter B (TCB) Bit : TCB17 TCB16 TCB15 TCB14 TCB13 TCB12 TCB11 TCB10 Initial value : R/W : The TCB is an 8-bit readable register which works to count up by the internal clock inputs and external event inputs. The input clock can be selected by the TMB12 to TMB10 of the TMB. When the TCB overflows (H'FF →...
  • Page 272: Port Mode Register A (Pmra)

    12.2.4 Port Mode Register A (PMRA) Bit : — — — PMRA7 PMRA6 — — — Initial value : — — — — — — R/W : The port mode register A (PMRA) works to changeover the pin functions of the port 6 and to designate the edge sense of the event inputs of timer B (TMBI).
  • Page 273: Module Stop Control Register (Mstpcr)

    12.2.5 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode. When the MSTP14 bit is set to 1, the Timer B stops its operation at the ending point of the bus cycle to shift to the module stop mode.
  • Page 274: Operation

    12.3 Operation 12.3.1 Operation as the Interval Timer When the TMB17 bit of the TMB is set to 0, timer B works as an 8-bit interval timer. When reset, since the TCB is cleared to H'00 and as the TMB17 bit is cleared to 0, timer B continues counting up as the interval timer without interrupts right after resetting.
  • Page 275: Section 13 Timer J

    Section 13 Timer J 13.1 Overview Timer J consists of twin counters. It carries different operation modes such as reloading and event counting. 13.1.1 Features Timer J consists of an 8-bit reloading timer and an 8-bit/16-bit selectable reloading timer. It has various functions as listed below.
  • Page 276 BUZZ REMOout Toggle Edge detection Toggle 8/16 Reloading register Synchronization PS11,10 Figure 13.1 Block Diagram of timer J Rev. 1.0, 02/00, page 262 of 1141...
  • Page 277: Pin Configuration

    13.1.3 Pin Configuration Table 13.1 shows the pin configuration of timer J. Table 13.1 Pin Configuration Name Abbrev. Function ,544 Event input pin Input Event inputs to the TMJ-1 ,545 Event input pin Input Event inputs to the TMJ-2 13.1.4 Register Configuration Table 13.2 shows the register configuration of timer J.
  • Page 278 13.2 Register Descriptions 13.2.1 Timer Mode Register J (TMJ) Bit : PS11 PS10 8/16 PS21 PS20 Initial value : R/W : The timer mode register J (TMJ) works to select the inputting clock for the TMJ-1 and TMJ-2 and to set the operation mode. The TMJ is an 8-bit register and bit 1 is for read only.
  • Page 279 Bit 5    Starting the Remote Controlled Operation (ST): This bit works to start the remote controlled operations. When this bit is set to 1, clock signal is supplied to the TMJ-1 to start signal transmissions. When this bit is cleared to 0, clock supply stops to discontinue the operation. The ST bit will be valid under the remote controlling mode, namely, when bit 0 (T/R bit) is 1 and bit 4 (8/16 bit) is 0.
  • Page 280 Bit 0    Switching Over Between Timer Output/Remote Controlling Output (T/R): This bit works to select if using the timer outputs from the TMJ-1 as the output signal through the TMO pin or if using the toggle outputs (remote controlled transmission data) from the TMJ-2 as the output signal through the TMO pin.
  • Page 281: Timer J Control Register (Tmjc)

    13.2.2 Timer J Control Register (TMJC) Bit : PS22 BUZZ1 BUZZ0 MON1 MON0 TMJ2IE TMJ1IE Initial value : R/W : The timer J control register (TMJC) works to select the buzzer output frequency and to control permission/prohibition of interrupts. The TMJC is an 8-bit read/write register. When reset, the TMJC is initialized to H'09.
  • Page 282 Bits 5 and 4    Selecting the Monitor Signals (MON1 or MON0): These bits work to select the type of signals being output through the BUZZ pin for monitoring purpose. These settings are valid only when the BUZZ1 and BUZZ0 bits are being set to 10. When PB-CTL or REC-CTL is chosen, signal duties will be output as they are.
  • Page 283 Bit 1    Enabling Interrupt of the TMJ1I (TMJ1IE): This bit works to permit/prohibit occurrence of TMJ1I interrupt of the TMJS in 1-set of the TMJ1I. Bit 1 TMJ1IE Description Prohibits occurrence of TMJ1I interrupt (Initial value) Permits occurrence of TMJ1I interrupt Bit 0...
  • Page 284: Timer J Status Register (Tmjs)

    13.2.3 Timer J Status Register (TMJS) Bit : TMJ2I TMJ1I — — — — — — Initial value : — — — — — — R/(W)* R/(W)* R/W : Note: * Only 0 can be written to clear the flag. The timer J status register (TMJS) works to indicate issuance of the interrupt request of timer J.
  • Page 285: Timer Counter J (Tcj)

    13.2.4 Timer Counter J (TCJ) Bit : TDR17 TDR16 TDR15 TDR14 TDR13 TDR12 TDR11 TDR10 Initial value : R/W : The timer counter J (TCJ) is an 8-bit readable down-counter which works to count down by the internal clock inputs or external clock inputs. The inputting clock can be selected by the PS11 and PS10 bits of the TMJ.
  • Page 286: Timer Load Register J (Tlj)

    13.2.6 Timer Load Register J (TLJ) Bit : TLR17 TLR16 TLR15 TLR14 TLR13 TLR12 TLR11 TLR10 Initial value : R/W : The timer load register J (TLJ) is an 8-bit write only register which works to set the reloading value of the TCJ. When the reloading value is set to the TLJ, the value will be simultaneously loaded to the TCJ and the TCJ starts counting down from the set value.
  • Page 287: Module Stop Control Register (Mstpcr)

    13.2.8 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode. When the MSTP13 bit is set to 1, timer J stops its operation at the ending point of the bus cycle to shift to the module stop mode.
  • Page 288: Operation

    13.3 Operation 13.3.1 8-bit Reload Timer (TMJ-1) The TMJ-1 is an 8-bit reload timer. As the clock source, dividing clock or edge signals through the ,544 pin are being used. By selecting the edge signals through the ,544 pin, it can also be used as an event counter.
  • Page 289: Remote Controlled Data Transmission

    information on the 16-bit or 24-bit reload timer, see section 13.3.1, 8-bit Reload Timer (TMJ-1). The TMJ-2 and TMJ-1, in combination, can be operated by remote controlled data transmission. Regarding the remote controlled data transmission, see section 13.3.3, Remote Controlled Data Transmission.
  • Page 290 Figure 13.3 Timer Output Timing Rev. 1.0, 02/00, page 276 of 1141...
  • Page 291 When the Timer J is set to the remote controlled operation mode, since the start bit (ST) is being set or cleared in synchronization with the inputting clock to the TMJ-2, a delay upto a cycle of the inputting clock at the maximum occurs, namely, after the ST bit has been set to 1 until the remote controlled data transmission starts.
  • Page 292: Tmj-2 Expansion Function

    13.3.4 TMJ-2 Expansion Function The TMJ-2 expansion function is enabled by setting the EXN bit in the timer J control register (TMJC) to 0. This function makes TMJ-2, which usually works as an 8-bit counter, work as a 16- bit counter. When this function is selected, timer counter K (TCK) and timer load register K (TLK) must be accessed as follows: TCK Read: To read TCK, use the word-length MOV instruction.
  • Page 293: Section 14 Timer L

    Section 14 Timer L 14.1 Overview Timer A is an 8-bit up/down counter using the control pulses or the CFG division signals as the clock source. 14.1.1 Features Features of timer L are as follows: • Two types of internal clocks (φ/128 and φ/64), DVCFG2 (CFG division signal 2), PB and REC-CTL (control pulses) are available for your selection.
  • Page 294: Block Diagram

    14.1.2 Block Diagram Figure 14.1 shows a block diagram of timer L. INTERNAL CLOCK φ/128 φ/64 Read DVCFG2 OVF/UDF PB and REC-CTL Reloading Match clear Comparator Interrupting circuit Write [Legend] DVCFG2 : Division signal 2 of the CFG Interrupt request PB and REC-CTL : Control pluses necessary when making reproduction and storage LMR : Timer L mode register...
  • Page 295: Register Configuration

    14.1.3 Register Configuration Table 14.1 shows the register configuration of timer L. The linear time counter (LTC) and the reload compare patch register (RCR) are being allocated to the same address. Reading or writing determines the accessing register. Table 14.1 Register Configuration Name Abbrev.
  • Page 296: Register Descriptions

    14.2 Register Descriptions 14.2.1 Timer L Mode Register (LMR) Bit : LMIF LMIE LMR3 LMR2 LMR1 LMR0 — — Initial value : — — R/W : R /(W)* Note: * Only 0 can be written to clear the flag. The timer L mode register A (LMR) is an 8-bit read/write register which works to control the interrupts, to select between up-counting and down-counting and to select the clock source.
  • Page 297 1. When Controlled to the Up-Counting Function  When any other values than H'00 are input to the RCR, the LTC will be cleared to H'00 before starting counting up. When the LTC value and the RCR value match, the LTC will be cleared to H'00.
  • Page 298: Linear Time Counter (Ltc)

    14.2.2 Linear Time Counter (LTC) Bit : LTC7 LTC6 LTC5 LTC4 LTC3 LTC2 LTC1 LTC0 Initial value : R/W : The linear time counter (LTC) is a readable 8-bit up/down-counter. The inputting clock can be selected by the LMR2 to LMR0 bits of the LMR. When reset, the LTC is initialized to H'00.
  • Page 299: Module Stop Control Register (Mstpcr)

    14.2.4 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode. When the MSTP12 bit is set to 1, timer L stops its operation at the ending point of the bus cycle to shift to the module stop mode.
  • Page 300: Operation

    14.3 Operation Timer L is an 8-bit up/down counter. The inputting clock for Timer L can be selected by the LMR2 to LMR0 bits of the LMR from the choices of the internal clock (φ/128 and φ/64), DVCDG2, PB and REC-CTL. Timer L is provided with three different types of operation modes, namely, the compare match clear mode when controlled to the up-counting function, the auto reloading mode when controlled to the down-counting function and the interval timer mode.
  • Page 301 φ PB-CTL Count-up signal Compare match clear signal H' 00 Interrupt request Figure 14.3 Compare Match Clearing Timing Chart (In case the rising edge of the PB-CTL is selected) Rev. 1.0, 02/00, page 287 of 1141...
  • Page 302: Section 15 Timer R

    Section 15 Timer R 15.1 Overview Timer R consists of triple 8-bit down-counters. It carries VCR mode identification function and slow tracking function in addition to the reloading function and event counter function. 15.1.1 Features The Timer R consists of triple 8-bit reloading timers. By combining the functions of three units of reloading timers/counters and by combining three units of timers, it can be used for the following applications: •...
  • Page 303 Figure 15.1 Block Diagram of Timer R Rev. 1.0, 02/00, page 290 of 1141...
  • Page 304: Pin Configuration

    15.1.3 Pin Configuration Table 15.1 shows the pin configuration of timer R. Table 15.1 Pin Configuration Name Abbrev. Function ,546 Input capture inputting pin Input Input capture inputting for the Timer R 15.1.4 Register Configuration Table 15.2 shows the register configuration of timer R. Table 15.2 Register Configuration Name Abbrev.
  • Page 305: Register Descriptions

    15.2 Register Descriptions 15.2.1 Timer R Mode Register 1 (TMRM1) Bit : CLR2 AC/BR RLCK PS21 PS20 RLD/CAP Initial value : R/W : The timer R mode register 1 (TMRM1) works to control the acceleration and braking processes and to select the inputting clock for the TMRU-2. This is an 8-bit read/write register. When reset, the TMRM1 is initialized to H'00.
  • Page 306 Bit 5    Using/Not Using the TMRU-2 for Reloading (RLD): This bit is used for selecting if the TMRU-2 reload function is to be turned on or not. Bit 5 Description Not using the TMRU-2 as the reload timer (Initial value) Using the TMRU-2 as the reload timer Bit 4...
  • Page 307: Timer R Mode Register 2 (Tmrm2)

    Bit 0    Capture Signals of the TMRU-1 (CPS): In combination with the LAT bit (Bit 7) of the TMR2, this bit works to select the capture signals of the TMRU-1. This bit becomes valid when the LAT bit is being set to 1. It will also become valid when the RLD/CAP bit (Bit 1) is being set to 1.
  • Page 308 Bit 7    Capture Signals of the TMRU-2 (LAT): In combination with the CPS bit (Bit 0) of the TMRM1, this bit works to select the capture signals of the TMRU-2. TMRM2 TMRM1 Bit 7 Bit 0 Description Captures when the TMRU-3 underflows (Initial value) Captures at the rising edge of the CFG...
  • Page 309 Bit 2    Interrupt Causes (CP/SLM): This bit works to select the interrupt causes for the TMRI3. Bit 2 CP/SLM Description Makes interrupt requests upon the capture signals of the TMRU-2 valid (Initial value) Makes interrupt requests upon ending of the slow tracking mono-multi valid Bit 1...
  • Page 310: Timer R Control/Status Register (Tmrcs)

    15.2.3 Timer R Control/Status Register (TMRCS) Bit : — — TMRI3E TMRI2E TMRI1E TMRI3 TMRI2 TMRI1 Initial value : — — R/(W)* R/(W)* R/(W)* R/W : Note: * Only 0 can be written to clear the flag. The timer R control/status register (TMRCS) works to control the interrupts of timer R. The TMRCS is an 8-bit read/write register.
  • Page 311 Bit 5    Enabling the TMRI1 Interrupt (TMRI1E): This bit works to permit/prohibit occurrence of the TMRI1 interrupt when the TMRI1 has been set to 1 by issuance of the underflow signal of the TMRU-1. Bit 5 TMRI1E Description Prohibits occurrences of TMRI1 interrupts (Initial value)
  • Page 312: Timer R Capture Register 1 (Tmrcp1)

    Bit 2    TMRI1 Interrupt Requesting Flag (TMRI1): This is the TMRI1 interrupt requesting flag. It indicates occurrences of the TMRU-1 underflow signals. Bit 2 TMRI1 Description [Clearing conditions] (Initial value) When 0 is written after reading 1. [Setting conditions] When the TMRU-1 underflows.
  • Page 313: Timer R Capture Register 2 (Tmrcp2)

    15.2.5 Timer R Capture Register 2 (TMRCP2) Bit : TMRC27 TMRC26 TMRC25 TMRC24 TMRC23 TMRC22 TMRC21 TMRC20 Initial value : R/W : The timer R capture register 2 (TMRCP2) works to store the capture data of the TMRU-2. At each CFG edge, IRQ3 edge, or at occurrence of underflow of the TMRU-3, the TMRU-2 counter readings are captured by the TMRCP2.
  • Page 314: Timer R Load Register 2 (Tmrl2)

    15.2.7 Timer R Load Register 2 (TMRL2) Bit : TMR27 TMR26 TMR25 TMR24 TMR23 TMR22 TMR21 TMR20 Initial value : R/W : The timer R load register 2 (TMRL2) is an 8-bit write only register which works to set the load value of the TMRU-2.
  • Page 315: Module Stop Control Register (Mstpcr)

    15.2.9 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode. When the MSTP11 bit is set to 1, timer R stops its operation at the ending point of the bus cycle to shift to the module stop mode.
  • Page 316: Operation

    15.3 Operation 15.3.1 Reload Timer Counter Equipped with Capturing Function TMRU-1 TMRU-1 is a reload timer counter equipped with capturing function. It consists of an 8-bit down- counter, a reloading register and a capture register. The clock source can be selected from among the leading edge of the CFG signals and three types of dividing clocks.
  • Page 317: Reload Timer Counter Equipped With Capturing Function Tmru-2

    15.3.2 Reload Timer Counter Equipped with Capturing Function TMRU-2 TMRU-2 is a reload timer counter equipped with capturing function. It consists of an 8-bit down- counter, a reloading register and a capture register. The clock source can be selected from among the undedrflowing signal of the TMRU-1 and three types of dividing clocks.
  • Page 318: Mode Identification

    searches. These DVCTL signals can also be used for phase controls of the capstan motor. Also, by selecting the dividing clock as the clock source, it is possible to make a delay with the edges of the DVCTL to provide the slow tracking mono-multi function. 15.3.4 Mode Identification When making mode identification (2/4/6 identification) of the SP/LP/EP modes of reproducing...
  • Page 319: Slow Tracking Mono-Multi Function

    underflowing works to set to CFG mask F/F (masking movement) and the reload timer will be cleared by the CFG. • When the acceleration has been finished (when the CFG signal is input before the prescribed time has elapsed = reloading movement has been made before the down counter underflows), an interrupt request will be issued because of the CFG.
  • Page 320 Compensation for vertical vibrations (Supplementary V-pulse) FG acceleration detection Accelerating the Hi-Z capstan motor Acceleration process DVCTL↑ Interrupt Slow tracking mono-multi Slow tracking delay FG stopping detection Reloading Reverse Braking the rotation capstan motor Forward rotation Braking process Braking the Servo drum motor Compensation for...
  • Page 321: Interrupt Cause

    15.4 Interrupt Cause In timer R, bits TMRI1 to TMRI3 of the timer R control/status register cause interrupts. The following are descriptions of the interrupts. 1. Interrupts caused by the underflowing of the TMRU-1 (TMRI1) These interrupts will constitute the timing for reloading with the TMRU-1. 2.
  • Page 322: Settings For Respective Functions

    15.5 Settings for Respective Functions 15.5.1 Mode Identification When making mode identification (2/4/6 identification) of the SP/LP/EP modes of reproducing tapes, the TMRU-1 (CFG dividing circuit), TMRU-2 (capturing function/without reloading function) and TMRU-3 (DVCTL dividing circuit) of the timer R should be used. Timer R will be initialized to this mode identification status after a reset.
  • Page 323: Reeling Controls

    15.5.2 Reeling Controls CFG counts can be captured by making 16-bit capturing operation combining the TMRU-1 and TMRU-2. By choosing the IRQ3 as the capture signal, and by counting the CFG within the duration of the reel pulse being input through the ,546 pin, reeling controls, etc. can be effected. Settings •...
  • Page 324: Acceleration And Braking Processes Of The Capstan Motor

    Settings • Setting the timer R mode register 2 (TMRM2)  PS31 and PS30 (bits 4 and 3) = Other than (0, 0): The dividing clock is to be used as the clock source for the TMRU-3.  CP/SLM bit (bit 2) = 1: The slow tracking delay signal is to work to issue the TMRI3 interrupt request.
  • Page 325  PS21 and PS20 (bits 3 and 2) = Other than (0, 0): The dividing clock is to be used as the clock source for the TMRU-2. • Setting the timer R load register 2 (TMRL2)  Set the count reading for the duration until the braking process finishes. When the count is n, the set value should be (n - 1).
  • Page 326: Section 16 Timer X1

    Section 16 Timer X1 16.1 Overview Timer X1 is capable of outputting two different types of independent waveforms using a 16-bit free running counter (FRC) as the basic means and it is also applicable to measurements of the durations of input pulses and the cycles external clocks. 16.1.1 Features Timer X1 has the following features:...
  • Page 327: Block Diagram

    16.1.2 Block Diagram Figure 16.1 shows a block diagram of the Timer X1. FTIA* ICRA (HSW) FTIB* (VD) ICRB Input FTIC* capture (DVCTL) control ICRC FTID* (NHSW) ICRD TCRX OCRB Comparison circuit (DVCFG) φ / 4 Comparison circuit φ / 16 φ...
  • Page 328: Pin Configuration

    16.1.3 Pin Configuration Table 16.1 shows the pin configuration of timer X1. Table 16.1 Pin Configuration Name Abbrev. Function Output comparing A output-pin FTOA Output Output pin for the output comparing A Output comparing B output-pin FTOB Output Output pin for the output comparing B Input capture A input-pin FTIA Input...
  • Page 329: Register Configuration

    16.1.4 Register Configuration Table 16.2 shows the register configuration of timer X1. Table 16.2 Register Configuration Name Abbrev. Initial Value Address Timer interrupt enabling register TIER H'00 H'D100 Timer control/status register X TCSRX R/ (W) H'00 H'D101 Free running counter H FRCH H'00 H'D102...
  • Page 330: Register Descriptions

    16.2 Register Descriptions 16.2.1 Free Running Counter (FRC) Free running counter H (FRCH) Free running counter L (FRCL) Bit : Initial value : R/W : FRCH FRCL The FRC is a 16-bit read/write up-counter which counts up by the inputting internal clock/external clock.
  • Page 331: Output Comparing Registers A And B (Ocra And Ocrb)

    16.2.2 Output Comparing Registers A and B (OCRA and OCRB) Output comparing register AH and BH (OCRAH and OCRBH) Output comparing register AL and BL (OCRAL and OCRBL) OCRA, OCRB Bit : Initial value : R/W : OCRAH, OCRBH OCRAL, OCRBL The OCR consists of twin 16-bit read/write registers (OCRA and OCRB).
  • Page 332: Input Capture Registers A Through D (Icra Through Icrd)

    16.2.3 Input Capture Registers A Through D (ICRA Through ICRD) Input capture register AH to DH (ICRAH to ICRDH) Input capture register AL to DL (ICRAL to ICRDL) ICRA, ICRB, ICRC, ICRD Bit : Initial value : R/W : ICRAH, ICRBH, ICRCH, ICRDH ICRAL, ICRBL, ICRCL, ICRDL The ICR consists of four 16-bit read-only registers (ICRA through ICRD).
  • Page 333 IEDGA BUFEA IEDGC Edge detection and FTIA capture signal generating circuit. ICRC ICRA Figure 16.2 Buffer Operation (Example) Table 16.3 Input Signal Edge Selection when Making Buffer Operation IEDGA IEDGC Selection of the Input Signal Edge Captures at the falling edge of the input capture input A (Initial value) Captures at both rising and falling edges of the input capture input A Captures at the rising edge of the input capture input A Reading can be made from the ICR through the CPU at 8-bit or 16-bit.
  • Page 334: Timer Interrupt Enabling Register (Tier)

    16.2.4 Timer Interrupt Enabling Register (TIER) Bit : ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE ICSA Initial value : R/W : The TIER is an 8-bit read/write register that controls permission/prohibition of interrupt requests. The TIER is initialized to H'00 when reset or under the standby mode, watch mode, subsleep mode, module stop mode or subactive mode.
  • Page 335 Bit 4    Enabling the Input Capture Interrupt D (ICIDE): This bit works to permit/prohibit interrupt requests (ICID) by the ICFD when the ICFD of the TCSRX is being set to 1. Bit 4 ICIDE Description Prohibits interrupt requests (ICID) by the ICFD (Initial value) Permits interrupt requests (ICID) by the ICFD Bit 3...
  • Page 336 Bit 0    Selecting the Input Capture A Signals (ICSA): This bit works to select the input capture A signals. Bit 0 ICSA Description Selects the FTIA pin for inputting of the input capture A signals (Initial value) Selects the HSW for inputting of the input capture A signals Rev.
  • Page 337: Timer Control/Status Register X (Tcsrx)

    16.2.5 Timer Control/Status Register X (TCSRX) Bit : ICFA ICFB ICFC ICFD OCFA OCFB CCLRA Initial value : R/W : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written to clear the flag for Bits 7 to 1. The TCSRX is an 8-bit register which works to select counter clearing timing and to control respective interrupt requesting signals.
  • Page 338 Bit 6    Input Capture Flag B (ICFB): This status flag indicates the fact that the value of the FRC has been transferred to the ICRB by the input capture signals. When the BUFEB of the TCRX is being set to 1, the ICFB indicates the status that the FRC value has been transferred to the ICRB by the input capture signals and that the ICRB value before being updated has been transferred to the ICRC.
  • Page 339 Bit 4    Input Capture Flag D (ICFD): This status flag indicates the fact that the value of the FRC has been transferred to the ICRD by the input capture signals. When an input capture signal occurs while the BUFEB of the TCRX is being set to 1, although the ICFD will be set out, data transference to the ICRD will not be performed.
  • Page 340 Bit 2    Output Comparing Flag B (OCFB): This status flag indicates the fact that the FRC and the OCRB have come to a comparing match. This flag should be cleared by use of the software. Such setting should only be made by use of the hardware.
  • Page 341: Timer Control Register X (Tcrx)

    16.2.6 Timer Control Register X (TCRX) Bit : IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0 Initial value : R/W : The TCRX is an 8-bit read/write register that selects the input capture signal edge, designates the buffer operation, and selects the inputting clock for the FRC. The TCRX is initialized to H'00 when reset or under the standby mode, watch mode, subsleep mode, module stop mode or subactive mode.
  • Page 342 Bit 4    Input Capture Signal Edge Selection D (IEDGD): This bit works to select the rising edge or falling edge of the input capture signal D (FTID). Bit 4 IEDGD Description Captures the falling edge of the input capture signal D (Initial value) Captures the rising edge of the input capture signal D Bit 3...
  • Page 343: Timer Output Comparing Control Register (Tocr)

    16.2.7 Timer Output Comparing Control Register (TOCR) Bit : ICSB ICSC ICSD OSRS OLVLA OLVLB Initial value : R/W : The TOCR is an 8-bit read/write register that select input capture signals and output comparing output level, permits output comparing outputs, and controls switching over of the access of the OCRA and OCRB.
  • Page 344 Bit 4    Selecting the Output Comparing Register (OCRS): The addresses of the OCRA and OCRB are the same. The OCRS works to control which register to choose when reading/writing this address. The choice will not influence the operation of the OCRA and OCRB. Bit 4 OCRS Description...
  • Page 345: Module Stop Control Register (Mstpcr)

    Bit 0    Output Level B (OLVLB): This bit works to select the output level to output through the FTOB pin by use of the comparing match B (matching signal between the FRC and OCRB). Bit 0 OLVLB Description Low level (Initial value)
  • Page 346: Operation

    16.3 Operation 16.3.1 Operation of Timer X1 • Output Comparing Operation Right after resetting, the FRC is initialized to H'0000 to start counting up. The inputting clock can be selected from among three different types of internal clocks or the external clock by setting the CKS1 and CKS0 of the TCRX.
  • Page 347: Counting Timing Of The Frc

    16.3.2 Counting Timing of the FRC The FRC is counted up by the inputting clock. By setting the CKS1 and CKS0 of the TCRX, the inputting clock can be selected from among three different types of clocks (φ/4, φ/16 and φ/64) and the DVCFG.
  • Page 348: Output Comparing Signal Outputting Timing

    16.3.3 Output Comparing Signal Outputting Timing When a comparing match occurs, the output level having been set by the OLVL of the TOCR is output through the output comparing signal outputting pins (FTOA and FTOB). Figure 16.5 shows the timing chart for the output comparing signal outputting A. φ...
  • Page 349: Input Capture Signal Inputting Timing

    16.3.5 Input Capture Signal Inputting Timing • Input Capture Signal Inputting Timing As for the input capture signal inputting, rising or falling edge is selected by settings of the IEDGA through IEDGD bits of the TCRX. Figure 16.7 shows the timing chart when the rising edge is selected (IEDGA through IEDGD = φ...
  • Page 350: Input Capture Flag (Icfa Through Icfd) Setting Up Timing

    Even when the ICRC or ICRD is used as the buffer register, the input capture flag will be set up corresponding to the designated edge change of respective input capture signals. For example, when using the ICRC as the buffer register for the ICRA, when an edge change having been designated by the IEDGC bit is detected with the input capture signals C and if the ICIEC bit is duly set, an interrupt request will be issued.
  • Page 351: Output Comparing Flag (Ocfa And Ocfb) Setting Up Timing

    16.3.7 Output Comparing Flag (OCFA and OCFB) Setting Up Timing The OCFA and OCFB are being set to 1 by the comparing match signal being output when the values of the OCRA, OCRB and FRC match. The comparing match signal is generated at the last state of the value match (the timing of the FRC's updating the matching count reading).
  • Page 352: Operation Mode Of Timer X1

    16.4 Operation Mode of Timer X1 Table 16.4 indicated below shows the operation mode of Timer X1. Table 16.4 Operation Mode of Timer X1 Operation Module Mode Reset Active Sleep Watch Subactive Standby Subsleep Stop Reset Functions Functions Reset Reset Reset Reset Reset...
  • Page 353: Interrupt Causes

    16.5 Interrupt Causes Total seven interrupt causes exist with Timer X1, namely, ICIA through ICID, OCIA, OCIB and FOVI. Table 16.5 lists the contents of interrupt causes. Interrupt requests can be permitted or prohibited by setting interrupt enabling bits of the TIER. Also, independent vector addresses are allocated to respective interrupt causes.
  • Page 354: Exemplary Uses Of Timer X1

    16.6 Exemplary Uses of Timer X1 Figure 16.12 shows an example of outputting at optional phase difference of the pulses of the 50% duty. For this setting, follow the procedures listed below. 1. Set the CCLRA bit of the TCSRX to 1. 2.
  • Page 355: Precautions When Using Timer X1

    16.7 Precautions when Using Timer X1 Pay great attention to the fact that the following competitions and operations occur during operation of timer X1. 16.7.1 Competition between Writing and Clearing with the FRC When a counter clearing signal is issued under the T2 state where the FRC is under the writing cycle, writing into the FRC will not be effected and the priority will be given to clearing of the FRC.
  • Page 356: Competition Between Writing And Counting Up With The Frc

    16.7.2 Competition between Writing and Counting Up with the FRC When a counting up cause occurs under the T2 state where the FRC is under the writing cycle, the counting up will not be effected and the priority will be given to count writing. Figure 16.14 shows the timing chart.
  • Page 357: Competition Between Writing And Comparing Match With The Ocr

    16.7.3 Competition between Writing and Comparing Match with the OCR When a comparing match occurs under the T2 state where the OCRA and OCRB are under the writing cycle, the priority will be given to writing of the OCR and the comparing match signal will be prohibited.
  • Page 358: Changing Over The Internal Clocks And Counter Operations

    16.7.4 Changing Over the Internal Clocks and Counter Operations Depending on the timing of changing over the internal clocks, the FRC may count up. Table 16.6 shows the relations between the timing of changing over the internal clocks (Re-writing of the CKS1 and CKS0) and the FRC operations.
  • Page 359 Rewriting Timing for the CKS1 and CKS0 FRC Operation High → low level Clock before changeover the changeover Clock after the changeover Count clock Rewriting of the CKS1 and CKS0 High → high level Clock before changeover the changeover Clock after the changeover Count clock...
  • Page 360: Section 17 Watchdog Timer (Wdt)

    Section 17 Watchdog Timer (WDT) 17.1 Overview This LSI has an on-chip watchdog timer with one channel (WDT) for monitoring system operation. The WDT outputs an overflow signal if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow. At the same time, the WDT can also generate an internal reset signal or internal NMI interrupt signal.
  • Page 361: Block Diagram

    17.1.2 Block Diagram Figure 17.1 shows block diagram of WDT. φ / 2 φ / 64 WOVI φ / 128 (Interrupt request signal) Interrupt φ / 512 Clock control Overflow Clock Internal NMI φ / 2048 select • interrupt request signal φ...
  • Page 362: Register Configuration

    17.1.3 Register Configuration The WDT has two registers, as described in table 17.1. These registers control clock selection, WDT mode switching, the reset signal, etc. Table 17.1 WDT Registers Address Name Abbrev. Initial Value Write Read Watchdog timer WTCSR R/ (W) H'00 H'FFBC H'FFBC...
  • Page 363: Register Descriptions

    17.2 Register Descriptions 17.2.1 Watchdog Timer Counter (WTCNT) Bit : Initial value : R/W : TCNT is an 8-bit readable/writable* up-counter. When the TME bit is set to 1 in WTCSR, WTCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in WTCSR. When the count overflows (changes from H'FF to H'00), the OVF flag in WTCSR is set to 1.
  • Page 364 Bit 7    Overflow Flag (OVF): A status flag that indicates that WTCNT has overflowed from H'FF to H'00. Bit 7 Description [Clearing conditions] (Initial value) 1. Write 0 in the TME bit 2. Read WTCSR when OVF = 1, then write 0 in OVF [Setting condition] When WTCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is...
  • Page 365 Bit 3    Reset or NMI (RST/10, 10,): Specifies whether an internal reset or NMI interrupt is requested on WTCNT overflow in watchdog timer mode. Bit 3 RST/10, Description An NMI interrupt request is generated (Initial value) An internal reset request is generated Bits 2 to 0...
  • Page 366: System Control Register (Syscr)

    17.2.3 System Control Register (SYSCR) Bit : — — INTM1 INTM0 XRST — — — Initial value : — — — — — R/W : Only bit 3 is described here. For details on functions not related to the watchdog timer, see sections 3.2.2 and 6.2.1, System Control Register (SYSCR), and the descriptions of the relevant modules.
  • Page 367: Notes On Register Access

    17.2.4 Notes on Register Access The watchdog timer's WTCNT and WTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. • Writing to WTCNT and WTCSR These registers must be written to by a word transfer instruction.
  • Page 368: Operation

    17.3 Operation 17.3.1 Watchdog Timer Operation To use the WDT as a watchdog timer, set the WT/,7 and TME bits in WTCSR to 1. Software must prevent WTCNT overflows by rewriting the WTCNT value (normally by writing H'00) before overflow occurs. This ensures that WTCNT does not overflow while the system is operating normally.
  • Page 369: Interval Timer Operation

    17.3.2 Interval Timer Operation To use the WDT as an interval timer, clear the WT/,7 bit in WTCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time WTCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 17.4.
  • Page 370: Timing Of Setting Of Overflow Flag (Ovf)

    17.3.3 Timing of Setting of Overflow Flag (OVF) The OVF bit in WTCSR is set to 1 if WTCNT overflows during interval timer operation. At the same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 17.5. If NMI request generation is selected in watchdog timer mode, when WTCNT overflows the OVF bit in WTCSR is set to 1 and at the same time an NMI interrupt is requested.
  • Page 371: Interrupts

    17.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in WTCSR. OVF must be cleared to 0 in the interrupt handling routine. When NMI interrupt request generation is selected in watchdog timer mode, an overflow generates an NMI interrupt request.
  • Page 372: Changing Value Of Cks2 To Cks0

    17.5.2 Changing Value of CKS2 to CKS0 If bits CKS2 to CKS0 in WTCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS2 to CKS0.
  • Page 373: Section 18 8-Bit Pwm

    Section 18 8-Bit PWM 18.1 Overview The 8-bit PWM incorporates 4 channels of the duty control method. Its outputs can be used to control a reel motor or loading motor. 18.1.1 Features • Conversion period: 256-state • Duty control method 18.1.2 Block Diagram Figure 18.1 shows a block diagram of the 8-bit PWM (1 channel).
  • Page 374: Pin Configuration

    18.1.3 Pin Configuration Table 18.1 shows the 8-bit PWM pin configuration. Table 18.1 Pin Configuration Name Abbrev. Function 8-bit PWM square-wave output pin 0 PWM0 Output 8-bit PWM square-wave output 0 8-bit PWM square-wave output pin 1 PWM1 Output 8-bit PWM square-wave output 1 8-bit PWM square-wave output pin 2 PWM2 Output...
  • Page 375: Register Descriptions

    18.2 Register Descriptions 18.2.1 8-bit PWM Data Registers 0, 1, 2 and 3 (PWR0, PWR1, PWR2, PWR3) PWR0 Bit : PW07 PW06 PW05 PW04 PW03 PW02 PW01 PW00 Initial value : R/W : PWR1 Bit : PW17 PW16 PW15 PW14 PW13 PW12 PW11...
  • Page 376: 8-Bit Pwm Control Register (Pw8Cr)

    18.2.2 8-bit PWM Control Register (PW8CR) Bit : — — — — PWC3 PWC2 PWC1 PWC0 Initial value : — — — — R/W : The 8-bit PWM control register (PW8CR) is an 8-bit readable/writable register that controls PWM functions. PW8CR is initialized to H'00 by a reset. Bits 7 to 4...
  • Page 377: Port Mode Register 3 (Pmr3)

    18.2.3 Port Mode Register 3 (PMR3) Bit : PMR37 PMR36 PMR35 PMR34 PMR33 PMR32 PMR31 PMR30 Initial value : R/W : The port mode register 3 (PMR3) controls function switching of each pin in the port 3. Switching is specified for each bit. The PMR3 is a 8-bit readable/writable register and is initialized to H'00 by a reset.
  • Page 378: Module Stop Control Register (Mstpcr)

    18.2.4 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : The MSTPCR consists of two 8-bit readable/writable registers that control module stop mode. When MSTP4 bit is set to 1, the 8-bit PWM stops its operation upon completion of the bus cycle and transits to the module stop mode.
  • Page 379: 8-Bit Pwm Operation

    18.3 8-Bit PWM Operation The 8-bit PWM outputs PWM pulses having a cycle length of 256 states and a pulse width determined by the data registers (PWR). The output PWM pulse can be converted to a DC voltage through integration in a low-pass filter. Figure 18.2 shows the output waveform example of 8-bit PWM.
  • Page 380: Section 19 12-Bit Pwm

    Section 19 12-Bit PWM 19.1 Overview The 12-bit PWM incorporates 2 channels of the pulse pitch control method and functions as the drum and capstan motor controller. 19.1.1 Features Two on-chip 12-bit PWM signal generators are provided to control motors. These PWMs use the pulse-pitch control method (periodically overriding part of the output).
  • Page 381: Block Diagram

    19.1.2 Block Diagram Figure 19.1 shows a block diagram of the 12-bit PWM (1 channel). The PWM signal is generated by combining quantizing pulses from a 12-bit pulse generator with quantizing pulses derived from the contents of a data register. Low-frequency components are reduced because the two quantizing pulses have different frequencies.
  • Page 382: Pin Configuration

    19.1.3 Pin Configuration Table 19.1 shows the 12-bit PWM pin configuration. Table 19.1 Pin Configuration Name Abbrev. Function Capstan mix CAPPWM Output 12-bit PWM square-wave output Drum mix DRMPWM 19.1.4 Register Configuration Table 19.2 shows the 12-bit PWM register configuration. Table 19.2 12-Bit PWM Registers Name Abbrev.
  • Page 383: Register Descriptions

    19.2 Register Descriptions 19.2.1 12-Bit PWM Control Registers (CPWCR, DPWCR) CPWCR Bit : CPOL CHiZ CH/L CSF/DF CCK2 CCK1 CCK0 Initial value : R/W : DPWCR Bit : DPOL DHiZ DH/L DSF/DF DCK2 DCK1 DCK0 Initial value : R/W : CPWCR is the PWM output control register for the capstan motor.
  • Page 384 Bits 5 and 4    PWM Pin Output (HiZ, H/L): When bit DC is set to 1, the 12-bit PWM output pins (CAPPWM, DRMPWM) output a value determined by the HiZ and H/L bits. The output is not affected by bit POL. In power-down modes, the 12-bit PWM circuit and pin statuses are retained.
  • Page 385 Bits 2 to 0    Carrier Frequency Select (CK2 to CK0): Selects the carrier frequency of the PWM modulated signal. Do not set them to 111. Bit 2 Bit 1 Bit 0 Description φ2 φ4 φ8 (Initial value) φ16 φ32 φ64...
  • Page 386: 12-Bit Pwm Data Registers (Dpwdr, Cpwdr)

    19.2.2 12-Bit PWM Data Registers (DPWDR, CPWDR) CPWDR Bit : — — — — CPWDR11 CPWDR10 CPWDR9 CPWDR8 CPWDR7 CPWDR6 CPWDR5 CPWDR4 CPWDR3 CPWDR2 CPWDR1 CPWDR0 Initial value : R/W : — — — — DPWDR Bit : — — —...
  • Page 387: Operation

    19.3 Operation 19.3.1 Output Waveform The PWM signal generator combines the error data with the output from an internal pulse generator to produce a pulse-width modulated signal. When Vcc/2 is set as the reference value, the following conditions apply: 1. When the motor is running at the correct speed and phase, the PWM signal is output with a 50% duty cycle.
  • Page 388 Figure 19.2 Sample Waveform Output by 12-Bit PWM (4 Bits) Rev. 1.0, 02/00, page 377 of 1141...
  • Page 389: Section 20 14-Bit Pwm

    Section 20 14-Bit PWM 20.1 Overview The 14-bit PWM is a pulse division type PWM that can be used for electronic tuner control, etc. 20.1.1 Features Features of the 14-bit PWM are given below: • Choice of two conversion periods A conversion period of 32768/φ...
  • Page 390: Block Diagram

    20.1.2 Block Diagram Figure 20.1 shows a block diagram of the 14-bit PWM. PWCR PWDRL PWDRU φ/4 PWM waveform PWM14 φ/2 generator [Legend] PWCR : PWM control register PWDRL : PWM data register L PWDRU : PWM data register U PWM14 : PWM14 output pin Figure 20.1 Block Diagram of 14-Bit PWM...
  • Page 391: Register Configuration

    20.1.4 Register Configuration Table 20.2 shows the 14-bit PWM register configuration. Table 20.2 14-Bit PWM Registers Name Abbrev. Size Initial Value Address* PWM control register PWCR Byte H'FE H'D122 PWM data register U PWDRU Byte H'00 H'D121 PWM data register L PWDRL Byte H'00...
  • Page 392: Register Descriptions

    20.2 Register Descriptions 20.2.1 PWM Control Register (PWCR) Bit : — — — — — — — PWCR0 Initial value : — — — — — — — R/W : The PWM control register (PWCR) is an 8-bit read/write register that controls the 14-bit PWM functions.
  • Page 393: Pwm Data Registers U And L (Pwdru, Pwdrl)

    20.2.2 PWM Data Registers U and L (PWDRU, PWDRL) PWDRU Bit : — — PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 Initial value : R/W : — — PWDRL Bit : PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 Initial value : R/W : PWM data registers U and L (PWDRU and PWDRL) indicate high level width in one PWN waveform cycle.
  • Page 394: Module Stop Control Register (Mstpcr)

    20.2.3 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : The module stop control register (MSTPCR) consists of two 8-bit readable/writable registers that control the module stop mode functions.
  • Page 395: 14-Bit Pwm Operation

    20.3 14-Bit PWM Operation When using the 14-bit PWM, set the registers in this sequence: 1. Set bit PWM40 to 1 in port mode register 4 (PMR4) so that pin P40/PWM14 is designated for PWM output. 2. Set bit PWCR0 in the PWM control register (PWCR) to select a conversion period of either 32768/φ...
  • Page 396: Section 21 Prescalar Unit

    Section 21 Prescalar Unit 21.1 Overview The prescalar unit (PSU) has a 18-bit free running counter (FRC) that uses φ as a clock source and a 5-bit counter that uses φW as a clock source. 21.1.1 Features • Prescalar S (PSS) Generates frequency division clocks that are input to peripheral functions.
  • Page 397: Block Diagram

    21.1.2 Block Diagram Figure 21.1 shows a block diagram of the prescalar unit. PWM3 PWM2 PWM1 Stable oscillation PWM0 wait time count output 6 bits 8 bits Prescalar S φ/131072 to φ/2 φ 18-bit free running counter (FRC) 8 bits φ/4 φ/8 φ/16...
  • Page 398: Pin Configuration

    21.1.3 Pin Configuration Table 21.1 shows the pin configuration of the prescalar unit. Table 21.1 Pin Configuration Name Abbrev. Function ,& Input capture input Input Prescalar unit input capture input pin Frequency division clock TMOW Output Prescalar unit frequency division clock output output pin 21.1.4...
  • Page 399: Registers

    21.2 Registers 21.2.1 Input Capture Register 1 (ICR1) Bit : ICR17 ICR16 ICR15 ICR14 ICR13 ICR12 ICR11 ICR10 Initial value : R/W : Input capture register 1 (ICR1) captures 8-bit data of 2 to 2 of the FRC according to the edge of the ,&...
  • Page 400 Bit 6    Input Capture Interrupt Enable (ICIE): When ICIF was set to 1 by the input capture according to the edge of the ,& pin, ICIE enables and disables the generation of an input capture interrupt. Bit 6 ICIE Description Disables the generation of an input capture interrupt...
  • Page 401 Bits 2 to 0    Frequency Division Clock Output Select (DCS2 to DCS0): DCS2 to DCS0 select eight types of frequency division clocks that are output from the TMOW pin. Bit 2 Bit 1 Bit 0 DCS2 DCS1 DCS0 Description Outputs PSS, φ/32...
  • Page 402: Port Mode Register 1 (Pmr1)

    21.2.3 Port Mode Register 1 (PMR1) Bit : PMR17 PMR16 PMR15 PMR14 PMR13 PMR12 PMR11 PMR10 Initial value : R/W : The port mode register 1 (PMR1) controls switching of each pin function of port 1. The switching is specified in a unit of bit. PMR1 is an 8-bit read/write enable register.
  • Page 403: Noise Cancel Circuit

    21.3 Noise Cancel Circuit The ,& pin has a built-in a noise cancel circuit. The circuit can be used for noise protection such as remote control receiving. The noise cancel circuit samples the input values of the ,& pin twice at an interval of 256 states.
  • Page 404: Prescalar W (Psw)

    21.4.2 Prescalar W (PSW) PSW is a counter that uses the subclock as an input clock. The PSW also generates the input clock of the timer A. In this case, the timer A functions as a clock time base. When reset, the PSW is initialized to H'00, and starts increment after reset has been released. Even if the mode has been shifted to the standby mode *, watch mode *, subactive mode *, and subsleep mode *, the PSW continues the operation as long as the clocks are supplied by the X1 and X2 pins.
  • Page 405: 8-Bit Pwm

    21.4.4 8-bit PWM This 8-bit PWM controls the duty control PWM signal in the conversion cycle 256 states. It counts the cycle and the duty cycle at 2 to 2 of the FRC. It can be used for controlling reel motors and loading motors.
  • Page 406: Section 22 Serial Communication Interface 1 (Sci1)

    Section 22 Serial Communication Interface 1 (SCI1) 22.1 Overview The serial communication interface (SCI) can handle both asynchronous and clocked synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function). 22.1.1 Features SCI1 features are listed below. •...
  • Page 407 • Full-duplex communication capability  The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously  Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data •...
  • Page 408: Block Diagram

    22.1.2 Block Diagram Figure 22.1 shows a block diagram of the SCI. Module data bus RDR1 TDR1 SCMR1 BRR1 SSR1 φ SCR1 Baud rate φ/4 RSR1 TSR1 generator SMR1 φ/16 Transmission/ φ/64 reception control Parity generation Clock Parity check External clock SCK1 [Legend] RSR1...
  • Page 409: Pin Configuration

    22.1.3 Pin Configuration Table 22.1 shows the serial pins used by the SCI. Table 22.1 SCI Pins Channel Pin Name Symbol Function Serial clock pin 1 SCK1 SCI1 clock input/output Receive data pin 1 Input SCI1 receive data input Transmit data pin 1 Output SCI1 transmit data output 22.1.4...
  • Page 410: Register Descriptions

    22.2 Register Descriptions 22.2.1 Receive Shift Register 1 (RSR1) Bit : R/W : — — — — — — — — RSR1 is a register used to receive serial data. The SCI sets serial data input from the SI1 pin in RSR1 in the order received, starting with the LSB (bit 0), and converts it to parallel data.
  • Page 411: Transmit Shift Register 1 (Tsr1)

    22.2.3 Transmit Shift Register 1 (TSR1) Bit : R/W : — — — — — — — — TSR1 is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR1 to TSR1, then sends the data to the SO1 pin starting with the LSB (bit 0).
  • Page 412: Serial Mode Register 1 (Smr1)

    22.2.5 Serial Mode Register 1 (SMR1) Bit : STOP CKS1 CKS0 Initial value : R/W : SMR1 is an 8-bit register used to set the SCI's serial transfer format and select the baud rate generator clock source. SMR1 can be read or written to by the CPU at all times. SMR1 is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode.
  • Page 413 Bit 5    Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In synchronous mode, or when a multiprocessor format is used, parity bit addition and checking is not performed, regardless of the PE bit setting.
  • Page 414 Bit 3    Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is only valid in asynchronous mode. If synchronous mode is set the STOP bit setting is invalid since stop bits are not added. Bit 3 STOP Description...
  • Page 415: Serial Control Register 1 (Scr1)

    Bits 1 and 0    Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The clock source can be selected from φ, φ/4, φ/16, and φ/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 22.2.8, Bit Rate Register 1.
  • Page 416 Bit 6    Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request generation when serial receive data is transferred from RSR1 to RDR1 and the RDRF flag in SSR1 is set to 1. Bit 6 Description Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request...
  • Page 417 Bit 3    Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when receiving with the MP bit in SMR1 set to 1. The MPIE bit setting is invalid in clock synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE Description...
  • Page 418 Bits 1 and 0    Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or the serial clock input pin.
  • Page 419: Serial Status Register 1 (Ssr1)

    22.2.7 Serial Status Register 1 (SSR1) Bit : TDRE RDRF ORER TEND MPBT Initial value : R/W : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written to clear the flag. SSR1 is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits.
  • Page 420 Bit 5    Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 5 ORER Description [Clearing conditions] (Initial value) When 0 is written in ORER after reading ORER = 1 [Setting conditions] When the next serial reception is completed while RDRF = 1 Notes: 1.
  • Page 421 Bit 3    Parity Error (PER): Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. Bit 4 Description [Clearing conditions] (Initial value) When 0 is written in PER after reading PER = 1 [Setting conditions] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/( bit in SMR1...
  • Page 422: Bit Rate Register 1 (Brr1)

    Bit 0    Multiprocessor Bit Transfer (MPBT): When transmission is performed using a multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid when a multiprocessor format is not used, when not transmitting, and in synchronous mode.
  • Page 423 Table 22.3 BRR1 Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency φ φ φ φ (MHz) 2.097152 2.4576 Error Error Error Error Bit Rate (bits/s) −0.04 −0.26 0.03 0.03 0.16 0.21 0.00 0.16 0.16 0.21 0.00 0.16 0.16 0.21 0.00 0.16 −0.70...
  • Page 424 Operating Frequency φ φ φ φ (MHz) 6.144 7.3728 Error Error Error Error Bit Rate (bits/s) −0.44 −0.07 0.08 0.03 0.16 0.00 0.00 0.16 0.16 0.00 0.00 0.16 0.16 0.00 0.00 0.16 1200 0.16 0.00 0.00 0.16 2400 0.16 0.00 0.00 0.16 4800...
  • Page 425 Table 22.4 BRR1 Settings for Various Bit Rates (Synchronous Mode) Operating Frequency φ φ φ φ (MHz) Bit Rate (bits/s)         2.5 k 10 k 25 k 50 k 100 k 250 k 500 k 2.5 M Note: As far as possible, the setting should be made so that the error is no more than 1%.
  • Page 426 The BRR1 setting is found from the following equations. • Asynchronous mode: φ 6 − 1 × 10 64 × 2 × B 2n−1 • Synchronous mode: φ 6 − 1 × 10 8 × 2 × B 2n−1 Where Bit rate (bits/s) BRR1 setting for baud rate generator (0 ≤...
  • Page 427 Table 22.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ φ φ φ (MHz) Maximum Bit Rate (bits/s) 62500 2.097152 65536 2.4576 76800 93750 3.6864 115200 125000 4.9152 153600 156250 187500 6.144 192000 7.3728 230400 250000 9.8304 307200 312500 Rev.
  • Page 428 Table 22.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) φ φ φ φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 0.7500 46875 3.6864 0.9216 57600 1.0000 62500 4.9152 1.2288 76800 1.2500...
  • Page 429: Serial Interface Mode Register 1 (Scmr1)

    22.2.9 Serial Interface Mode Register 1 (SCMR1) Bit : — — — — SDIR SINV — SMIF Initial value : R/W : — — — — — SCMR1 is an 8-bit readable/writable register used to select SCI functions. SCMR1 is initialized to H'F2 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode.
  • Page 430: Module Stop Control Register (Mstpcr)

    22.2.10 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control. When bit MSTP8 is set to 1, SCI1 operation stops at the end of the bus cycle and a transition is made to module stop mode.
  • Page 431: Operation

    22.3 Operation 22.3.1 Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or synchronous mode and the transmission format is made using SMR1 as shown in table 22.8.
  • Page 432 Table 22.8 SMR1 Settings and Serial Transfer Format Selection SMR1 Settings SCI Transfer Format Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 Data Multiproc- Parity Stop Bit C/$ $ $ $ STOP Mode Length essor Bit Length Asynchro- 8-bit 1 bit nous mode...
  • Page 433: Operation In Asynchronous Mode

    22.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and followed by one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-by- character basis.
  • Page 434 • Data Transfer Format Table 22.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected by settings in SMR1. Table 22.10 Serial Transfer Formats (Asynchronous Mode) SMR1 Settings Serial Transfer Format and Frame Length STOP 8-bit data STOP...
  • Page 435 • Clock Either an internal clock generated by the built-in baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/$ bit in SMR1 and the CKE1 and CKE0 bits in SCR1. For details of SCI clock source selection, see table 22.9.
  • Page 436 • Data Transfer Operations  SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, first clear the TE and RE bits in SCR1 to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure.
  • Page 437  Serial Data Transmission (Asynchronous Mode) Figure 22.5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. SCI initialization: Initialization The SO1 pin is automatically designated as the transmit data output pin. Start transmission SCI status check and transmit data write: Read SSR and check that the TDRE flag is...
  • Page 438 In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR1, and if it is 0, recognizes that data has been written to TDR1, and transfers the data from TDR1 to TSR1. 2. After transferring data from TDR1 to TSR1, the SCI sets the TDRE flag to 1 and starts transmission.
  • Page 439 Figure 22.6 shows an example of the operation for transmission in asynchronous mode. Data Data Start Parity Stop Parity Stop Start Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR1 and TXI interrupt request TEI interrupt request request TDRE flag cleared to 0 generated...
  • Page 440  Serial Data Reception (Asynchronous Mode) Figures 22.7 and 22.8 show sample flowcharts for serial reception. The following procedure should be used for serial data reception. SCI initialization: Initialization The SI1 pin is automatically designated as the receive data input pin. Start reception Receive error handling and break [2][3]...
  • Page 441 Error handling ORER=1 Overrun error handling FER=1 Break? Framing error handling Clear RE bit in SCR1 to 0 PER=1 Parity error handling Clear ORER, PER, and FER flags in SSR1 to 0 < End > Figure 22.8 Sample Serial Reception Data Flowchart (2) Rev.
  • Page 442 In serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in RSR1 in LSB-to-MSB order. 3.
  • Page 443: Multiprocessor Communication Function

    Figure 22.9 shows an example of the operation for reception in asynchronous mode. Data Data Start Parity Stop Parity Stop Start Idle state (mark state) RDRF RXI interrupt RDR1 data read ERI interrupt request request and RDRF flag generated by framing generation cleared to 0 in error...
  • Page 444 1. Data Transfer Format There are four data transfer formats. When a multiprocessor format is specified, the parity bit specification is invalid. For details, see table 22.10. 2. Clock See the section on asynchronous mode. Transmitting station Serial communication line Receiving Receiving Receiving...
  • Page 445 SCI initialization: Initialization The SO2 pin is automatically designated as the transmit data output pin. Start transmission SCI status check and transmit data write: Read SSR and check that the TDRE flag is Read TDRE flag in SSR1 set to 1, then write transmit data to TDR1. Set the MPBT bit in SSR1 to 0 or 1.
  • Page 446 In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR1, and if it is 0, recognizes that data has been written to TDR1, and transfers the data from TDR1 to TSR1. 2. After transferring data from TDR1 to TSR1, the SCI sets the TDRE flag to 1 and starts transmission.
  • Page 447 Figure 22.12 shows an example of SCI operation for transmission using a multiprocessor format. Multi- Multi- Data Data processor Start processor Stop Start Stop bit 1 Idle state (mark state) TDRE TEND Data written to TDR1 and TXI interrupt request TXI interrupt TEI interrupt TDRE flag cleared to 0...
  • Page 448 Initialization SCI initialization: The SI1 pin is automatically designated as the receive data input pin. Start reception ID reception cycle: Set the MPIE bit in SCR1 to 1. Set MPIE bit in SCR1 to 1 SCI status check, ID reception and Read ORER and FER flags in SSR1 comparison: Read SSR and check that the RDRF flag is...
  • Page 449 Error handling ORER=1 Overrun error handling FER=1 Break? Framing error handling Clear RE bit in SCR1 to 0 Clear ORER, PER, and FER flags in SSR1 to 0 < End > Figure 22.14 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 1.0, 02/00, page 440 of 1141...
  • Page 450 Figure 22.15 shows an example of SCI operation for multiprocessor format reception. Data (ID1) Data (Data 1) Start Stop Start Stop Idle state (mark state) MPIE RDRF RDR1 value MPIE=0 RXI interrupt RDR1 data read If not this station's RXI interrupt request request (multi- is not generated, and and RDRF flag...
  • Page 451: Operation In Synchronous Mode

    22.3.4 Operation in Synchronous Mode In synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer.
  • Page 452 • Data Transfer Operations  SCI Initialization (Synchronous Mode) Before transmitting and receiving data, first clear the TE and RE bits in SCR1 to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure.
  • Page 453  Serial Data Transmission (Synchronous Mode) Figure 22.18 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. SCI initialization: Initialization The SO2 pin is automatically designated as the transmit data output pin. Start transmission SCI status check and transmit data write: Read SSR1 and check that the TDRE flag...
  • Page 454 In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR1, and if it is 0, recognizes that data has been written to TDR1, and transfers the data from TDR1 to TSR1. 2. After transferring data from TDR1 to TSR1, the SCI sets the TDRE flag to 1 and starts transmission.
  • Page 455  Serial Data Reception (Synchronous Mode) Figure 22.20 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. When changing the operating mode from asynchronous to synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0. The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be possible.
  • Page 456 SCI initialization: Initialization The SI1 pin is automatically designated as the receive data input pin. Start reception Receive error handling: [2][3] IF a receive error occurs, read the ORER flag in SSR1, and after performing the Read ORER flag in SSR1 appropriate error handling, clear the ORER flag to 0.
  • Page 457 In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with serial clock input or output. 2. The received data is stored in RSR1 in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from RSR1 to RDR1.
  • Page 458  Simultaneous Serial Data Transmission and Reception (Synchronous Mode) Figure 22.22 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. SCI initialization: Initialization The SO2 pin is designated as the transmit data output pin, and the SI1 pin is Start transfer designated as the receive data input pin,...
  • Page 459: Sci Interrupts

    22.4 SCI Interrupts The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 22.12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in SCR1. Each kind of interrupt request is sent to the interrupt controller independently.
  • Page 460: Usage Notes

    22.5 Usage Notes The following points should be noted when using the SCI. • Relation between Writes to TDR1 and the TDRE Flag The TDRE flag in SSR1 is a status flag that indicates that transmit data has been transferred from TDR1 to TSR1.
  • Page 461 • Break Detection and Processing When framing error (FER) detection is performed, a break can be detected by reading the SI1 pin value directly. In a break, the input from the SI1 pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set.
  • Page 462 16 clocks 8 clocks 15 0 15 0 Internal basic clock Receive data Start bit Synchronization sampling timing Data sampling timing Figure 22.23 Receive Data Sampling Timing in Asynchronous Mode Thus the reception margin in asynchronous mode is given by formula (1) below. | D –...
  • Page 463 • Operation in Case of Mode Transition  Transmission Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module stop mode, standby mode, watch mode, subactive mode, or subsleep mode transition. TSR1, TDR1, and SSR1 are reset. The output pin states in module stop mode, standby mode, watch mode, subactive mode, or subsleep mode depend on the port settings, and becomes high-level output after the relevant mode is cleared.
  • Page 464 <Transmission> [1] Data being transmitted is interrupted. All data transmitted? After exiting software standby mode, etc., normal CPU transmis- sion is possible by setting TE to 1, reading SSR1, writing TDR1, and Read TEND flag in SSR1 clearing TDRE to 0. [2] If TIE and TEIE are set to 1, clear TEND = 1 them to 0 in the same way.
  • Page 465 Transition Exit from End of Start of transmission transmission to standby standby TE bit Port input/output SCK1 output pin SO1 output pin Port input/output High output Start Stop Port input/output High output SCI TxD Port Port SCI TxD output output Figure 22.25 Asynchronous Transmission Using Internal Clock End of Transition...
  • Page 466 <Reception> Read RDRF flag in SSR1 Receive data being received RDRF= 1 becomes invalid. Read receive data in RDR1 RE= 0 Transition to standby Includes module stop mode, mode, etc. watch mode, subactive mode, and subsleep mode. Exit from standby mode, etc.
  • Page 467: Section 23 I C Bus Interface (Iic)

    Section 23 I C Bus Interface (IIC) 23.1 Overview This LSI incorporates a 2-channel I C bus interface. The I C bus interface conforms to and provides a subset of the Philips I C bus (inter-IC bus) interface functions. The register configuration that controls the I C bus differs partly from the Philips configuration, however.
  • Page 468: Block Diagram

    23.1.2 Block Diagram Figure 23.1 shows a block diagram of the I C bus interface. Figure 23.2 shows an example of I/O pin connections to external circuits. I/O pins are driven only by NMOS and apparently function as NMOS open-drain outputs. However, applicable voltages to input pins depend on the power (Vcc) voltage of this LSI.
  • Page 469: Pin Configuration

    (Master) This chip (Slave 1) (Slave 2) Figure 23.2 I C Bus Interface Connections (Example: This Chip as Master) 23.1.3 Pin Configuration Table 23.1 summarizes the input/output pins used by the I C bus interface. Table 23.1 I C Bus Interface Pins Channel Name Abbrev.* I/O Function...
  • Page 470: Register Configuration

    23.1.4 Register Configuration Table 23.2 summarizes the registers of the I C bus interface. Table 23.2 Register Configuration Channel Name Abbrev. Initial Value Address C bus control register ICCR0 H'01 H'D0E8 C bus status register ICSR0 H'00 H'D0E9  C bus data register ICDR0 H'D0EE* C bus mode register...
  • Page 471: Register Descriptions

    23.2 Register Descriptions 23.2.1 C Bus Data Register (ICDR) Bit : ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0 Initial value : — — — — — — — — R/W : ICDRR Bit : ICDRR7 ICDRR6 ICDRR5 ICDRR4 ICDRR3 ICDRR2 ICDRR1 ICDRR0...
  • Page 472 ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is divided internally into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). ICDRS cannot be read or written by the CPU, ICDRR is read-only, and ICDRT is write-only.
  • Page 473 TDRE Description The next transmit data is in ICDR (ICDRT), or transmission cannot be started [Clearing conditions] (Initial value) 1. When transmit data is written in ICDR (ICDRT) in transmit mode (TRS = 1) 2. When a stop condition is detected in the bus line state after a stop condition is issued with the I C bus format or serial format selected 3.
  • Page 474: Slave Address Register (Sar)

    23.2.2 Slave Address Register (SAR) Bit : SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 Initial value : R/W : SAR is an 8-bit readable/writable register that stores the slave address and selects the communication format. When the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device.
  • Page 475 Bit 0    Format Select (FS): Used together with the FSX bit in SARX and the SW bit in DDCSWR to select the communication format. • I C bus format: addressing format with acknowledge bit • Synchronous serial format: non-addressing format without acknowledge bit, for master mode only •...
  • Page 476: Second Slave Address Register (Sarx)

    23.2.3 Second Slave Address Register (SARX) Bit : SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 Initial value : R/W : SARX is an 8-bit readable/writable register that stores the second slave address and selects the communication format. When the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device.
  • Page 477: C Bus Mode Register (Icmr)

    23.2.4 C Bus Mode Register (ICMR) Bit : WAIT CKS2 CKS1 CKS0 Initial value : R/W : ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the master mode transfer clock frequency and the transfer bit count.
  • Page 478 Bit 6    Wait Insertion Bit (WAIT) Selects whether to insert a wait between the transfer of data and the acknowledge bit, in master mode with the I C bus format. When WAIT is set to 1, after the fall of the clock for the final data bit, the IRIC flag is set to 1 in ICCR, and a wait state begins (with SCL at the low level).
  • Page 479 Bits 5 to 3    Transfer Clock Select (CKS2 to CKS0): These bits, together with the IICX1 bit (for channel 1) or IICX0 bit (for channel 0) in STCR, select the serial clock frequency in master mode. They should be set according to the required transfer rate. STCR Bits 5, 6 Bit 5...
  • Page 480 Bits 2 to 0    Bit Counter (BC2 to BC0): Bits BC2 to BC0 specify the number of bits to be transferred next. With the I C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the data is transferred with one addition acknowledge bit.
  • Page 481: C Bus Control Register (Iccr)

    23.2.5 C Bus Control Register (ICCR) Bit : IEIC ACKE BBSY IRIC Initial value : R/(W)* R/W : Note: * Only 0 can be written to clear the flag. ICCR is an 8-bit readable/writable register that enables or disables the I C bus interface, enables or disables interrupts, selects master or slave mode and transmission or reception, enables or disables acknowledgement, confirms the I...
  • Page 482 Bits 5 and 4    Master/Slave Select (MST) and Transmit/Receive Select (TRS): MST selects whether the I C bus interface operates in master mode or slave mode. TRS selects whether the I C bus interface operates in transmit mode or receive mode. In master mode with the I C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode.
  • Page 483 Bit 4 Description Receive mode (Initial value) [Clearing conditions] 1. When 0 is written by software (in cases other than setting condition 3) 2. When 0 is written in TRS after reading TRS = 1 (in case of setting condition 3) 3.
  • Page 484 Bit 2    Bus Busy (BBSY): The BBSY flag can be read to check whether the I C bus (SCL, SDA) is busy or free. In master mode, this bit is also used to issue start and stop conditions. A high-to-low transition of SDA while SCL is high is recognized as a start condition, setting BBSY to 1.
  • Page 485 Bit 1 IRIC Description Waiting for transfer, or transfer in progress (Initial value) [Clearing condition] When 0 is written in IRIC after reading IRIC = 1 Interrupt requested [Setting conditions] • I C bus format master mode 1. When a start condition is detected in the bus line state after a start condition is issued (when the TDRE flag is set to 1 because of first frame transmission) 2.
  • Page 486 When, with the I C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer. When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set.
  • Page 487 Table 23.3 Flags and Transfer States BBSY ESTP STOP IRTR AASX AL ACKB State Idle state (flag clearing required) Start condition issuance Start condition established Master mode wait Master mode transmit/receive end Arbitration lost SAR match by first frame in slave mode General call address match SARX match...
  • Page 488: C Bus Status Register (Icsr)

    23.2.6 C Bus Status Register (ICSR) Bit : ESTP STOP IRTR AASX ACKB Initial value : R/W : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written to clear the flag. ICSR is an 8-bit readable/writable register that performs flag confirmation and acknowledge confirmation and control.
  • Page 489 Bit 6    Normal Stop Condition Detection Flag (STOP): Indicates that a stop condition has been detected after completion of frame transfer in I C bus format slave mode. Bit 6 STOP Description No normal stop condition (Initial value) [Clearing condition] 1.
  • Page 490 Bit 4    Second Slave Address Recognition Flag (AASX): In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX. AASX is cleared by reading AASX after it has been set to 1, then writing 0 in AASX.
  • Page 491 Bit 2    Slave Address Recognition Flag (AAS): In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected.
  • Page 492: Serial/Timer Control Register (Stcr)

    Bit 0    Acknowledge Bit (ACKB): Stores acknowledge data. In transmit mode, after the receiving device receives data, it returns acknowledge data, and this data is loaded into ACKB. In receive mode, after data has been received, the acknowledge data set in this bit is sent to the transmitting device.
  • Page 493: Ddc Switch Register (Ddcswr)

    23.2.8 DDC Switch Register (DDCSWR) Bit : CLR3 CLR2 CLR1 CLR0 Initial value : R/W : R/(W)* Notes: 1. Only 0 can be written to clear the flag. Always read as 1. DDCSWR is an 8-bit read/write register that controls automatic format switching for IIC channel 0 and IIC internal latch clearing.
  • Page 494 Bit 5    DDC Mode Switch Interrupt Enable Bit (IE): Enables or disables an interrupt request to the CPU when the format for IIC channel 0 is automatically switched. Bit 5 Description Disables an interrupt at automatic format switching (Initial value) Enables an interrupt at automatic format switching Bit 4...
  • Page 495 Bit 3 Bit 2 Bit 1 Bit 0 CLR3 CLR2 CLR1 CLR0 Description   This setting must not be used This setting must not be used IIC0 internal latch cleared IIC1 internal latch cleared IIC 0 and IIC1 internal latches cleared ...
  • Page 496: Module Stop Control Register (Mstpcr)

    23.2.9 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Bit : MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop mode control.
  • Page 497: Operation

    23.3 Operation 23.3.1 C Bus Data Format The I C bus interface has serial and I C bus formats. The I C bus formats are addressing formats with an acknowledge bit. These are shown in figures 23.3(1) and (2). The first frame following a start condition always consists of 8 bits. Formatless transfer can be selected only for IIC channel 0.
  • Page 498: Master Transmit Operation

    FS = 1 and FSX = 1 DATA DATA Transfer bit count (n = 1 to 8) Transfer frame count (m = 1 or above) Figure 23.4 I C Bus Data Format (Serial Format) DATA DATA Figure 23.5 I C Bus Timing Table 23.4 I C Bus Data Format Symbols Symbol...
  • Page 499 TDRE internal flag is set to 1 and the IRIC and IRTR flags are also set to 1. If IEIC is set to 1 in ICCR, a CPU interrupt is requested. 3. If bit FS is 0 in SAR or bit FSX is 0 in SARX, the first frame following the start condition contains a 7-bit slave address and indicates the transmit/receive direction.
  • Page 500 Start condition issuance (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 (Master output) Slave address Data 1 (Slave output) TDRE Interrupt Interrupt request IRIC request generated generated ICDRT Data 1...
  • Page 501 When continuously transmitting data, 6. Clear IRIC flag to 0 before startup of the 9th transmit clock of the data being transmitted, and then write the next transmit data in ICDR. 7. 1 frame data transmission ends, and upon startup of the 9th transmit clock, IRIC flag in ICCR is set to 1.
  • Page 502: Master Receive Operation

    23.3.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. The slave device transmits the data. The receive procedure and operations in master receive mode are described below. 1.
  • Page 503 Master transmit Master receive mode mode (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 (Slave output) Data 1 Data 2 (Master output) RDRF Interrupt Interrupt IRIC request request generated...
  • Page 504: Slave Receive Operation

    23.3.4 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The receive procedure and operations in slave receive mode are described below. 1. Set bit ICE in ICCR to 1. Set bits MLS in ICMR and bits MST and TRS in ICCR according to the operating mode.
  • Page 505 Start condition issurance (Master output) (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 (Master output) Slave address Data 1 (Slave output) RDRF Interrupt request IRIC generated ICDRS Address + R/W ICDRR...
  • Page 506 (Master output) (Slave output) Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Master output) Data 1 Data 2 (Slave output) RDRF Interrupt Interrupt IRIC request request generated generated ICDRS Data 1 Data 2...
  • Page 507: Slave Transmit Operation

    23.3.5 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, and the master device outputs the transmit clock and returns an acknowledge signal. The transmit procedure and operations in slave transmit mode are described below. 1.
  • Page 508: Iric Setting Timing And Scl Control

    Slave receive mode Slave transmit mode (Master output) (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 (Slave output) Data 1 Data 2 (Master output) TDRE Interrupt Interrupt Interrupt IRIC...
  • Page 509 (a) When WAIT = 0, and FS = 0 or FSX = 0 (I C bus format, no wait) IRIC User Clear Write to ICDR (transmit) or processing IRIC read ICDR (receive) (b) When WAIT = 1, and FS = 0 or FSX = 0 (I C bus format, wait inserted) IRIC User...
  • Page 510: Automatic Switching From Formatless Transfer To I

    23.3.7 Automatic Switching from Formatless Transfer to I C Bus Format Transfer Setting the SW bit in DDCSWR to 1 selects the IIC0 formatless transfer operation. When an SCL falling edge is detected, the operating mode automatically switches from formatless transfer to I bus format transfer (slave mode).
  • Page 511: Noise Canceler

    23.3.8 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 23.13 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree.
  • Page 512 Start Test the status of the SCL and SDA lines. Initialize Select master transmit mode. Read BBSY flag in ICCR Generate a start condition. Set transmit data for the first byte (slave BBSY=0? address +R/W) Wait for 1 byte to be transmitted. Set MST=1 and TRS=1 in ICCR Test for acknowledgement by the...
  • Page 513 Master receive mode Select receive mode. Set TRS=0 in ICCR Set acknowledge data. Clear IRIC flag in ICCR Start receiving. The first read is a dummy Set ACKB=0 in ICSR read. Wait for 1 byte to be received. Last receive? Set acknowledge data for the last receive.
  • Page 514 Start Initialize Set MST=0 and TRS=0 in ICCR Set ACKB=0 in ICSR Read IRIC flag in ICCR IRIC=1? Read AAS and ADZ flags in ICSR AAS=1 and General call address processing ADZ=0? *Description omitted Read TRS bit in ICCR Slave transmit mode TRS=0? Last receive? Read ICDR...
  • Page 515: 23.3.10 Initializing Internal Status

    Set transmit data for the second and Slave transmit mode subsequent bytes. Clear IRIC in ICCR Wait for 1 byte to be transmitted. Write transmit data in ICDR Test for end of transfer. Clear IRIC flag in ICCR Select slave receive mode. Dummy read (to release the SCL line).
  • Page 516 • Internal latches which holds the register read information to set or clear the flags in ICMR, ICCR, ICSR, and DDCSWR • Bit counter (BC2 to BC0) value in ICMR • Sources of interrupts generated (interrupts that has been transferred to the interrupt controller) (2) Notes on Initialization •...
  • Page 517: Usage Notes

    23.4 Usage Notes 1. In master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly. To output consecutive start and stop conditions, after issuing the instruction that generates the start condition, read the relevant ports, check that SCL and SDA are both low, then issue the instruction that generates the stop condition.
  • Page 518 5. The I C bus interface specification for the SCL rise time t is under 1000 ns (300 ns for high- speed mode). In master mode, the I C bus interface monitors the SCL line and synchronizes one bit at a time during communication. If t (the time for SCL to go from low to V ) exceeds the time determined by the input clock of the I...
  • Page 519 7. Precautions on reading ICDR at the end of master receive mode When terminating the master receive mode, set TRS bit to 1, and select "write" for ICCR BBSY = 0 and SCP = 0. This forces to move SDA from low to high level when SCL is at high level, thereby generating the stop condition.
  • Page 520 Table 23.7 I C Bus Timing (with Maximum Influence of t Time Indication (at Maximum Transfer Rate) [ns] C Bus Influence Specification φ φ φ φ = 8 MHz φ φ φ φ = 10 MHz Item Indication (Max.) (Min.) −1000 ←...
  • Page 521: Section 24 A/D Converter

    Section 24 A/D Converter 24.1 Overview This LSI incorporates a 10-bit successive-approximations A/D converter that allows up to 12 analog input channels to be selected. 24.1.1 Features A/D converter has the following features. • 10-bit resolution • 12 input channels •...
  • Page 522: Block Diagram

    24.1.2 Block Diagram Figure 24.1 shows a block diagram of the A/D converter. Internal data bus Reference Voltage 10-bit Hardware control circuit ADTRG (HSW timing generator) Vref ADTRG Chopper type Control circuit comparator φ/2 Sample-and- φ/4 hold circuit Interrupt request [Legend] : Software trigger A/D result register ADTRG, DFG...
  • Page 523: Pin Configuration

    24.1.3 Pin Configuration Table 24.1 summarizes the input pins used by the A/D converter. Table 24.1 A/D Converter Pins Name Abbrev. Function Analog power supply pin Input Analog block power supply and A/D conversion reference voltage Analog ground pin Input Analog block ground and A/D conversion reference voltage Analog input pin 0...
  • Page 524: Register Configuration

    24.1.4 Register Configuration Table 24.2 summarizes the registers of the A/D converter. Table 24.2 A/D Converter Registers Name Abbrev. Size Initial Value Address Software trigger A/D ADRH Byte H'00 H'D130 result register H Software trigger A/D ADRL Byte H'00 H'D131 result register L Hardware trigger A/D AHRH...
  • Page 525: Register Descriptions

    24.2 Register Descriptions 24.2.1 Software-Triggered A/D Result Register (ADR) ADRH ADRL Bit : ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 — — — — — — Initial value : — — — — — — R/W : The software-triggered A/D result register (ADR) is a register that stores the result of an A/D conversion started by software.
  • Page 526: A/D Control Register (Adcr)

    AHR can be read by the CPU at any time, but the AHR value during A/D conversion is not fixed. The upper bytes can always be read directly, but the data in the lower bytes is transferred via a temporary register (TEMP). For details, see section 24.3, Interface to Bus Master. AHR is a 16-bit read-only register which is initialized to H'0000 at a reset, and in module stop mode, standby mode, watch mode, subactive mode and subsleep mode.
  • Page 527 States Instruction execution MOV.B WRITE Start flag Conversion frequency Conversion period (134 or 266 states) Interrupt request flag IRQ sampling (CPU) Note: IRQ sampling; When conversion ends, the start flag is cleared and the interrupt request flag is set. The CPU recognizes the interrupt in the last execution state of an instruction, and executes interrupt exception handling after completing the instruction.
  • Page 528 Bits 3 to 0    Software Channel Select (SCH3 to SCH0): These bits select the analog input channel that is converted by software triggering. When channels AN0 to AN7 are used, appropriate pin settings must be made in port mode register 0 (PMR0).
  • Page 529: A/D Control/Status Register (Adcsr)

    24.2.4 A/D Control/Status Register (ADCSR) Bit : SEND HEND ADIE BUSY SCNL — Initial value : R/(W)* R/(W)* — R/W : Note: * Only 0 can be written to bits 7 and 6, to clear the flag. The A/D status register (ADCSR) is an 8-bit register that can be used to start or stop A/D conversion, or check the status of the A/D converter.
  • Page 530 Bit 5    A/D Interrupt Enable (ADIE): Selects enable or disable of interrupt (ADI) generation upon A/D conversion end. Bit 5 ADIE Description Interrupt (ADI) upon A/D conversion end is disabled (Initial value) Interrupt (ADI) upon A/D conversion end is enabled Bit 4...
  • Page 531 Bit 2    Busy Flag (BUSY): During hardware- or external-triggered A/D conversion, if software attempts to start A/D conversion by writing to the SST bit, the SST bit is not modified and instead the BUSY flag is set to 1. This flag is cleared when the hardware-triggered A/D result register (AHR) is read.
  • Page 532: Trigger Select Register (Adtsr)

    24.2.5 Trigger Select Register (ADTSR) Bit : — — — — — — TRGS1 TRGS0 Initial value : R/W : — — — — — — The trigger select register (ADTSR) selects hardware- or external-triggered A/D conversion start factor. ADTSR is an 8-bit readable/writable register that is initialized to H'FC by a reset, and in module stop mode, standby mode, watch mode, subactive mode and subsleep mode.
  • Page 533: Module Stop Control Register (Mstpcr)

    Bits 7 to 0    P07/AN7 to P00/AN0 Pin Switching (PMR07 to PMR00): These bits set the P0n/ANn pin as the input pin for P0n or as the ANn pin for A/D conversion analog input channel. Bit n PMR0n Description P0n/ANn functions as a general-purpose input port...
  • Page 534: Interface To Bus Master

    24.3 Interface to Bus Master ADR and AHR are 16-bit registers, but the data bus to the bus master is only 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP).
  • Page 535: Operation

    24.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. 24.4.1 Software-Triggered A/D Conversion A/D conversion starts when software sets the software A/D start flag (SST bit) to 1. The SST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. Conversion can be software-triggered on any of the 12 channels provided by analog input pins AN0 to ANB.
  • Page 536: Hardware- Or External-Triggered A/D Conversion

    24.4.2 Hardware- or External-Triggered A/D Conversion The system contains the hardware trigger function that allows to turn on A/D conversion at a specified timing by use of the hardware trigger (internal signals: ADTRG and DFG) and the incoming external trigger ($'75*). This function can be used to measure an analog signal that varies in synchronization with an external signal at a fixed timing.
  • Page 537: Interrupt Sources

    24.5 Interrupt Sources When A/D conversion ends, SEND or HEND flag in ADCSR is set to 1. The A/D conversion end interrupt (ADI) can be enabled or disabled by ADIE bit in ADCSR. Figure 24.4 shows the block diagram of A/D conversion end interrupt. A/D control/status register (ADCSR) SEND HEND...
  • Page 538: Section 25 Address Trap Controller (Atc)

    Section 25 Address Trap Controller (ATC) 25.1 Overview The address trap controller (ATC) is capable of generating interrupt by setting an address to trap, when the address set appears during bus cycle. 25.1.1 Features Address to trap can be set independently at three points. 25.1.2 Block Diagram Figure 25.1 shows a block diagram of the address trap controller.
  • Page 539: Register Configuration

    25.1.3 Register Configuration Table 25.1 Register List Name Abbrev. Initial Value Address * Address trap control register ATCR H'F8 H'FFB9 Trap address register 0 TAR0 H'F00000 H'FFB0 to H'FFB2 Trap address register 1 TAR1 H'F00000 H'FFB3 to H'FFB5 Trap address register 2 TAR2 H'F00000 H'FFB6 to H'FFB8...
  • Page 540 Bit 1    Trap Control 1 (TRC1): Sets ON/OFF operation of the address trap function 1. Bit 1 TRC1 Description Address trap function 1 disabled (Initial value) Address trap function 1 enabled Bit 0    Trap Control 0 (TRC0): Sets ON/OFF operation of the address trap function 0. Bit 0 TRC0 Description...
  • Page 541: Trap Address Register 2 To 0 (Tar2 To Tar0)

    25.2.2 Trap Address Register 2 to 0 (TAR2 to TAR0) Bit : Initial value : R/W : Bit : Initial value : R/W : Bit : — Initial value : — R/W : The TAR is composed of three 8-bit readable/writable registers (TARnA, B, and C)(n = 2 to 0) The TAR sets the address to trap.
  • Page 542: Precautions In Usage

    25.3 Precautions in Usage Address trap interrupt arises 2 states after prefetching the trap address. Trap interrupt may occur after the trap instruction has been executed, depending on a combination of instructions immediately preceding the setting up of the address trap. If the instruction to trap immediately follows the branch instruction or the conditional branch instruction, operation may differ, depending on whether the condition was satisfied or not, or the address to be stacked may be located at the branch.
  • Page 543 2. Figure 25.3 shows the operation when the instruction immediately preceding the trap address is that of 2 states or more of the execution cycle and the next instruction prefetch occurs in the second state from the last. The address to be stacked is 0268. Start of exception Data instruc-...
  • Page 544: Enabling

    25.3.2 Enabling The address trap function becomes valid after executing one instruction following the setting of the enable bit of the address trap control register (TRCR) to 1. 029C BSET #0, @TRCR MOV.W R0, R1 *029E After executing the MOV instruction, 02A0 MOV.B R1L, R3H the address trap interrupt does not...
  • Page 545 2. When the condition is not satisfied by Bcc instruction (8-bit displacement) If the trap address is the next instruction to the Bcc instruction and the condition is not satisfied by the Bcc instruction and thus it fails to branch, transition is made to the address trap interrupt after executing the trap address instruction and prefetching the next instruction.
  • Page 546 3. When condition is not satisfied by Bcc instruction (16-bit displacement) If the trap address is the next instruction to the Bcc instruction and the condition is not satisfied by the Bcc instruction and thus it fails to branch, transition is made to the address trap interrupt after executing the trap address instruction (if the trap address instruction is that of 2 states or more.
  • Page 547 4. When the condition is not satisfied by Bcc instruction (Trap address at branch) When the trap address is at the branch of the Bcc instruction and the condition is not satisfied by the Bcc instruction and thus it fails to branch, transition is made into the address trap interrupt after executing the next instruction (if the next instruction is that of 2 states or more.
  • Page 548: Bsr Instruction

    25.3.4 BSR Instruction 1. BSR Instruction (8-bit displacement) When the trap address is the next instruction to the BSR instruction and the addressing mode is an 8-bit displacement, transition is made to the address trap interrupt after prefetching the instruction at the branch. The address to be stacked is 02C2. Stack Start of instruc-...
  • Page 549: Jsr Instruction

    25.3.5 JSR Instruction 1. JSR Instruction (Register indirect) When the trap address is the next instruction to the JSR instruction and the addressing mode is a register indirect, transition is made to the address trap interrupt after prefetching the instruction at the branch. The address to be stacked is 02C8. Stack Start of instruc-...
  • Page 550 2. JSR Instruction (Memory indirect) When the trap address is the next instruction to the JSR instruction and the addressing mode is memory indirect, transition is made to the address trap interrupt after prefetching the instruction at the branch. The address to be stacked is 02EA. Start of Data Stack...
  • Page 551: Jmp Instruction

    25.3.6 JMP Instruction 1. JMP Instruction (Register indirect) When the trap address is the next instruction to the JMP instruction and the addressing mode is a register indirect, transition is made to the address trap interrupt after prefetching the instruction at the branch. The address to be stacked is 02AA. Data Start of instruc-...
  • Page 552: Rts Instruction

    2. JMP Instruction (Memory indirect) When the trap address is the next instruction to the JMP instruction and the addressing mode is memory indirect, transition is made to the address trap interrupt after prefetching the instruction at the branch. The address to be stacked is 02E4. Internal Data Start of...
  • Page 553: Sleep Instruction

    25.3.8 SLEEP Instruction 1. SLEEP Instruction 1 When the trap address is the SLEEP instruction and the instruction execution cycle immediately preceding the SLEEP in