Interrupt Exception Handling Sequence - Hitachi H8S/2199 Hardware Manual

Single-chip microcomputer
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6.4.4

Interrupt Exception Handling Sequence

Figure 6.8 shows the interrupt exception handling sequence. The example shown is for the case
where interrupt control 0 is set in advanced mode, and the program area and stack area are in on-
chip memory.
Figure 6.8 Interrupt Exception Handling
Rev. 1.0, 02/00, page 118 of 1141

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