Hitachi H8/300L Series Programming Manual
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Hitachi H8/300L Series Programming Manual

Hitachi H8/300L Series Programming Manual

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  • Page 1 H8/300L Series Programming Manual...
  • Page 2 Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document.

  • Page 3: Table Of Contents

    Contents Preface ......................1 Section 1. CPU....................3 1.1 Overview ......................... 3 1.1.1 Features ......................3 1.1.2 Data Structure..................... 4 1.1.3 Address Space..................... 6 1.1.4 Register Configuration..................6 1.2 Registers .......................... 7 1.2.1 General Registers....................7 1.2.2 Control Registers ....................7 1.2.3 Initial Register Values ..................
  • Page 4 2.2.17 BSET (bit set) ....................65 2.2.18 BSR (branch to subroutine)................67 2.2.19 BST (bit store) ....................68 2.2.20 BTST (bit test)....................70 2.2.21 BXOR (bit exclusive OR) ................. 72 2.2.22 (1) CMP (compare) (byte) CMP................ 74 2.2.22 (2) CMP (compare) (word)................75 2.2.23 DAA (decimal adjust add) ................
  • Page 5 2.2.53(2) SUB (subtract binary) (word)................ 123 2.2.54 SUBS (subtract with sign extension) ..............124 2.2.55 SUBX (subtract with extend carry) ..............125 2.2.56 XOR (exclusive OR logical) ................126 2.2.57 XORC (exclusive OR control register).............. 127 2.3 Operation Code Map......................128 2.4 List of Instructions ......................

  • Page 7: Preface

    This manual gives detailed descriptions of the H8/300L instructions. The descriptions apply to all chips in the H8/300L Series. Assembly-language programmers should also read the separate H8/300 Series Cross Assembler User's Manual. For hardware details, refer to the hardware manual of the specific chip.

  • Page 9: Section 1. Cpu

    Section 1. CPU Overview The H8/300L CPU at the heart of the H8/300L Series features 16 general registers of 8 bits each (or 8 registers of 16-bits each), and a concise, optimized instruction set geared to high-speed operation. 1.1.1 Features The H8/300L CPU has the following features.

  • Page 10: Data Structure

    1.1.2 Data Structure The H8/300L CPU can process 1-bit data, 4-bit (packed BCD) data, 8-bit (byte) data, and 1 6-bit (word) data. • Bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a byte operand.
  • Page 11 0.* The same applies to instruction codes. Note that the LSIs in the H8/300L Series also contain on-chip peripheral modules for which access in word size is not possible. Details are given in the applicable hardware manual.

  • Page 12: Address Space

    1.1.3 Address Space The H8/300L CPU supports a 64-Kbyte address space (program code + data). The memory map differs depending on the particular chip in the H8/300L Series and its operating mode. See the applicable hardware manual for details. 1.1.4 Register Configuration Figure 1-3 shows the register configuration of the H8/300L CPU.

  • Page 13: Registers

    Registers 1.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7). When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high (R0H to R7H) and low (R0L to R7L) bytes can be accessed separately as 8-bit registers.

  • Page 14: Initial Register Values

    Initial value Read/Write Not fixed Bit 7--Interrupt Mask Bit (I): When this bit is set to 1, all interrupts except NMI are masked. This bit is set to I automatically at the start of interrupt handling. Bits 6 and 4--User Bits (U): These bits can be written and read by software for its own purposes using LDC, STC, ANDC, ORC, and XORC instructions.

  • Page 15: Instructions

    Instructions Features: • The H8/300L CPU has a concise set of 55 instructions. • A general-register architecture is adopted. • All instructions are 2 or 4 bytes long. • Fast multiply/divide instructions and extensive bit manipulation instructions are supported. • Eight addressing modes are supported. 1.3.1 Types of Instructions Table 1-1 classifies the H8/300L instructions by type.
  • Page 16 Notation General register (destination) General register (source) General register (EAd) Destination operand (EAs) Source operand Condition code register N (negative) bit of CCR Z (zero) bit of CCR V (overflow) bit of CCR C (carry) bit of CCR Program counter Stack pointer (R7) #Imm Immediate data...
  • Page 17 Table 1-2. Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:8 or #xx:16, @-Rn, and @Rn+ addressing modes are available for byte or word data.
  • Page 18 Table 1-3. Arithmetic Instructions Instruction Size* Function Rd ± Rs → Rd, Rd + #Imm → Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register.
  • Page 19 Table 1-4. Logic operation Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #Imm → Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #Imm → Rd Performs a logical OR operation on a general register and another general register or immediate data.
  • Page 20 Table 1-6. Bit Manipulation Instructions Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory to 1. The bit is specified by a bit number, given in 3-bit immediate data or the lower three bits of a general register. 0 →...
  • Page 21 Table 1-7. Branching Instructions Instruction Size Function Branches if condition cc is true. The branching conditions are as follows. Mnemonic Description Condition BRA (BT) Always (True) Always BRN (BF) Never (False) Never C ∨ Z = 0 High C ∨ Z = 1 Low or Same BCC (BHS) Carry Clear (High...
  • Page 22 Execution of the next instruction starts as soon as the block transfer is completed. This instruction is for writing to the large-capacity EEPROM provided on chip with some models in the H8/300L Series. For details see the applicable hardware manual.
  • Page 23 Notes on Bit Manipulation Instructions: BSET, BCLR, BNOT, BST, and BIST are read- modify-write instructions. They read a byte of data, modify one bit in the byte, then write the byte back. Care is required when these instructions are applied to registers with write-only bits and to the I/O port registers.
  • Page 24 Explanation: To execute the BCLR instruction, the CPU begins by reading PCR4. Since PCR4 is a write-only register, it is read as H'FF, even though its true value is H'3F. Next the CPU clears bit 0 of the read data, changing the value to H'FE. Finally, the CPU writes this value (H'FE) back to PCR4 to complete the BCLR instruction.
  • Page 25 Explanation: To execute the BSET instruction, the CPU begins by reading port 4. Since P47 and P46 are input pins, the CPU reads the level of these pins directly, not the value in the port data register. It reads P47 as Low (0) and P46 as High (1). Since P45 to P40 are output pins, for these pins the CPU reads the value in PDR4.

  • Page 26: Basic Instruction Formats

    1.3.3 Basic Instruction Formats (1) Format of Data Transfer Instructions Figure 1-5 shows the format used for data transfer instructions. @Rm, or @Rm @(d:16,Rm) Rn, or @(d:16,Rm) disp. @ Rm+ Rn, or Rn @-Rm @ aa :8 Rn, or Rn @ aa :8 abs.
  • Page 27 (2) Format of Arithmetic, Logic Operation, and Shift Instructions Figure 1-6 shows the format used for arithmetic, logic operation, and shift instructions. ADD, SUB, CMP(Rm) ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT MULXU, DIVXU ADD, ADDX, SUBX, CMP (#xx :8) AND, OR, XOR (Rm) AND, OR, XOR (#xx:8)
  • Page 28 (3) Format of Bit Manipulation Instructions Figure 1-7 shows the format used for bit manipulation instructions. BSET, BCLR, BNOT, BTST Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register direct (Rn) Bit No.: register direct (Rm) Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) Bit No.: register direct (Rm)
  • Page 29 BIAND, BIOR, BIXOR, BILD, BIST Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) Operand: absolute (@aa:8) abs. Bit No.: immediate (#xx:3) Notation Operation field r , r Register field abs. Absolute address Immediate data Figure 1-7.
  • Page 30 (4) Format of Branching Instructions Figure 1-8 shows the format used for branching instructions. disp. 0 0 0 JMP (@Rm) JMP (@aa:16) abs. abs. JMP (@@aa:8) disp. JSR (@Rm) JSR (@aa:16) abs. abs. JSR (@@aa:8) Notation Operation field Condition field Register field disp.

  • Page 31: Addressing Modes And Effective Address Calculation

    (5) Format of System Control Instructions Figure 1-9 shows the format used for system control instructions. RTE, SLEEP, NOP LDC, STC (Rn) ANDC, ORC,XORC, LDC (#xx:8) Notation Operation field r , r Register field Immediate data Figure 1-9. Instruction Format of System Control Instructions (6) Format of Block Data Transfer Instruction Figure 1-10 shows the format used for the block data transfer instruction.
  • Page 32 Table 1-10. Addressing Modes Mode Notation Register direct Register indirect Register indirect with 16-bit displacement @(d:16, Rn) Register indirect with post-increment @Rn+ Register indirect with pre-decrement @-Rn Absolute address (8 or 16 bits) @aa:8, @aa:16 Immediate (3-, 8-, or 16-bit data) #xx:3, #xx:8, #xx:16 PC-relative (8-bit displacement) @(d:8, PC)
  • Page 33 (5) Absolute Address--@aa:8 or @aa:16: The instruction specifies the absolute address of the operand in memory. The @aa:8 mode uses an 8-bit absolute address of the form H'FFxx. The upper 8 bits are assumed to be 1, so the possible address range is H'FF00 to H'FFFF (65280 to 65535).
  • Page 34 Effective Address Calculation Table 1-11 explains how the effective address is calculated in each addressing mode. Table 1-11. Effective Address Calculation (1) No. Addressing mode, instruction format Effective address calculation Effective address Register direct Rn None reg n reg m reg m reg n Operand are contained in registers m and n...
  • Page 35 Table 1-11. Effective Address Calculation (2) Addressing mode, instruction Effective address Effective format calculation address Register indirect with displacement @(d:16, Rn) 16 - bit register contents 16 - bit displacement Operand address is sum disp of register contents and displacement Register indirect with pre- decrement @-Rn 16 - bit register contents...
  • Page 36 Table 1-11. Effective Address Calculation (3) No. Addressing mode, instruction format Effective address calculation Effective address Immediate #xx:8. None Operand is 1 - byte immediate data Immediate #xx:16 None Operand is 2 - byte immediate data PC-relative @(d:8, PC) PC contents disp Sign extension Destination address...

  • Page 37: Section 2. Instruction Set

    Section 2. Instruction Set Explanation Format Section 2 gives full descriptions of all the H8/300L Series instructions, presenting them in alphabetic order. Each instruction is explained in a table like the following: ADD (add binary) (byte) Operation Rd + (EAs) → Rd Assembly-Language Format b ADD.B <EAs>, Rd...
  • Page 38 Instruction Formats and Number of Execution States Instruction code Addressing mode Mnem. Operands 1st byte 2nd byte 3rd byte 4th byte No. of states Immediate ADD.B #xx:8, Rd Register direct ADD.B Rs, Rd The parts of the table are explained below. Name: The full and mnemonic names of the instruction are given at the top of the page.
  • Page 39 Assembly-Language Format: The assembly-language coding of the instruction is given. An example is: ADD. <EAs>, Rd Mnemonic Size Source Destination The operand size is indicated by the letter B (byte) or W (word). Some instructions have restrictions on the size of operands they handle. The abbreviation EAs or EAd (effective address of source or destination) is used for operands that permit more than one addressing mode.
  • Page 40 instruction and its operands are located in on-chip memory. The following symbols are used: Symbol Meaning Imm. Immediate data (3, 8, or 16 bits) abs. An absolute address (8 bits or 16 bits) disp. Displacement (8 bits or 16 bits) rs, rd, rn General register number (3 bits or 4 bits) The s, d, and n correspond to the letters in the operand notation.
  • Page 41 BSET R1L, R2H don't care Bit number = 3 Bit 3 is set to 1 BLD # 5, @H'FF02 : 8 Bit No. 5 H'FF02 Loaded to C (carry) flag in CCR The addressing mode and operand size apply to the register or memory byte containing the bit. Number of States Required for Execution: The number of states indicated is the number required when the instruction and any memory operands are located in on-chip ROM or RAM.

  • Page 42: 2.2 Instructions

    the instruction or an operand is located in external memory or the on-chip register field, additional states are required for each access. See section 2.5, Number of Execution States. 2.2 Instructions 2.2.1(1) ADD (add binary) (byte) Operation Rd+ (EAs) → Rd Assembly-Language Format ADD.B <EAs>, Rd Operand Size...

  • Page 43: 2) Add (Add Binary) (Word)

    2.2.1 (2) ADD (add binary) (word) Operation Rd + Rs → Rd Assembly-Language Format ADD.W Rs, Rd Operand Size Word Condition Code ∆ ∆ ∆ ∆ ∆ — — — Previous value remains unchanged. Set to 1 when there is a carry from bit 11; otherwise cleared to 0. Set to 1 when the result is negative;...

  • Page 44: Adds (Add With Sign Extension)

    2.2.2 ADDS (add with sign extension) Operation Rd+1 → Rd Rd+2 → Rd Assembly-Language Format ADDS #1, Rd ADDS #2, Rd Operand Size Word Condition Code — — — — — — — — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.

  • Page 45: Addx (Add With Extend Carry)

    2.2.3 ADDX (add with extend carry) Operation Rd+(EAs)+C → Rd Assembly-Language Format ADDX <EAs>, Rd Operand Size Byte Condition Code ∆ ∆ ∆ ∆ ∆ — — — Previous value remains unchanged. Set to 1 if there is a carry from bit 3; otherwise cleared to 0. Set to 1 when the result is negative;...

  • Page 46: And (And Logical)

    2.2.4 AND (AND logical) Operation Rd ∧ (EAs) → Rd Assembly-Language Format AND <EAs>, Rd Operand Size Byte Condition Code ∆ ∆ — — — — — Previous value remains unchanged. Previous value remains unchanged. Set to 1 when the result is negative; otherwise cleared to 0. Set to 1 when the result is zero;...

  • Page 47: Andc (And Control Register)

    2.2.5 ANDC (AND control register) Operation CCR ∧ #IMM → CCR Assembly-Language Format ANDC #xx:8, CCR Operand Size Byte Condition Code ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ANDed with bit 7 of the immediate data. ANDed with bit 5 of the immediate data. ANDed with bit 3 of the immediate data.

  • Page 48: Band (Bit And)

    2.2.6 BAND (bit AND) Operation C ∧ (<Bit No.> of <EAd>) → C Assembly-Language Format BAND #xx:3, <EAd> Operand Size Byte Condition Code ∆ — — — — — — — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
  • Page 49 #xx:3 Bit No. <EAd>* → Byte data in register or memory The value of the specified bit is not changed. Instruction Formats and Number of Execution States Instruction code Addressing No of mode Mnem. Operands 1st byte 2nd byte 3rd byte 4th byte states Register direct BAND...

  • Page 50: Bcc (Branch Conditionally)

    2.2.7 Bcc (branch conditionally) Operation If cc then PC+d:8 → PC else next; Assembly-Language Format Bcc →d:8 Condition code field (For mnemonics, see the table on the next page.) Operand Size − Condition Code — — — — — — —...
  • Page 51 Mnemonic cc Field Description Condition Meaning BRA (BT) 0 0 0 0 Always (True) Always true BRN (BF) 0 0 0 1 Never (False) Never X > Y (Unsigned) 0 0 1 0 High C v Z = 0 C ∨ Z = 1 X ≤...
  • Page 52 Instruction Formats and Number of Execution States Instruction code Addressing mode Mnem. Operands 1st byte 2nd byte 3rd byte 4th byte No of states PC relative BRA (BT) disp. PC relative BRN (BF) disp. PC relative disp. PC relative disp. PC relative BCC (BHS) disp.

  • Page 53: Bclr (Bit Clear)

    2.2.8 BCLR (bit clear) Operation 0 → (<Bit No.> of <EAd>) Assembly-Language Format BCLR #xx:3, <EAd> BCLR Rn, <EAd> Operand Size Byte Condition Code — — — — — — — — I: Previous value remains unchanged. H: Previous value remains unchanged. N: Previous value remains unchanged.
  • Page 54 #xx:3 or Rn Bit No. <EAd>* → Byte data in register or memory Register direct, register indirect, or absolute addressing. Instruction Formats and Number of Execution States Instruction code Addressing No of mode Mnem. Operands 1st byte 2nd byte 3rd byte 4th byte states Register direct BCLR...

  • Page 55: Biand (Bit Invert And)

    2.2.9 BIAND (bit invert AND) Operation C ∧ [ ¬ (<Bit No.> of <EAd>)] → C Assembly-Language Format BIAND #xx:3, <EAd> Operand Size Byte Condition Code ∆ — — — — — — — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
  • Page 56 #xx:3 Bit No. Invert <EAd>* → Byte data in register or memory The value of the specified bit is not changed. Instruction Formats and Number of Execution States Instruction code Addressing No of mode Mnem. Operands 1st byte 2nd byte 3rd byte 4th byte states Register...

  • Page 57: Bild (Bit Invert Load)

    2.2.10 BILD (bit invert load) Operation ¬ (<Bit No.> of <EAd>) → C Assembly-Language Format BILD #xx:3, <EAd> Operand Size Byte Condition Code ∆ — — — — — — — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
  • Page 58 #xx:3 Bit No. invert <EAd>* → Byte data in register or memory The value of the specified bit is not changed. Instruction Formats and Number of Execution States Instruction code Addressing No of mode Mnem. Operands 1st byte 2nd byte 3rd byte 4th byte states Register direct...

  • Page 59: Bior (Bit Invert Inclusive Or)

    2.2.11 BIOR (bit invert inclusive OR) Operation C ∨ [¬ (<Bit No.> of <EAd>) → C Assembly-Language Format BIOR #xx:3, <EAd> Operand Size Byte Condition Code ∆ — — — — — — — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
  • Page 60 #xx:3 Bit No. Invert <EAd>* → Byte data in register or memory The value of the specified bit is not changed. Instruction Formats and Number of Execution States Instruction code Addressing No of mode Mnem. Operands 1st byte 2nd byte 3rd byte 4th byte states...

  • Page 61: Bist (Bit Invert Store)

    2.2.12 BIST (bit invert store) Operation ¬ C → (<Bit No.> of <EAd>) Assembly-Language Format BIST #xx:3, <EAd> Operand Size Byte Condition Code — — — — — — — — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
  • Page 62 #xx:3 Bit No. Invert <EAd>* → Byte data in register or memory The values of the unspecified bits are not changed. Instruction Formats and Number of Execution States Instruction code Addressing No of mode Mnem. Operands 1st byte 2nd byte 3rd byte 4th byte states Register direct...

  • Page 63: Bixor (Bit Invert Exclusive Or)

    2.2.13 BIXOR (bit invert exclusive OR) Operation C ⊕ [← (<Bit No.> of <EAd>)] → C Assembly-Language Format BIXOR #xx:3, <EAd> Operand Size Byte Condition Code ∆ — — — — — — — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged Previous value remains unchanged.
  • Page 64 #xx:3 Bit No. Invert <EAd>* → Byte data in register or momory The value of the specified bit is not changed. Instruction Formats and Number of Execution States Instruction code Addressing No of mode Mnem. Operands 1st byte 2nd byte 3rd byte 4th byte states...

  • Page 65: Bld (Bit Load)

    2.2.14 BLD (bit load) Operation (<Bit No.> of <EAd>) → C Assembly-Language Format BLD #xx:3, <EAd> Operand Size Byte Condition Code ∆ — — — — — — — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
  • Page 66 #xx:3 Bit No. <Ead>*→ Byte data in register or memory The value of the specified bit is not changed Instruction Formats and Number of Execution States Instruction code Addressing No of mode Mnem. Operands 1st byte 2nd byte 3rd byte 4th byte states Register #xx:3, Rd...

  • Page 67: Bnot (Bit Not)

    2.2.15 BNOT (bit NOT) Operation ¬ (<Bit No.> of <EAd>) → (<Bit No.> of <EAd>) Assembly-Language Format BNOT #xx:3, <EAd> BNOT Rn, <EAd> Operand Size Byte Condition Code — — — — — — — — Previous value remains unchanged. Previous value remains unchanged.
  • Page 68 #xx:3 or Rn Bit No. Invert <EAd>*→ Byte data in register or memory The bit is not tested before being inverted. The condition code flags are not altered. Register direct, register indirect, or absolute addressing. Instruction Formats and Number of Execution States Instruction code Addressing No of...

  • Page 69: Bor (Bit Inclusive Or)

    2.2.16 BOR (bit inclusive OR) Operation C ∨ (<Bit No.>of <EAd>) → C Assembly-Language Format BOR #xx:3, <EAd> Operand Size Byte Condition Code ∆ — — — — — — — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
  • Page 70 #xx:3 Bit No. <EAd>* → Byte data in register or memory The value of the specified bit is not changed. Instruction Formats and Number of Execution States Instruction code Addressing No of mode Mnem. Operands 1st byte 2nd byte 3rd byte 4th byte states Register direct...

  • Page 71: Bset (Bit Set)

    2.2.17 BSET (bit set) Operation 1 → (<Bit No.> of <EAd>) Assembly-Language Format BEST #xx:3,<EAd> BEST Rn,<EAd> Operand Size Byte Condition Code — — — — — — — — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
  • Page 72 #xx:3 or Rn Bit No. <EAd>* → Byte data i register or momory Register direct, register indirect, or absolute addressing. Instruction Formats and Number of Execution States Instruction code Addressing No. of mode Mnem. Operands 1st byte 2nd byte 3rd byte 4th byte states Register direct BSET...

  • Page 73: Bsr (Branch To Subroutine)

    2.2.18 BSR (branch to subroutine) Operation PC → @−SP PC + d:8 → PC Assembly-Language Format BSR d:8 Operand Size − Condition Code — — — — — — — — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.

  • Page 74: Bst (Bit Store)

    2.2.19 BST (bit store) Operation C → (<Bit No.> of <EAd>) Assembly-Language Format BST #xx:3, <EAd> Operand Size: Byte Condition Code — — — — — — — — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
  • Page 75 #xx:3 Bit No. <EAd>* → Byte data in register or memory Instruction Formats and Number of Execution States Instruction code Addressing No. of mode Mnem. Operands 1st byte 2nd byte 3rd byte 4th byte states Register direct #xx:3, Rd Register indirect #xx:3, Absolute address BST #xx:3,...

  • Page 76: Btst (Bit Test)

    2.2.20 BTST (bit test) Operation ¬ (<Bit No.> of <EAd>) → Z Assembly-Language Format BTST #xx:3, <EAd> BTST Rn, <EAd> Operand Size Byte Condition Code ∆ — — — — — — — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
  • Page 77 #xx:3 or Rn Bit No. Test <EAD>* → Byte data in register or memory The value of the specified bit is not altered. Register direct, register indirect, or absolute addressing. Instruction Formats and Number of Execution States Instruction code Addressing No.

  • Page 78: Bxor (Bit Exclusive Or)

    2.2.21 BXOR (bit exclusive OR) Operation C ⊕ (<Bit No.> of <EAd>) → C Assembly-Language Format BXOR #xx:3, <EAd> Operand Size Byte Condition Code ∆ — — — — — — — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.
  • Page 79 #xx:3 Bit No. <EAd>* → Byte data in register or memory The value of the specified bit is not changed. Instruction Formats and Number of Execution States Instruction code Addressing No. of mode Mnem. Operands 1st byte 2nd byte 3rd byte 4th byte states Register BXOR...

  • Page 80: 2.2.22 (1) Cmp (Compare) (Byte) Cmp

    2.2.22 (1) CMP (compare) (byte) CMP Operation Rd − (EAs); set condition code Assembly-Language Format CMP.B <EAs>, Rd Operand Size Byte Condition Code ∆ ∆ ∆ ∆ ∆ — — — Previous value remains unchanged. Set to 1 when there is a borrow from bit 3; otherwise cleared to 0. Set to 1 when the result is negative;...

  • Page 81: 2) Cmp (Compare) (Word)

    2.2.22 (2) CMP (compare) (word) Operation Rd − Rs; set condition code Assembly-Language Format CMP.W Rs, Rd Operand Size Word Condition Code ∆ ∆ ∆ ∆ ∆ — — — Previous value remains unchanged. Set to 1 when there is a borrow from bit 11; otherwise cleared to 0. Set to 1 when the result is negative;...

  • Page 82: Daa (Decimal Adjust Add)

    2.2.23 DAA (decimal adjust add) Operation Rd (decimal adjust) → Rd Assembly-Language Format DAA Rd Operand Size Byte Condition Code ∆ ∆ ∆ — — — Previous value remains unchanged. Unpredictable Set to 1 when the adjusted result is negative; otherwise cleared to 0. Set to 1 when the adjusted result is zero;...
  • Page 83 Status before adjustment C flag Upper nibble H flag Lower nibble Value added Resulting C flag 0 - 9 0 - 9 H'00...

  • Page 84: Das (Decimal Adjust Subtract)

    2.2.24 DAS (decimal adjust subtract) Operation Rd (decimal adjust) → Rd Assembly-Language Format DAS Rd Operand Size Byte Condition Code ∆ ∆ — — — — Previous value remains unchanged. Unpredictable. Set to 1 when the adjusted result is negative; otherwise cleared to 0. Set to 1 when the adjusted result is zero;...

  • Page 85: Dec (Decrement)

    2.2.25 DEC (decrement) Operation Rd - 1 → Rd Assembly-Language Format DEC Rd Operand Size Byte Condition Code ∆ ∆ ∆ — — — — — Previous value remains unchanged. Previous value remains unchanged. Set to 1 when the result is negative; otherwise cleared to 0. Set to I when the result is zero;...

  • Page 86: Divxu (Divide Extend As Unsigned)

    2.2.26 DIVXU (divide extend as unsigned) Operation Rd ÷ Rs → Rd Assembly-Language Format DIVXU Rs, Rd Operand Size Byte Condition Code ∆ ∆ — — — — — — Previous value remains unchanged. Previous value remains unchanged. Set to I when the divisor is negative; otherwise cleared to 0. Cleared to 0 when divisor ≠...
  • Page 87 Instruction Formats and Number of Execution States Instruction code Addressing No. of mode Mnem. Operands 1st byte 2nd byte 3rd byte 4th byte states Register direct DIVXU Rs, Rd Note: DIVXU Overflow Since the DIVXU instruction performs 16-bit ÷ 8-bit → 8-bit division, an overflow will occur if the divisor byte is equal to or less than the upper byte of the dividend.
  • Page 88 Divisor Dividend Remainder Quotient (*1) Dividend H'00 Dividend (High) (*2) Partial remainder Dividend (Low) Partial remainder Quotient (High) (*3) Remainder Quotient (Low) (*4) Quotient...

  • Page 89: Eepmov (Move Date To Eeprom)

    2.227 EEPMOV (move date to EEPROM) Operation if R4L ≠ 0 then repeat @R5+ → @R6+ R4L − 1 → R4L until R4L = O else next; Assembly-Language Format EEPMOV Operand Size  Condition Code — — — — — —...
  • Page 90 Instruction Formats and Number of Execution States Instruction code Addressing No. of mode Mnem. Operands 1st byte 2nd byte 3rd byte 4th byte states  EEPMOV 9+4n* n is the initial value in R4L (0 ≤ n ≤ 255). Although n bytes of data are transferred, memory is accessed 2(n+1) times, requiring 4(n+1) states.

  • Page 91: Inc

    2.2.28 INC (increment Operation Rd + 1 → Rd Assembly-Language Format INC Rd Operand Size Byte Condition Code ∆ ∆ ∆ — — — — — Previous value remains unchanged. Previous value remains unchanged. Set to 1 when the result is negative; otherwise cleared to 0. Set to 1 when the result is zero;...

  • Page 92: Jmp (Jump)

    2.2.29 JMP (jump) Operation (EAd) → PC Assembly-Language Format JMP <EA> Operand Size  Condition Code — — — — — — — — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.

  • Page 93: Jsr (Jump To Subroutine)

    2.2.30 JSR (Jump to subroutine) Operation PC → @−SP (EAd) → PC Assembly-Language Format JSR <EA> Operand Size  Condition Code — — — — — — — — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.

  • Page 94: Ldc (Load To Control Register)

    2.2.31 LDC (load to control register) Operation (EAs) → CCR Assembly-Language Format LDC <EAs>, CCR Operand Size Byte Condition Code ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ Loaded from the source operand. Loaded from the source operand. Loaded from the source operand. Loaded from the source operand.

  • Page 95: 1) Mov (Move Data) (Byte)

    2.2.32 (1) MOV (move data) (byte) Operation Rs → Rd Assembly-Language Format MOV.B Rs, Rd Operand Size Byte Condition Code ∆ ∆ — — — — —...

  • Page 96: 2) Mov (Move Data) (Word)

    2.2.32(2) MOV (move data) (word) Operation Rs → Rd Assembly-Language Format MOV.W Rs, Rd Operand Size Word Condition Code ∆ ∆ — — — — — Previous value remains unchanged. Previous value remains unchanged. Set to 1 when the data value is negative; otherwise cleared to 0. Set to 1 when the data value is zero;...

  • Page 97: 3) Mov (Move Data) (Byte)

    2.2.32(3) MOV (move data) (byte) Operation (EAs) → Rd Assembly-Language Format MOV.B <EAs>, Rd Operand Size Byte Condition Code ∆ ∆ — — — — — Previous value remains unchanged. Previous value remains unchanged. Set to 1 when the data value is negative; otherwise cleared to 0. Set to 1 when the data value is zero;...
  • Page 98 Instruction Formats and Number of Execution States Instruction code Addressing No. of mode Mnem. Operands 1st byte 2nd byte 3rd byte 4th byte states Immediate MOV.B #xx:8, Rd Register indirect MOV.B @RS, Rd Register indirect MOV.B @(d:16, Rs), disp. with displacement Register indirect MOV.B @Rs+, Rd...

  • Page 99: 4) Mov (Move Data) (Word)

    MOV.W @R7+, Rd is identical in machine language to POP.W Rd. Note that the LSIs in the H8/300L Series contain on-chip peripheral modules for which access in word size is not possible. Details are given in the applicable hardware manual.
  • Page 100 Instruction Formats and Number of Execution States Instruction code Addressing No. of mode Mnem. Operands 1st byte 2nd byte 3rd byte 4th byte states Immediate MOV.W #xx:16, Rd Register indirect MOV.W @RS, Rd Register indirect MOV.W @(d:16,Rs),Rd 6 disp. with displacement Register indirect MOV.W @Rs+, Rd...

  • Page 101: 5) Mov (Move) Data) (Byte)

    2.2.32(5) MOV (move) data) (byte) Operation Rs → (EAd) Assembly-Language Format MOV .B Rs, <EAd> Operand Size Byte Condition Code ∆ ∆ — — — — — Previous value remains unchanged. Previous value remains unchanged. Set to 1 when the data value is negative; otherwise cleared to 0. Set to I when the data value is zero;...

  • Page 102: 6) Mov (Move Data) (Word)

    The instruction MOV.W Rn, @-Rn decrements register Rn by 2, then moves the decremented result to memory. Note that the LSIs in the H8/300L Series contain on-chip peripheral modules for which access in word size is not possible. Details are given in the applicable hardware manual.
  • Page 103 Instruction Formats and Number of Execution States Instruction code Addressing No. of mode Mnem. Operands 1st byte 2nd byte 3rd byte 4th byte states Register indirect MOV.W Rs, @Rd Register indirect MOV.W Rs,@(d:16, disp. with displacement Register indirect MOV.W Rs,@-Rd with pre- decrement Absolute address MOV.W...

  • Page 104: Mulxu (Multiply Extend As Unsigned)

    2.2.33 MULXU (multiply extend as unsigned) Operation Rd × Rs → Rd Assembly-Language Format MULXU Rs, Rd Operand Size Byte Condition Code — — — — — — — — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.

  • Page 105: Neg (Negate)

    2.2.34 NEG (negate) Operation 0 - Rd → Rd Assembly-Language Format NEG Rd Operand Size Byte Condition Code ∆ ∆ ∆ ∆ ∆ — — — Previous value remains unchanged. Set to 1 when there is a borrow from bit 3; otherwise cleared to 0. Set to 1 when the result is negative;...

  • Page 106: Nop (No Operation)

    2.2.35 NOP (no operation) Operation PC + 2 → PC Assembly-Language Format Operand Size  Condition Code — — — — — — — — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.

  • Page 107: Not (Not = Logical Complement)

    2.2.36 NOT (NOT = logical complement) Operation ¬ Rd → Rd Assembly-Language Format NOT Rd Operand Size Byte Condition Code ∆ ∆ — — — — — Previous value remains unchanged. Previous value remains unchanged. Set to 1 when the result is negative; otherwise cleared to 0. Set to 1 when the result is zero;...

  • Page 108: Or (Inclusive Or Logical)

    2.2.37 OR (inclusive OR logical) Operation Rd ∨ (EAs) → Rd Assembly-Language Format OR <EAs>, Rd Operand Size Byte Condition Code ∆ ∆ — — — — — Previous value remains unchanged. Previous value remains unchanged. Set to 1 when the result is negative; otherwise cleared to 0. Set to 1 when the result is zero;...

  • Page 109: Orc (Inclusive Or Control Register)

    2.2.38 ORC (inclusive OR control register) Operation CCR ∨ #IMM → CCR Assembly-Language Format ORC #xx:8, CCR Operand Size Byte Condition Code ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ORed with bit 7 of the immediate data. ORed with bit 5 of the immediate data. ORed with bit 3 of the immediate data.

  • Page 110: Pop (Pop Data)

    2.2.39 POP (pop data) Operation @SP+ → Rn Assembly-Language Format POP Rn Operand Size Word Condition Code ∆ ∆ — — — — — Previous value remains unchanged. Previous value remains unchanged. Set to 1 when the data value is negative; otherwise cleared to 0. Set to 1 when the data value is zero;...

  • Page 111: Push (Push Data)

    2.2.40 PUSH (push data) Operation Rn → @-SP Assembly-Language Format PUSH Rn Operand Size Word Condition Code ∆ ∆ — — — — — Previous value remains unchanged. Previous value remains unchanged. Set to 1 when the data value is negative; otherwise cleared to 0. Set to 1 when the data value is zero;...

  • Page 112: Rotl (Rotate Left)

    2.2.41 ROTL (rotate left) Operation Rd (rotated left) → Rd Assembly-Language Format ROTL Rd Operand Size Byte Condition Code ∆ ∆ — — — — — Previous value remains unchanged. Previous value remains unchanged. Set to 1 when the result is negative; otherwise cleared to 0. Set to 1 when the result is zero;...

  • Page 113: Rotr (Rotate Right)

    2.2.42 ROTR (rotate right) Operation Rd (rotated right) → Rd Assembly-Language Format ROTR Rd Operand Size Byte Condition Code ∆ ∆ — — — — — Previous value remains unchanged. Previous value remains unchanged. Set to I when the result is negative; otherwise cleared to 0. Set to 1 when the result is zero;...

  • Page 114: Rotxl (Rotate With Extend Carry Left)

    2.2.43 ROTXL (rotate with extend carry left) Operation Rd (rotated with carry left) → Rd Assembly-Language Format ROTXL Rd Operand Size Byte Condition Code ∆ ∆ — — — — — Previous value remains unchanged. Previous value remains unchanged. Set to 1 when the result is negative; otherwise cleared to 0. Set to 1 when the result is zero;...

  • Page 115: Rotxr (Rotate With Extend Carry Right)

    2.2.44 ROTXR (rotate with extend carry right) Operation Rd (rotated with carry right) → Rd Assembly-Language Format ROTXR Rd Operand Size Byte Condition Code ∆ ∆ — — — — — Previous value remains unchanged. Previous value remains unchanged. Set to 1 when the result is negative; otherwise cleared to 0. Set to 1 when the result is zero;...

  • Page 116: Rte (Return From Exception)

    2.2.45 RTE (return from exception) Operation @SP + → CCR @SP + → PC Assembly-Language Format Operand Size  Condition Code ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆...

  • Page 117: Rts (Return From Subroutine)

    2.2.46 RTS (return from subroutine) Operation @SP + → PC Assembly-Language Format Operand Size  Condition Code — — — — — — — — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.

  • Page 118: Shal (Shift Arithmetic Left)

    2.2.47 SHAL (shift arithmetic left) Operation Rd (shifted arithmetic left ) → Rd Assembly-Language Format SHAL Rd Operand Size Byte Condition Code ∆ ∆ ∆ ∆ — — — — Previous value remains unchanged. Previous value remains unchanged. Set to 1 when the result is negative; otherwise cleared to 0. Set to 1 when the result is zero;...

  • Page 119: Shar (Shift Arithmetic Right)

    2.2.48 SHAR (shift arithmetic right) Operation Rd (shifted arithmetic right) → Rd Assembly-Language Format SHAR Rd Operand Size Byte Condition Code ∆ ∆ — — — — — Previous value remains unchanged. Previous value remains unchanged. Set to 1 when the result is negative; otherwise cleared to 0. Set to 1 when the result is zero;...
  • Page 120 Instruction Formats and Number of Execution States Instruction code Addressing No. of mode Mnem. Operands 1st byte 2nd byte 3rd byte 4th byte states Register direct SHAR...

  • Page 121: Shll (Shift Logical Left)

    2.2.49 SHLL (shift logical left) Operation Rd (shifted logical left ) → Rd Assembly-Language Format SHLL Rd Operand Size Byte Condition Code ∆ ∆ — — — — — Previous value remains unchanged. Previous value remains unchanged. Set to 1 when the result is negative; otherwise cleared to 0. Set to 1 when the result is zero;...
  • Page 122 Instruction Formats and Number of Execution States Instruction code Addressing No. of mode Mnem. Operands 1st byte 2nd byte 3rd byte 4th byte states Register SHLL direct...

  • Page 123: Shlr (Shift Logical Right)

    2.2.50 SHLR (shift logical right) Operation Rd (shifted logical right) → Rd Assembly-Language Format SHLR Rd Operand Size Byte Condition Code ∆ ∆ — — — — — Previous value remains unchanged. Previous value remains unchanged. Set to 1 when the result is negative; otherwise cleared to 0. Set to 1 when the result is zero;...
  • Page 124 Instruction Formats and Number of Execution States Instruction code Addressing No. of mode Mnem. Operands 1st byte 2nd byte 3rd byte 4th byte states Register SHLR direct...

  • Page 125: Sleep (Sleep)

    2.2.51 SLEEP (sleep) Operation Program execution state → power-down mode Assembly-Language Format SLEEP Operand Size  Condition Code — — — — — — — — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.

  • Page 126: Stc (Store From Control Register)

    2.2.52 STC (store from control register) Operation CCR → Rd Assembly-Language Format STC CCR, Rd Operand Size Byte Condition Code — — — — — — — — Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged. Previous value remains unchanged.

  • Page 127: 1) Sub (Subtract Binary) (Byte)

    2.2.53(1) SUB (subtract binary) (byte) Operation Rd - Rs → Rd Assembly-Language Format SUB.B Rs, Rd Operand Size Byte Condition Code ∆ ∆ ∆ ∆ ∆ — — — Previous value remains unchanged. Set to 1 when there is a borrow from bit 3; otherwise cleared to 0. Set to 1 when the result is negative;...
  • Page 128 Instruction Formats and Number of Execution States Instruction code Addressing No. of mode Mnem. Operands 1st byte 2nd byte 3rd byte 4th byte states Register direct SUB.B Rs, Rd...

  • Page 129: 2) Sub (Subtract Binary) (Word)

    2.2.53(2) SUB (subtract binary) (word) Operation Rd - Rs → Rd Assembly - Language Format SUB.W Rs, Rd Operand Size Word Condition Code ∆ ∆ ∆ ∆ ∆ — — — Previous value remains unchanged. Set to 1 when there is a borrow from bit 11; otherwise cleared to 0. Set to 1 when the result is negative;...

  • Page 130: Subs (Subtract With Sign Extension)

    2.2.54 SUBS (subtract with sign extension) Operation Rd - 1 → Rd Rd - 2 → Rd Assembly-Language Format SUBS #1, Rd SUBS #2, Rd Operand Size Word Condition Code — — — — — — — — Previous value remains unchanged. Previous value remains unchanged.

  • Page 131: Subx (Subtract With Extend Carry)

    2.2.55 SUBX (subtract with extend carry) Operation Rd - (EAs) - C → Rd Assembly-Language Format SUBX <EAs>, Rd Operand Size Byte Condition Code ∆ ∆ ∆ ∆ ∆ — — — Previous value remains unchanged. Set to 1 if there is a borrow from bit 3; otherwise cleared to 0. Set to 1 when the result is negative;...

  • Page 132: Xor (Exclusive Or Logical)

    2.2.56 XOR (exclusive OR logical) Operation Rd ⊕ (Eas) → Rd Assembly-Language Format XOR <Eas>, Rd Operand Size Byte Condition Code ∆ ∆ — — — — — Previous value remains unchanged. Previous value remains unchanged, Set to 1 when the result is negative; otherwise cleared to 0. Set to 1 when the result is zero;...

  • Page 133: Xorc (Exclusive Or Control Register)

    2.2.57 XORC (exclusive OR control register) Operation CCR ⊕ #IMM → CCR Assembly-Language Format XORC #xx:8, CCR Operand Size Byte Condition Code ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ Exclusive-ORed with bit 7 of the immediate data. Exclusive-ORed with bit 5 of the immediate data. Exclusive-ORed with bit 3 of the immediate data.

  • Page 134: 2.3 Operation Code Map

    2.3 Operation Code Map Table 2-1 shows the operation code map for instructions of the H8/300L CPU. Only the first byte (bits 15 to 8 of the first word) of the instruction code is indicated here. Indicates that the most significant bit of the 2nd byte (bit 7 of 1st word of instruction code) is 0.
  • Page 135 Table 2-1. Operation Code Map...

  • Page 136: 2.4 List Of Instructions

    2.4 List of Instructions Table 2-2. List of Instructions (1) Addressing Mode and Instruction Length (Bytes) Mnemonic Operation Condition Code ∆ ∆ MOV.B #xx:8,Rd #xx:8→Rd8 ∆ ∆ MOV.B Rs,Rd Rs8→Rd8 ∆ ∆ MOV.B @Rs,Rd @Rs16→Rd8 ∆ ∆ MOV.B @(d:16,Rs),Rd @(d:16,Rs16)→Rd8 ∆...
  • Page 137 Table 2-2. List of Instructions (2) Addressing Mode and Instruction Length (Bytes) Mnemonic Operation Condition Code ∆ ∆ ∆ ∆ ∆ ADD.B #xx:8,Rd Rd8+#xx:8→Rd8 ∆ ∆ ∆ ∆ ∆ ADD.B Rs,Rd Rd8+Rs8→Rd8 ∆ ∆ ∆ ∆ ADD.W Rs,Rd Rd16+Rs16→Rd16 ∆ ∆...
  • Page 138 Table 2-2. List of Instructions (3) Addressing Mode and Instruction Length (Bytes) Mnemonic Operation Condition Code ∆ ∆ ∆ ∆ SHAL.B Rd ∆ ∆ ∆ SHAR.B Rd ∆ ∆ ∆ SHLL.B Rd ∆ ∆ SHLR.B Rd ∆ ∆ ∆ ROTXL.B Rd ∆...
  • Page 139 Table 2-2. List of Instructions (4) Addressing Mode and Instruction Length (Bytes) Mnemonic Operation Condition Code BCLR #xx:3,Rd (#xx:3 of Rd8)←0 BCLR #xx:3,@Rd (#xx:3 of @Rd16)←0 BCLR #xx:3,@aa:8 (#xx:3 of @aa:8)←0 BCLR Rn,Rd @Rd (Rn8 of @Rd8)←0 BCLR Rn,@Rd (Rn8 of @Rd 16)←0 BCLR Rn,@aa:8 (Rn8 of @aa:8)←0...
  • Page 140 Table 2-2. List of Instructions (5) Addressing Mode and Instruction Length (Bytes) Mnemonic Operation Condition Code V0 C → (#xx:3 of Rd8) BIST #xx:3,Rd & → (#xx:3 of @Rd16) BIST #xx:3,@Rd & → (#xx:3 of @aa:8) BIST #xx:3,@aa8 & C^ (#xx:3 of Rd8) → C ∆...
  • Page 141 Table 2-2. List of Instructions (6) Addressing Mode and Instruction Length (Bytes) Mnemonic Operation Condition Code Branching Condition BPL d:8 if condition is true then ← PC+d :8 else next; BMI d:8 ⊕ BGE d:8 ⊕ BLT d:8 ⊕ BGT d:8 Zv(N V)=0 ⊕...
  • Page 142 Addressing Mode and Instruction Length (Bytes) Mnemonic Operation Condition Code Branching Z V0 C Condition BHI d:8 CvZ=0 condition is true then PC ← PC+d:8 else next; BLS d:8 CvZ=1 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8...
  • Page 143 Table 2-2. List of Instructions (7) Addressing Mode and Instruction Length (Bytes) Mnemonic Operation Condition Code CCR⊕#xx:8 → CCR 2 ∆ ∆ ∆ ∆ ∆ ∆ XORC #xx:8,CCR PC ← PC+2 EEPMOV if R4L≠0 Repeat @R5 → @ R6 R5+1 →...

  • Page 144: Number Of Execution States

    Number of Execution States The tables here can be used to calculate the number of states required for instruction execution. Table 2-3 indicated the number of states required for each cycle (instruction fetch, branch address read, stack operation, byte data access, word data access, internal operation). Table 2-4 indicates the number of cycles of each type occurring in each instruction..
  • Page 145 Table 2-4. Number of Cycles in Each Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDS ADDS.W #1/2, Rd ADDX ADDX.B #xx:8, Rd ADDX.B Rs, Rd AND.B #xx:8, Rd AND.B Rs, Rd...
  • Page 146 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BCLR Rn, Rd BCLR BCLR Rn, @Rd BCLR Rn, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 BILD BILD #xx3, Rd BILD #xx:3, @Rd BILD #xx3, @aa:8 BIOR...
  • Page 147 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BSET Rn, Rd BSET Rn, @Rd BSET BSET Rn, @aa:8 BSR d:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BTST BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd...
  • Page 148 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @Rs, Rd MOV.B @(d:16, Rs), Rd MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, Rd) MOV.B Rs, @-Rd MOV.B Rs, @aa:8...
  • Page 149 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ROTXL ROTXL.B Rd ROTXR ROTXR.B Rd SHLL SHLL.B Rd SHAL SHAL.B Rd SHAR SHAR.B Rd SHLR SHLR.B Rd SLEEP SLEEP STC CCR, Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBS...

  • Page 151: Section 3. Cpu Operation States

    Section 3. CPU Operation States There are three CPU operation states, namely, program execution state, power-down state, and exception-handling state. In power-down state there are sleep mode, standby mode, and watch mode. These operation states are shown in figure 3-1. Figure 3-2 shows the state transitions. For further details please refer to the applicable hardware manual.

  • Page 152: Program Execution State

    Program Execution State In program execution state the CPU executes program instructions in sequence. Exception Handling States Exception-handling states are transient states occurring when exception handling is raised by a reset or interrupt, and the CPU changes its normal processing flow, branching to a start address acquired from a vector table.
  • Page 153 Table 3-1. Types of Exception Handling and Priorities Timing for start of exception Priority Exception source Detection timing handling High Reset Clock-synchronous Reset exception handling starts as soon as pin changes from low to #$ high. Interrupt End of instruction When an interrupt request is made, execution* interrupt exception handling starts after...

  • Page 154: Exception Sources And Vector Table

    3.2.2 Exception Sources and Vector Table The factors causing exception handling can be classified as in figure 3-3. For details of exception handling, the vector numbers of each source, and the vector addresses, see the applicable hardware manual. Reset Exception source External interrupt Interrupt Internal interrupt...

  • Page 155: Reset State

    SP – 4 SP (R7) SP – 3 SP + 1 CCR* SP – 2 SP + 2 SP – 1 SP + 3 Even-numbered SP (R7) SP + 4 address Stack Prior to start of interrupt After completion of interrupt Contents exception handling exception handling...

  • Page 157: Section 4. Basic Operation Timing

    Section 4. Basic Operation Timing CPU operation is synchronized by a clock (φ). The period from the rising edge of φ to the next rising edge is called one state. A memory cycle or bus cycle consists of two or three states. For details on access to on-chip memory and to on-chip peripheral modules see the applicable hardware manual.

  • Page 158: On-Chip Peripheral Modules And External Devices

    On-chip Peripheral Modules and External Devices On-chip peripheral modules are accessed in two or three states. The data bus width is 8 bits, so access is made in byte size only. Access to word data or instruction codes is not possible. Figure 4-2 shows the on-chip peripheral module access cycle.

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