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Hitachi H8/329 Series Hardware Manual

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OMC942723054
HITACHI SINGLE-CHIP MICROCOMPUTER
HD6473298, HD6433298, HD6413298
HD6473278, HD6433278, HD6413278
H8/329 SERIES
H8/329
H8/328
HD6433288
H8/327
H8/326
HD6433268
HARDWARE MANUAL

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Summary of Contents for Hitachi H8/329 Series

  • Page 1 OMC942723054 HITACHI SINGLE-CHIP MICROCOMPUTER H8/329 SERIES H8/329 HD6473298, HD6433298, HD6413298 H8/328 HD6433288 H8/327 HD6473278, HD6433278, HD6413278 H8/326 HD6433268 HARDWARE MANUAL...
  • Page 2 This manual describes the hardware of the H8/329 Series. Refer to the H8/300 Series Programming Manual for a detailed description of the instruction set. Notes: * ZTAT is a registered trademark of Hitachi, Ltd.

  • Page 3: Table Of Contents

    Contents Section 1. Overview ....................... Overview..........................Block Diagram........................Pin Assignments and Functions.................... 1.3.1 Pin Arrangement...................... 1.3.2 Pin Functions ......................Section 2. MCU Operating Modes and Address Space ..........15 Overview..........................15 2.1.1 Mode Selection ......................15 2.1.2 Mode and System Control Registers (MDCR and SYSCR) ........16 System Control Register (SYSCR)—H'FFC4 ..............
  • Page 4 3.5.8 Block Data Transfer Instruction ................50 CPU States ..........................51 3.6.1 Program Execution State ..................52 3.6.2 Exception-Handling State..................52 3.6.3 Power-Down State ....................53 Access Timing and Bus Cycle ....................53 3.7.1 Access to On-Chip Memory (RAM and ROM) ............53 3.7.2 Access to On-Chip Register Field and External Devices ........
  • Page 5 6.1.2 Block Diagram......................113 6.1.3 Input and Output Pins ....................115 6.1.4 Register Configuration .................... 115 Register Descriptions......................116 6.2.1 Free-Running Counter (FRC)—H'FF92..............116 6.2.2 Output Compare Registers A and B (OCRA and OCRB)—H'FF94....... 117 6.2.3 Input Capture Registers A to D (ICRA to ICRD)— H'FF98, H'FF9A, H'FF9C, H'FF9E .................
  • Page 6 7.3.3 External Reset of TCNT ..................155 7.3.4 Setting of TCSR Overflow Flag (OVF) ..............156 Interrupts..........................157 Sample Application....................... 157 Application Notes ......................... 158 Section 8. Serial Communication Interface ..............163 Overview..........................163 8.1.1 Features........................163 8.1.2 Block Diagram......................164 8.1.3 Input and Output Pins ....................
  • Page 7 9.2.3 A/D Control Register (ADCR)—H'FFEA............... 215 Operation ..........................215 9.3.1 Single Mode (SCAN = 0) ..................216 9.3.2 Scan Mode (SCAN = 1) ..................219 9.3.3 Input Sampling Time and A/D Conversion Time............ 222 9.3.4 External Trigger Input Timing................. 223 Interrupts..........................
  • Page 8 12.4.3 Sample Application of Software Standby Mode ............. 243 12.4.4 Application Note ..................... 244 12.5 Hardware Standby Mode ...................... 245 12.5.1 Transition to Hardware Standby Mode..............245 12.5.2 Recovery from Hardware Standby Mode..............245 12.5.3 Timing Relationships....................246 Section 13. Clock Pulse Generator ..................
  • Page 9 Appendix C. Pin States ......................317 C.1 Pin States in Each Mode ....................... 317 Appendix D. Timing of Transition to and Recovery from Hardware Standby Mode ....................319 Appendix E. Package Dimensions ..................320...

  • Page 10: Section 1. Overview

    (SCI), an A/D converter, and I/O ports. The H8/329 Series can operate in a single-chip mode or in two expanded modes, depending on the requirements of the application. (The operating mode will be referred to as the MCU mode in this manual.)
  • Page 11 Table 1-1. Features Item Specification Two-way general register configuration • Eight 16-bit registers, or • Sixteen 8-bit registers High-speed operation • Maximum clock rate: 10MHz • Add/subtract: 0.2µs • Multiply/divide: 1.4µs Streamlined, concise instruction set • Instruction length: 2 or 4 bytes •...
  • Page 12 Table 1-1. Features (cont.) Item Specification A/D converter • 8-bit resolution • Eight channels: single or scan mode (selectable) • Start of A/D conversion can be externally triggered • Sample-and-hold function I/O ports • 43 input/output lines (16 of which can drive LEDs) •...
  • Page 13 Table 1-1. Features (cont.) Item Specification Series lineup 5-V version 3-V version Package H8/329 HD6473298C HD6473298VC 64-pin windowed shrink DIP PROM (DC-64S) HD6473298P HD6473298VP 64-pin shrink DIP (DP-64S) HD6473298F HD6473298VF 64-pin QFP (FP-64A) HD6473298CP HD6473298VCP 68-pin PLCC (CP-68) HD6433298P HD6433298VP 64-pin shrink DIP (DP-64S) Masked ROM HD6433298F...

  • Page 14: Block Diagram

    1.2 Block Diagram Figure 1-1 shows a block diagram of the H8/329 Series. Clock pulse gener- H8/300 ator Data bus (Low) P4 /IRQ /ADTRG P4 /IRQ P4 /IRQ P4 /RD PROM P4 /WR (or masked ROM) P4 /AS P4 /Ø...

  • Page 15: Pin Assignments And Functions

    1.3 Pin Assignments and Functions 1.3.1 Pin Arrangement Figure 1-2 shows the pin arrangement of the DC-64S and DP-64S packages. Figure 1-3 shows the pin arrangement of the FP-64A package. Figure 1-4 shows the pin arrangement of the CP-68 package. /ADTRG/IRQ /IRQ /IRQ...
  • Page 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 /TxD /RxD /SCK STBY XTAL EXTAL 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 1-3. Pin Arrangement (FP-64A, Top View)
  • Page 17 68 67 66 65 64 63 62 61 /TxD /RxD /SCK STBY XTAL EXTAL 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Figure 1-4. Pin Arrangement (CP-68, Top View)

  • Page 18: Pin Functions

    1.3.2 Pin Functions (1) Pin Assignments in Each Operating Mode: Table 1-2 lists the assignments of the pins of the DC-64S, DP-64S, FP-64A, and CP-68 packages in each operating mode. Table 1-2. Pin Assignments in Each Operating Mode (1) Pin No. DC-64S Expanded modes Single-chip mode...
  • Page 19 Table 1-2. Pin Assignments in Each Operating Mode (2) Pin No. DC-64S Expanded modes Single-chip mode PROM DP-64S FP-64A CP-68 Mode 1 Mode 2 Mode 3 mode /FTCI/TMCI /FTCI/TMCI /FTCI/TMCI /FTOA /FTOA /FTOA — — /FTIA /FTIA /FTIA /FTIB/TMRI /FTIB/TMRI /FTIB/TMRI /FTIC/TMO /FTIC/TMO...
  • Page 20 (2) Pin Functions: Table 1-3 gives a concise description of the function of each pin. Table 1-3. Pin Functions (1) Pin No. DC-64S Type Symbol DP-64S FP-64A CP-68 I/O Name and function Power 14, 39 6, 31 15, 42 Power: Connected to the power supply (+5V).
  • Page 21 Table 1-3. Pin Functions (2) Pin No. DC-64S Type Symbol DP-64S FP-64A CP-68 I/O Name and function Data bus to D 57 to 64 49 to 56 61 to 68 I/O Data bus: 8-Bit bidirectional data bus. WAIT Wait: Requests the CPU to insert T control states into the bus cycle when an external address is accessed.
  • Page 22 Table 1-3. Pin Functions (3) Pin No. DC-64S Type Symbol DP-64S FP-64A CP-68 I/O Name and function Serial com- TxD Transmit Data: Data output pin for the munication serial communication interface. interface Receive Data: Data input pin for the serial communication interface. I/O Serial ClocK: Input/output pin for the serial clock.
  • Page 23 Table 1-3. Pin Functions (4) Pin No. DC-64S Type Symbol DP-64S FP-64A CP-68 I/O Name and function General- to P1 49 to 56 41 to 48 53 to 60 I/O Port 1: An 8-bit input/output port with purpose programmable MOS input pull-ups and LED driving capability.

  • Page 24: Section 2. Mcu Operating Modes And Address Space

    Section 2. MCU Operating Modes and Address Space 2.1 Overview 2.1.1 Mode Selection The H8/329 Series operates in three modes numbered 1, 2, and 3. The mode is selected by the inputs at the mode pins (MD and MD ) when the chip comes out of a reset. See table 2-1.

  • Page 25: Mode And System Control Registers (Mdcr And Syscr)

    2.1.2 Mode and System Control Registers (MDCR and SYSCR) Table 2-2 lists the registers related to the operating mode: the system control register (SYSCR) and mode control register (MDCR). The mode control register indicates the inputs to the mode pins and MD Table 2-2.
  • Page 26 Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling time when the chip recovers from the software standby mode by an external interrupt. During the selected time the CPU and on-chip supporting modules continue to stand by. These bits should be set according to the clock frequency so that the settling time is at least 10ms.

  • Page 27: Mode Control Register (Mdcr)-H'ffc5

    2.3 Mode Control Register (MDCR)—H'FFC5 — — — — — — MDS1 MDS0 Initial value Read/Write — — — — — — Note: * Initialized according to MD and MD inputs. The mode control register (MDCR) is an eight-bit register that indicates the operating mode of the chip.

  • Page 28: Address Space Maps

    2.4 Address Space Maps Figures 2-1 to 2-4 show memory maps of the H8/329, H8/328, H8/327, and H8/326 in modes 1, 2, and 3. Mode 1 Mode 2 Mode 3 Expanded Mode without Expanded Mode with Single-Chip Mode On-Chip ROM On-Chip ROM H'0000 H'0000...
  • Page 29 Mode 1 Mode 2 Mode 3 Expanded Mode without Expanded Mode with Single-Chip Mode On-Chip ROM On-Chip ROM H'0000 H'0000 H'0000 Vector Table Vector Table Vector Table H'0047 H'0047 H'0047 H'0048 H'0048 H'0048 On-Chip ROM, On-Chip ROM, 24k bytes 24k bytes H'5FFF H'5FFF H'6000...
  • Page 30 Mode 1 Mode 2 Mode 3 Expanded Mode without Expanded Mode with Single-Chip Mode On-Chip ROM On-Chip ROM H'0000 H'0000 H'0000 Vector Table Vector Table Vector Table H'0047 H'0047 H'0047 H'0048 H'0048 H'0048 On-Chip ROM, On-Chip ROM, 16k bytes 16k bytes H'3FFF H'3FFF H'4000...
  • Page 31 Mode 1 Mode 2 Mode 3 Expanded Mode without Expanded Mode with Single-Chip Mode On-Chip ROM On-Chip ROM H'0000 H'0000 H'0000 Vector Table Vector Table Vector Table H'0047 H'0047 H'0047 H'0048 H'0048 H'0048 On-Chip ROM, On-Chip ROM, 8k bytes 8k bytes H'1FFF H'1FFF H'2000...

  • Page 32: Section 3. Cpu

    Section 3. CPU 3.1 Overview The H8/329 Series has the H8/300 CPU: a fast central processing unit with eight 16-bit general registers (also configurable as 16 eight-bit registers) and a concise instruction set designed for high- speed operation. 3.1.1 Features The main features of the H8/300 CPU are listed below.

  • Page 33: Register Configuration

    3.2 Register Configuration Figure 3-1 shows the register structure of the CPU. There are two groups of registers: the general registers and control registers. (SP) SP: Stack Pointer PC: Program Counter CCR: Condition Code Register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask bit...

  • Page 34: Control Registers

    Unused area (R7) Stack area Figure 3-2. Stack Pointer 3.2.2 Control Registers The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code register (CCR). (1) Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU will execute.

  • Page 35: Initial Register Values

    Bit 3—Negative Flag (N): This flag indicates the most significant bit (sign bit) of the result of an instruction. Bit 2—Zero Flag (Z): This flag is set to “1” to indicate a zero result and cleared to “0” to indicate a nonzero result.

  • Page 36: Addressing Modes

    3.3 Addressing Modes 3.3.1 Addressing Mode The H8/300 CPU supports eight addressing modes. Each instruction uses a subset of these addressing modes. Table 3-1. Addressing Modes Addressing mode Symbol Register direct Register indirect Register indirect with displacement @(d:16, Rn) Register indirect with post-increment @Rn+ Register indirect with pre-decrement @–Rn...
  • Page 37 1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even. • Register Indirect with Pre-Decrement—@–Rn The @–Rn mode is used with MOV instructions that store register contents to memory. It is similar to the register indirect mode, but the 16-bit general register specified in the register field of the instruction is decremented before the operand is accessed.

  • Page 38: How To Calculate Where The Execution Starts

    3.3.2 How to Calculate Where the Execution Starts Table 3-2 shows how to calculate the Effective Address (EA: Effective Address) for each addressing mode. In the operation instruction, 1) register direct, as well as 6) immediate (for each instruction, ADD.B, ADDX, SUBX, CMP.B, AND, OR, XOR) are used. In the move instruction, 7) program counter relative and 8) all addressing mode to delete the memory indirect can be used.
  • Page 39 Table 3-2. Effective Address Calculation (1) Addressing mode and instruction format Effective address calculation Effective address Register direct, Rn regm regn regm regn Operands are contained in registers regm and regn Register indirect, @Rn 16-bit register contents Register indirect with displacement, 16-bit register contents @(d:16, Rn) disp...
  • Page 40 Table 3-2. Effective Address Calculation (2) Addressing mode and instruction format Effective address calculation Effective address Absolute address H'FF @aa:8 @aa:16 Immediate #xx:8 Operand is 1- or 2-byte immediate data #xx:16 PC-relative PC contents @(d:8, PC) Sign extension disp disp...
  • Page 41 Table 3-2. Effective Address Calculation (3) Addressing mode and instruction format Effective address calculation Effective address Memory indirect, @@aa:8 H'00 Memory contents (16 bits) Notation reg: General register Operation code disp: Displacement IMM: Immediate data abs: Absolute address...

  • Page 42: Data Formats

    3.4 Data Formats The H8/300 CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. • Bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a byte operand.

  • Page 43: Data Formats In General Registers

    3.4.1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 3-3. Data type Register No. Data format 7 6 5 4 3 2 1 0 Don't-care 1-Bit data Don't-care 1-Bit data 7 6 5 4 3 2 1 0...

  • Page 44: Memory Data Formats

    3.4.2 Memory Data Formats Figure 3-4 indicates the data formats in memory. Word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded as “0.” If an odd address is specified, no address error occurs but the access is performed at the preceding even address.

  • Page 45: Instruction Set

    POP Rn is equivalent to MOV.W @SP+, Rn. *2 Bcc is a conditional branch instruction in which cc represents a condition code. *3 Not supported by the H8/329 Series. The following sections give a concise summary of the instructions in each category, and indicate...
  • Page 46 Operation Notation General register (destination) #xx:3 3-Bit immediate data General register (source) #xx:8 8-Bit immediate data General register #xx:16 16-Bit immediate data (EAd) Destination operand disp Displacement (EAs) Source operand Addition Stack pointer – Subtraction × Program counter Multiplication Condition code register ÷...

  • Page 47: Data Transfer Instructions

    @aa:8 addressing mode is available for byte data only. The @–R7 and @R7+ modes require word operands. Do not specify byte size for these two modes. Not supported by the H8/329 Series. MOVTPE Not supported by the H8/329 Series. MOVFPE Rn →...
  • Page 48 Rm → Rn Rn → @Rm, or @Rm → @(d:16, Rm) → Rn, or disp. Rn → @(d:16, Rm) @Rm+ → Rn, or Rn → @–Rm @aa:8 → Rn, or Rn → @aa:8 abs. @aa:16 → Rn, or abs. Rn → @aa:16 #xx:8 →...

  • Page 49: Arithmetic Operations

    3.5.2 Arithmetic Operations Table 3-5 describes the arithmetic instructions. See figure 3-6 in section 3.5.4, “Shift Operations” for their object codes. Table 3-5. Arithmetic Instructions Instruction Size* Function Rd ± Rs → Rd, Rd + #imm → Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register.

  • Page 50: Logic Operations

    3.5.3 Logic Operations Table 3-6 describes the four instructions that perform logic operations. See figure 3-6 in section 3.5.4, “Shift Operations,” for their object codes. Table 3-6. Logic Operation Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #imm → Rd Performs a logical AND operation on a general register and another general register or immediate data.
  • Page 51 ADD, SUB, CMP ADDX, SUBX (Rm), MULXU, DIVXU ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT #imm. ADD, ADDX, SUBX, CMP (#xx:8) AND, OR, XOR (Rm) #imm. AND, OR, XOR (#xx:8) SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR Operation field r m , r n : Register field #imm.:...

  • Page 52: Bit Manipulations

    3.5.5 Bit Manipulations Table 3-8 describes the bit-manipulation instructions. Figure 3-7 shows their object code formats. Table 3-8. Bit-Manipulation Instructions (1) Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory to “1.” The bit is specified by a bit number, given in 3-bit immediate data or the lower three bits of a general register.
  • Page 53 Table 3-8. Bit-Manipulation Instructions (2) Instruction Size* Function C ⊕ ¬ [(<bit-No.> of <EAd>)] → C BIXOR XORs the C flag with the inverse of a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data. (<bit-No.>...
  • Page 54 Before Execution of BCLR Instruction Input/output Input Input Output Output Output Output Output Output Pin state High Execution of BCLR Instruction ;clear bit 0 in data direction register BCLR #0, @P4DDR After Execution of BCLR Instruction Input/output Output Output Output Output Output Output Output Input Pin state High High...
  • Page 55 BSET, BCLR, BNOT, BTST #imm. Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register direct (Rn) Bit No.: register direct (Rm) Operand: register indirect (@Rn) #imm. Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) Bit No.: register direct (Rm) abs.

  • Page 56: Branching Instructions

    3.5.6 Branching Instructions Table 3-9 describes the branching instructions. Figure 3-8 shows their object code formats. Table 3-9. Branching Instructions Instruction Size Function — Branches to the specified address if condition cc is true. Mnemonic cc field Description Condition 0 0 0 0 Always (True) Always BRA (BT)
  • Page 57 disp. JMP (@Rm) JMP (@aa:16) abs. abs. JMP (@@aa:8) disp. JSR (@Rm) JSR (@aa:16) abs. abs. JSR (@@aa:8) Operation field Condition field r m : Register field disp.: Displacement abs.: Absolute address Figure 3-8. Branching Instruction Codes...

  • Page 58: System Control Instructions

    3.5.7 System Control Instructions Table 3-10 describes the system control instructions. Figure 3-9 shows their object code formats. Table 3-10. System Control Instructions Instruction Size Function — Returns from an exception-handling routine. — Causes a transition to the power-down state. SLEEP Rs →...

  • Page 59: Block Data Transfer Instruction

    RTE, SLEEP, NOP LDC, STC (Rn) #imm. ANDC, ORC, XORC, LDC (#xx:8) Operation field r n : Register field #imm.: Immediate data Figure 3-9. System Control Instruction Codes 3.5.8 Block Data Transfer Instruction Table 3-11 describes the EEPMOV instruction. Figure 3-10 shows its object code format. Table 3-11.

  • Page 60: Cpu States

    EEPROM Op: Operation field Figure 3-10. Block Data Transfer Instruction/EEPROM Write Operation Code Notes on EEPMOV Instruction 1. The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6. R5 →...

  • Page 61: Program Execution State

    Program SLEEP instruction Exception execution state SLEEP with SSBY bit set handling instruction request Exception handing Exception - Sleep mode handling state Interrupt request NMI or IRQ Software RES = 1 to IRQ standby mode STBY=1, RES=0 Hardware Reset state standby mode Power-down state Notes: *1 A transition to the reset state occurs when RES goes Low, except when the chip is in the hardware standby mode.

  • Page 62: Power-Down State

    3.6.3 Power-Down State The power-down state includes three modes: the sleep mode, the software standby mode, and the hardware standby mode. (1) Sleep Mode: The sleep mode is entered when a SLEEP instruction is executed. The CPU halts, but CPU register contents remain unchanged and the on-chip supporting modules continue to function.
  • Page 63 Bus cycle T2 state T1 state Ø Internal address bus Address Internal Read signal Internal data bus (read) Read data Internal Write signal Write data Internal data bus (write) Figure 3-13. On-Chip Memory Access Cycle Bus cycle T1 state T2 state Ø...

  • Page 64: Access To On-Chip Register Field And External Devices

    3.7.2 Access to On-Chip Register Field and External Devices The on-chip register field (I/O ports, on-chip supporting module registers, etc.) and external devices are accessed in a cycle consisting of three states: T , and T . Only one byte of data can be accessed per cycle, via an 8-bit data bus.
  • Page 65 Bus cycle T1 state T2 state T3 state Ø Address bus Address AS: High RD: High WR: High Data bus: high impedance state Figure 3-16. Pin States during On-Chip Register Field Access Cycle Read cycle T1 state T2 state T3 state Ø...
  • Page 66 Write cycle T1 state T2 state T3 state Ø Address bus Address RD: High Data bus Write data Figure 3-17 (b). External Device Access Timing (Write)

  • Page 68: Section 4. Exception Handling

    Section 4. Exception Handling 4.1 Overview The H8/329 Series recognizes only two kinds of exceptions: interrupts and the reset. Table 4-1 indicates their priority and the timing of their hardware exception-handling sequences. Table 4-1. Hardware Exception-Handling Sequences and Priority Type of...
  • Page 69 (1) The internal state of the CPU and the registers of the on-chip supporting modules are initialized, and the I bit in the condition code register (CCR) is set to “1.” (2) The CPU loads the program counter with the first word in the vector table (stored at addresses H'0000 and H'0001) and starts program execution.
  • Page 70 Internal process- Instruction prefetch Vector fetch Ø to A to D (8 bits) (1),(3) Reset vector address: (1)=H'0000, (3)=H'0001 (2),(4) Starting address of program (contents of reset vector): (2)=upper byte, (4)=lower byte (5),(7) Starting address of program: (5)=(2)(4), (7)=(2)(4)+1 (6),(8) First instruction of program: (6)=first byte, (8)=second byte Figure 4-2.

  • Page 71: Disabling Of Interrupts After Reset

    4.2.3 Disabling of Interrupts after Reset After a reset, if an interrupt were to be accepted before initialization of the stack pointer (SP: R7), the program counter and condition code register might not be saved correctly, leading to a program crash.
  • Page 72 H'0042 – H'0043 H'0044 – H'0045 A/D converter ADI (Conversion end) H'0046 – H'0047 Notes: 1. H'0000 and H'0001 contain the reset vector. 2. H'0002 to H'0005 are reserved in the H8/329 Series and are not available to the user.

  • Page 73: Interrupt-Related Registers

    4.3.2 Interrupt-Related Registers The interrupt-related registers are the system control register (SYSCR), IRQ sense control register (ISCR), and IRQ enable register (IER). Table 4-3. Registers Read by Interrupt Controller Name Abbreviation Read/Write Address System control register SYSCR H'FFC4 IRQ sense control register ISCR H'FFC6 IRQ enable register...
  • Page 74 Bits 0 to 2—IRQ to IRQ Sense Control (IRQ SC to IRQ SC): These bits determine whether to IRQ are level-sensed or sensed on the falling edge. Bits 0 to 2 SC to IRQ Description An interrupt is generated when IRQ to IRQ (Initial state) inputs are Low.

  • Page 75: External Interrupts

    If execution of interrupt-handling routines under these conditions is not desired, it can be avoided by using the following procedure to disable and clear interrupt requests. 1. Set the I bit to “1” in the CCR, masking interrupts. Note that the I bit is set to 1 automatically when execution jumps to an interrupt vector.

  • Page 76: Internal Interrupts

    4.3.4 Internal Interrupts Eighteen internal interrupts can be requested by the on-chip supporting modules. Each interrupt source has its own vector number, so the interrupt-handling routine does not have to determine which interrupt has occurred. All internal interrupts are masked when the I bit in the CCR is set to “1.”...
  • Page 77 The IRQ interrupts and interrupts from the on-chip supporting modules all have corresponding enable bits. When the enable bit is cleared to “0,” the interrupt signal is not sent to the interrupt controller, so the interrupt is ignored. These interrupts can also all be masked by setting the CPU’s interrupt mask bit (I) to “1.”...
  • Page 78 Program execution Interrupt requested? NMI? Pending I = 0? ADI? Latch vector No. Save PC Save CCR Reset I ← 1 Read vector address Branch to software interrupt-handling routine Figure 4-4. Hardware Interrupt-Handling Sequence...
  • Page 79 SP-4 SP(R7) SP-3 SP+1 CCR* SP+2 SP-2 PC (upper byte) SP-1 SP+3 PC (lower byte) SP(R7) SP+4 Even address Stack area Before interrupt After interrupt is accepted is accepted Pushed onto stack Program counter CCR: Condition code register Stack pointer Notes: The PC contains the address of the first instruction executed after return.
  • Page 80 Interrupt accepted Instruction fetch Interrupt priority (first instruction of decision. Wait for Instruction Internal Vector Internal interrupt-handling end of instruction. fetch process- Stack fetch process- routine) Interrupt request signal Ø Internal address Internal Read signal Internal Write signal Internal 16-bit (10) data bus Instruction prefetch address (Pushed on stack.

  • Page 81: Interrupt Response Time

    Table 4-4 indicates the number of states that elapse from an interrupt request signal until the first instruction of the software interrupt-handling routine is executed. Since the H8/329 Series accesses its on-chip memory 16 bits at a time, very fast interrupt service can be obtained by placing interrupt-handling routines in on-chip ROM and the stack in on-chip RAM.

  • Page 82: Note On Stack Handling

    Figure 4-7 shows an example in which the OCIAE bit is cleared to “0.” CPU write cycle to TIER OCIA interrupt handling Ø TIER address Internal address bus Internal write signal OCIAE OCFA OCIA interrupt signal Figure 4-7. Contention between Interrupt and Disabling Instruction The above contention does not occur if the enable bit or flag is cleared to “0”...
  • Page 83 H'FECC H'FECD H'FECF BSR instruction MOV.B R1L, @–R7 PC is improperly stored PC is lost H'FECF set in SP beyond top of stack PC : Upper byte of program counter PC : Lower byte of program counter R1 : General register SP : Stack pointer Figure 4-8.

  • Page 84: Section 5. I/O Ports

    Section 5. I/O Ports 5.1 Overview The H8/329 Series has seven parallel I/O ports, including: • Five 8-bit input/output ports—ports 1, 2, 3, 4, and 6 • One 8-bit input port—port 7 • One 3-bit input/output port—port 5 Ports 1, 2, and 3 have programmable input pull-up transistors. Ports 1 to 6 can drive a Darlington pair.
  • Page 85 Table 5-1. Port Functions Expanded modes Single-chip mode Port Description Pins Mode 1 Mode 2 Mode 3 Port 1 • 8-bit input-output P1 to P1 Address output General input General input/ port to A (low) when DDR = “0” output •...

  • Page 86: Port 1

    5.2 Port 1 Port 1 is an 8-bit input/output port that also provides the low bits of the address bus. The function of port 1 depends on the MCU mode as indicated in table 5-2. Table 5-2. Functions of Port 1 Mode 1 Mode 2 Mode 3...
  • Page 87 P1DDR is an 8-bit register that selects the direction of each pin in port 1. A pin functions as an output pin if the corresponding bit in P1DDR is set to “1,” and as an input pin if the bit is cleared to “0.”...
  • Page 88 Reset: A reset clears P1DDR, P1DR, and P1PCR to all “0,” placing all pins in the input state with the pull-up transistors off. In mode 1, when the chip comes out of reset, P1DDR is set to all “1.” Hardware Standby Mode: All pins are placed in the high-impedance state with the pull-up transistors off.

  • Page 89: Port 2

    Reset WP1P RP1P Mode 1 Reset Hardware standby WP1D Mode 3 Reset Mode 1 or 2 WP1P: Write Port 1 PCR WP1D: Write Port 1 DDR WP1: Write Port 1 RP1P : Read Port 1 PCR RP1: Read Port 1 n = 0 to 7 Note: Set-priority...
  • Page 90 Pins of port 2 can drive a single TTL load and a 90pF capacitive load when they are used as output pins. They can also drive light-emitting diodes and a Darlington pair. When they are used as input pins, they have programmable MOS transistor pull-ups. Table 5-6 details the port 2 registers.
  • Page 91 Port 2 Input Pull-Up Control Register (P2PCR)—H'FFAD PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 Initial value Read/Write P2PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 2. If a bit in P2DDR is cleared to “0”...
  • Page 92 Table 5-7 indicates the states of the input pull-up transistors in each operating mode. Table 5-7. States of Input Pull-Up Transistors (Port 2) Mode Reset Hardware standby Software standby Other operating modes On/off On/off On/off On/off Notes: Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if P2PCR = “1”...

  • Page 93: Port 3

    5.4 Port 3 Port 3 is an 8-bit input/output port that also provides the external data bus. The function of port 3 depends on the MCU mode as indicated in table 5-8. Table 5-8. Functions of Port 3 Mode 1 Mode 2 Mode 3 Data bus...
  • Page 94 Port 3 Data Register (P3DR)—H'FFB6 Initial value Read/Write P3DR is an 8-bit register containing the data for pins P3 to P3 . When the CPU reads P3DR, for output pins it reads the value in the P3DR latch, but for input pins, it obtains the logic level directly from the pin, bypassing the P3DR latch.
  • Page 95 Reset and Hardware Standby Mode: A reset or entry to the hardware standby mode clears P3DDR, P3DR, and P3PCR to all “0.” All pins are placed in the high-impedance state with the pull-up transistors off. Software Standby Mode: In the software standby mode, P3DDR, P3DR, and P3PCR remain in their previous state.
  • Page 96 Reset Mode 3 RP3P WP3P Mode 3 Reset External address write WP3D Mode 3 Reset Mode 1 or 2 External address read WP3P: Write Port 3 PCR WP3D: Write Port 3 DDR WP3: Write Port 3 RP3P : Read Port 3 PCR RP3: Read Port 3 n = 0 to 7...

  • Page 97: Port 4

    5.5 Port 4 Port 4 is an 8-bit input/output port that also provides pins for interrupt input (IRQ to IRQ ), A/D trigger input, system clock (Ø) output, and bus control signals (in the expanded modes). Pins P4 to P4 have different functions in different modes.
  • Page 98 Port 4 Data Direction Register (P4DDR)—H'FFB5 DDR P4 DDR P4 DDR P4 DDR P4 DDR P4 DDR P4 DDR P4 Modes 1 and 2 Initial value Read/Write — Mode 3 Initial value Read/Write P4DDR is an 8-bit register that selects the direction of each pin in port 4. A pin functions as an output pin if the corresponding bit in P4DDR is set to “1,”...
  • Page 99 In mode 3 (single-chip mode), these pins can be used for general-purpose input or output. Pin P4 : In modes 1 and 2, this pin is used for system clock (Ø) output. In mode 3, this pin is used for general-purpose input if P4 DDR is cleared to “0,”...
  • Page 100 Software Standby Mode: All pins remain in their previous state. For RD, WR, AS, and Ø this means the High output state. Figures 5-4 to 5-8 show schematic diagrams of port 4. Reset WP4D Reset A/D converter module ADTRG input WP4D: Write Port 4 DDR IRQ enable...
  • Page 101 Reset WP4D Reset input input WP4D: Write Port 4 DDR IRQ enable WP4: Write Port 4 register RP4: Read Port 4 n = 1, 2 enable enable Figure 5-5. Port 4 Schematic Diagram (Pins P4 and P4...
  • Page 102 Hardware standby Mode 1 or 2 Reset WP4D Mode 3 Reset Mode 1 or 2 RD output WR output AS ouput WP4D: Write Port 4 DDR WP4: Write Port 4 RP4: Read Port 4 n = 3, 4, 5 Figure 5-6. Port 4 Schematic Diagram (Pins P4 , P4 and P4...
  • Page 103 Mode 1, 2 Reset Hardware standby WP4D Ø WP4D: Write Port 4 DDR WP4: Write Port 4 RP4: Read Port 4 Note: Set-priority Figure 5-7. Port 4 Schematic Diagram (Pin P4...
  • Page 104 Reset Mode 1 or 2 WP4D Reset WAIT input WP4D: Write Port 4 DDR WP4: Write Port 4 RP4: Read Port 4 Figure 5-8. Port 4 Schematic Diagram (Pin P4...

  • Page 105: Port 5

    5.6 Port 5 Port 5 is a 3-bit input/output port that also provides input and output pins for the serial communi- cation interface (SCI). The pin functions depend on control bits in the serial control register (SCR). Pins not used for serial communication are available for general-purpose input/output. Table 5-13 lists the pin functions, which are the same in both the expanded and single-chip modes.
  • Page 106 Port 5 Data Register (P5DR)—H'FFBA — — — — — Initial value Read/Write — — — — — P5DR is an 8-bit register containing the data for pins P5 to P5 . When the CPU reads P5DR, for output pins (P5DDR = “1”) it reads the value in the P5DR latch, but for input pins (P5DDR = “0”), it obtains the logic level directly from the pin, bypassing the P5DR latch.
  • Page 107 Reset WP5D Reset SCI module Serial transmit enable Serial transmit data WP5D: Write Port 5 DDR WP5: Write Port 5 RP5: Read Port 5 Figure 5-9. Port 5 Schematic Diagram (Pin P5...
  • Page 108 Reset SCI module WP5D Serial receive enable Reset Serial receive data WP5D: Write Port 5 DDR WP5: Write Port 5 RP5: Read Port 5 Figure 5-10. Port 5 Schematic Diagram (Pin P5...

  • Page 109: Port 6

    Reset SCI module WP5D Serial clock Reset input enable Serial clock output enble Serial clock output enable Serial clock input WP5D: Write Port 5 DDR WP5: Write Port 5 RP5: Read Port 5 Figure 5-11. Port 5 Schematic Diagram (Pin P5...
  • Page 110 5.7 Port 6 Port 6 is an 8-bit input/output port that also provides input and output pins for the 16-bit free- running timer and 8-bit timers. The pin functions depend on control bits in the control registers of the timers. Pins not used by the timers are available for general-purpose input/output. Table 5-15 lists the pin functions, which are the same in both the expanded and single-chip modes.
  • Page 111 Port 6 Data Register (P6DR)—H'FFBB Initial value Read/Write P6DR is an 8-bit register containing the data for pins P6 to P6 . When the CPU reads P6DR, for output pins (P6DDR = “1”) it reads the value in the P6DR latch, but for input pins (P6DDR = “0”), it obtains the logic level directly from the pin, bypassing the P6DR latch.
  • Page 112 Pin P6 : This pin can be used for general-purpose input or output, input of the FTID input capture signal to the 16-bit free-running timer, or input of an external clock signal to 8-bit timer 1. FTID input operates simultaneously with the other functions. When external clock input is selected by the CKS bits of 8-bit timer 1, the P6DDR bit of this pin should normally be cleared to “0,”...
  • Page 113 Reset WP6D Reset Free-running timer module Counter clock input 8-bit timer module Counter clock input WP6D: Write Port 6 DDR WP6: Write Port 6 RP6: Read Port 6 Figure 5-12. Port 6 Schematic Diagram (Pin P6...
  • Page 114 Reset WP6D Reset Free-running timer module Output enable Output-compare output WP6D: Write Port 6 DDR WP6: Write Port 6 RP6: Read Port 6 Figure 5-13. Port 6 Schematic Diagram (Pin P6...
  • Page 115 Reset WP6D Reset Free-running timer module Input-capture input WP6D: Write Port 6 DDR WP6: Write Port 6 RP6: Read Port 6 Figure 5-14. Port 6 Schematic Diagram (Pin P6...
  • Page 116 Reset WP6D Reset Free-running timer module Input-capture input 8-bit timer module Counter clock input Counter reset input WP6D: Write Port 6 DDR WP6: Write Port 6 RP6: Read Port 6 n = 3, 5 Figure 5-15. Port 6 Schematic Diagram (Pins P6 and P6...
  • Page 117 Reset WP6D Reset 8-bit timer module Output enable 8-bit timer output Free-running timer module Input-capture input WP6D: Write Port 6 DDR WP6: Write Port 6 RP6: Read Port 6 Figure 5-16. Port 6 Schematic Diagram (Pin P6...
  • Page 118 Reset WP6D Reset Free-running timer module Output enable Output-compare output 8-bit timer module Counter reset input WP6D: Write Port 6 DDR WP6: Write Port 6 RP6: Read Port 6 Figure 5-17. Port 6 Schematic Diagram (Pin P6...
  • Page 119 Reset WP6D Reset 8-bit timer module Output enable 8-bit timer output WP6D: Write Port 6 DDR WP6: Write Port 6 RP6: Read Port 6 Figure 5-18. Port 6 Schematic Diagram (Pin P6...

  • Page 120: Port 7

    5.8 Port 7 Port 7 is an 8-bit input port that also provides the analog input pins for the A/D converter module. The pin functions are the same in both the expanded and single-chip modes. Table 5-17 lists the pin functions. Table 5-18 describes the port 7 data register, which simply consists of connections of the port 7 pins to the internal data bus.

  • Page 122: Section 6. 16-Bit Free-Running Timer

    Section 6. 16-Bit Free-Running Timer 6.1 Overview The H8/329 Series has an on-chip 16-bit free-running timer (FRT) module that uses a 16-bit free- running counter as a time base. Applications of the FRT module include rectangular-wave output (up to two independent waveforms), input pulse width measurement, and measurement of external clock periods.

  • Page 123: Block Diagram

    6.1.2 Block Diagram Figure 6-1 shows a block diagram of the free-running timer. Internal clock sources Ø/2 External Ø/8 clock source Ø/32 FTCI Clock OCRA (H/L) Clock select Compare- match A Comparator A FTOA Overflow FRC (H/L) FTOB Clear Internal data bus Comparator B Compare-...

  • Page 124: Input And Output Pins

    6.1.3 Input and Output Pins Table 6-1 lists the input and output pins of the free-running timer module. Table 6-1. Input and Output Pins of Free-Running Timer Module Name Abbreviation Function Counter clock input FTCI Input Input of external free-running counter clock signal Output compare A FTOA...

  • Page 125: Register Descriptions

    Table 6-2. Register Configuration (cont.) Initial Name Abbreviation value Address Input capture register B (High) ICRB (H) H'00 H'FF9A Input capture register B (Low) ICRB (L) H'00 H'FF9B Input capture register C (High) ICRC (H) H'00 H'FF9C Input capture register C (Low) ICRC (L) H'00 H'FF9D...

  • Page 126: Output Compare Registers A And B (Ocra And Ocrb)-H'ff94

    6.2.2 Output Compare Registers A and B (OCRA and OCRB)—H'FF94 Initial 1 value Read/ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Write OCRA and OCRB are 16-bit readable/writable registers, the contents of which are continually compared with the value in the FRC.
  • Page 127 Note: * The FRC contents are transferred to the input capture register regardless of the value of the input capture flag (ICFA/B/C/D). Input capture can be buffered by using the input capture registers in pairs. When the BUFEA bit in the timer control register (TCR) is set to “1,”...
  • Page 128 Table 6-3. Buffered Input Capture Edge Selection (Example) IEDGA IEDGC Input Capture Edge Captured on falling edge of input capture A (FTIA) (Initial value) Captured on both rising and falling edges of input capture A (FTIA) Captured on rising edge of input capture A (FTIA) Because the input capture registers are 16-bit registers, a temporary register (TEMP) is used when they are read.

  • Page 129: Timer Interrupt Enable Register (Tier)-H'ff90

    The input capture registers are initialized to H'0000 at a reset and in the standby modes. Note: When input capture is detected, the FRC value is transferred to the input capture register even if the input capture flag is already set. 6.2.4 Timer Interrupt Enable Register (TIER)—H'FF90 ICIAE ICIBE...
  • Page 130 Bit 5 ICICE Description Input capture interrupt request C (ICIC) is disabled. (Initial value) Input capture interrupt request C (ICIC) is enabled. Bit 4—Input Capture Interrupt D Enable (ICIDE): This bit selects whether to request input capture interrupt D (ICID) when input capture flag D (ICFD) in the timer status/control register (TCSR) is set to “1.”...

  • Page 131: Timer Control/Status Register (Tcsr)-H'ff91

    Bit 1 OVIE Description Timer overflow interrupt request (FOVI) is disabled. (Initial value) Timer overflow interrupt request (FOVI) is enabled. Bit 0—Reserved: This bit cannot be modified and is always read as “1.” 6.2.5 Timer Control/Status Register (TCSR)—H'FF91 ICFA ICFB ICFC ICFD OCFA...
  • Page 132 Bit 6—Input Capture Flag B (ICFB): This status bit is set to “1” to flag an input capture B event. If BUFEB = “0,” ICFB indicates that the FRC value has been copied to ICRB. If BUFEB = “1,” ICFB indicates that the old ICRB value has been moved into ICRC and the new FRC value has been copied to ICRB.
  • Page 133 Bit 4 ICFD Description To clear ICFD, the CPU must read ICFD after it (Initial value) has been set to “1,” then write a “0” in this bit. This bit is set to 1 when an FTID input signal is received. Bit 3—Output Compare Flag A (OCFA): This status flag is set to “1”...

  • Page 134: Timer Control Register (Tcr)-H'ff96

    Bit 0—Counter Clear A (CCLRA): This bit selects whether to clear the FRC at compare-match A (when the FRC and OCRA values match). Bit 0 CCLRA Description The FRC is not cleared. (Initial value) The FRC is cleared at compare-match A. 6.2.6 Timer Control Register (TCR)—H'FF96 IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1...
  • Page 135 Bit 5—Input Edge Select C (IEDGC): This bit causes input capture C events to be recognized on the selected edge of the input capture C signal (FTIC). Bit 5 IEDGC Description Input capture C events are recognized on the falling edge of FTIC. (Initial value) Input capture C events are recognized on the rising edge of FTIC.

  • Page 136: Timer Output Compare Control Register (Tocr)-H'ff97

    Bit 1 Bit 0 CKS1 CKS0 Description Ø/2 Internal clock source (Initial value) Ø/8 Internal clock source Ø/32 Internal clock source External clock source (rising edge) 6.2.7 Timer Output Compare Control Register (TOCR)—H'FF97 — — — OCRS OLVLA OLVLB Initial value Read/Write —...

  • Page 137: Cpu Interface

    Bit 2—Output Enable B (OEB): This bit enables or disables output of the output compare B signal (FTOB). Bit 2 OEB Description Output compare B output is disabled. (Initial value) Output compare B output is enabled. Bit 1—Output Level A (OLVLA): This bit selects the logic level to be output at the FTOA pin when the FRC and OCRA values match.
  • Page 138 • Register Read When the CPU reads the upper byte, the upper byte of data is sent to the CPU and the lower byte is placed in TEMP. When the CPU reads the lower byte, it receives the value in TEMP. (As an exception, when the CPU reads OCRA or OCRB, it reads both the upper and lower bytes directly, without using TEMP.) Programs that access these registers should normally use word access.

  • Page 139: Operation

    (1) Upper byte read Module data bus CPU reads Bus interface data H'AA TEMP [H'55] FRC H FRC L [H'AA] [H'55] (2) Lower byte read Module data bus CPU reads Bus interface data H'55 TEMP [H'55] FRC H FRC L Figure 6-4 (b).
  • Page 140 Ø Internal clock FRC clock pulse N – 1 N + 1 Figure 6-5. Increment Timing for Internal Clock Source External Clock: If external clock input is selected, the FRC increments on the rising edge of the FTCI clock signal. Figure 6-6 shows the increment timing. The pulse width of the external clock signal must be at least 1.5 system clock (Ø) periods.

  • Page 141: Output Compare Timing

    6.4.2 Output Compare Timing (1) Setting of Output Compare Flags A and B (OCFA and OCFB): The output compare flags are set to “1” by an internal compare-match signal generated when the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last state in which the two values match, just before the FRC increments to a new value.

  • Page 142: Input Capture Timing

    (2) Output Timing: When a compare-match occurs, the logic level selected by the output level bit (OLVLA or OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Figure 6-9 shows the timing of this operation for compare-match A. Ø...
  • Page 143 Ø Input at FTI pin Internal input capture signal Figure 6-11. Input Capture Timing (Usual Case) If the upper byte of ICRx is being read when the input capture signal arrives, the internal input capture signal is delayed by one state. Figure 6-12 shows the timing for this case. Read cycle: CPU reads upper byte of ICR Ø...
  • Page 144 Figure 6-14 shows how input capture operates when ICRA and ICRC are used in buffer mode and IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA. Ø...

  • Page 145: Setting Of Frc Overflow Flag (Ovf)

    (2) Timing of Input Capture Flag (ICF) Setting: The input capture flag ICFx (x = A, B, C, D) is set to “1” by the internal input capture signal. Figure 6-15 shows the timing of this operation. Ø Internal input capture signal ICFA/B/C/D ICRA/B/C/D...

  • Page 146: Interrupts

    6.5 Interrupts The free-running timer can request seven types of interrupts: input capture A to D (ICIA, ICIB, ICIC, ICID), output compare A and B (OCIA and OCIB), and overflow (FOVI). Each interrupt is requested when the corresponding enable and flag bits are set. Independent signals are sent to the interrupt controller for each type of interrupt.

  • Page 147: Application Notes

    6.7 Application Notes Application programmers should note that the following types of contention can occur in the free- running timers. (1) Contention between FRC Write and Clear: If an internal counter clear signal is generated during the T state of a write cycle to the lower byte of the free-running counter, the clear signal takes priority and the write is not performed.
  • Page 148 (2) Contention between FRC Write and Increment: If an FRC increment pulse is generated during the T state of a write cycle to the lower byte of the free-running counter, the write takes priority and the FRC is not incremented. Figure 6-19 shows this type of contention.
  • Page 149 (3) Contention between OCR Write and Compare-Match: If a compare-match occurs during the T state of a write cycle to the lower byte of OCRA or OCRB, the write takes priority and the compare-match signal is inhibited. Figure 6-20 shows this type of contention. Write cycle: CPU write to lower byte of OCRA or OCRB Ø...
  • Page 150 (4) Incrementation Caused by Changing of Internal Clock Source: When an internal clock source is changed, the changeover may cause the FRC to increment. This depends on the time at which the clock select bits (CKS1 and CKS0) are rewritten, as shown in table 6-5. The pulse that increments the FRC is generated at the falling edge of the internal clock source.
  • Page 151 Table 6-5. Effect of Changing Internal Clock Sources (cont.) Description Timing chart High → Low: Old clock CKS1 and CKS0 are source rewritten while old clock source is High and New clock source new clock source is Low. FRC clock pulse N + 1 N + 2...

  • Page 152: Section 7. 8-Bit Timers

    Section 7. 8-Bit Timers 7.1 Overview The H8/329 Series includes an 8-bit timer module with two channels (TMR0 and TMR1). Each channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to detect compare-match events. One application of the 8-bit timer module is to generate a rectangular-wave output with an arbitrary duty cycle.

  • Page 153: Input And Output Pins

    Internal External clock sources Channel 0 Channel 1 clock source Ø/2 Ø/2 TMCI Ø/8 Ø/8 Ø/32 Ø/64 Ø/64 Ø/128 Ø/256 Ø/1024 Ø/1024 Ø/2048 Clock Clock select TCORA Compare-match A Comparator A Internal Overflow data bus TMRI TCNT Clear Comparator B Control Compare-match B logic...

  • Page 154: Register Configuration

    7.1.4 Register Configuration Table 7-2 lists the registers of the 8-bit timer module. Each channel has an independent set of registers. Table 7-2. 8-Bit Timer Registers Address Name Abbreviation Initial value TMR0 TMR1 Timer control register H'00 H'FFC8 H'FFD0 Timer control/status register TCSR R/(W)* H'10...

  • Page 155: Time Constant Registers A And B (Tcora And Tcorb)- H'ffca And H'ffcb (Tmr0), H'ffd2 And H'ffd3 (Tmr1)

    The timer counters are initialized to H'00 at a reset and in the standby modes. 7.2.2 Time Constant Registers A and B (TCORA and TCORB)—H'FFCA and H'FFCB (TMR0), H'FFD2 and H'FFD3 (TMR1) Initial value Read/Write TCORA and TCORB are 8-bit readable/writable registers. The timer count is continually compared with the constants written in these registers.
  • Page 156 Bit 7 CMIEB Description Compare-match interrupt request B (CMIB) is disabled. (Initial value) Compare-match interrupt request B (CMIB) is enabled. Bit 6-Compare-match Interrupt Enable A (CMIEA): This bit selects whether to request compare-match interrupt A (CMIA) when compare-match flag A (CMFA) in the timer control/status register (TCSR) is set to “1”.
  • Page 157 Bits 2, 1, and 0—Clock Select (CKS2, CKS1, and CKS0): These bits and bits ICKS1 and ICKS0 in the serial/timer control register (STCR) select the internal or external clock source for the timer counter. Six internal clock sources, derived by prescaling the system clock, are available for each timer channel.

  • Page 158: Timer Control/Status Register (Tcsr)-H'ffc9 (Tmr0), H'ffd1 (Tmr1)

    7.2.4 Timer Control/Status Register (TCSR)—H'FFC9 (TMR0), H'FFD1 (TMR1) CMFB CMFA — Initial value Read/Write R/(W)* R/(W)* R/(W)* — Note: * Software can write a “0” in bits 7 to 5 to clear the flags, but cannot write a “1” in these bits. The TCSR is an 8-bit readable and partially writable register that indicates compare-match and overflow status and selects the effect of compare-match events on the timer output signal.
  • Page 159 Bit 5—Timer Overflow Flag (OVF): This status flag is set to “1” when the timer count overflows (changes from H'FF to H'00). OVF must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 5 Description To clear OVF, the CPU must read OVF after...

  • Page 160: Serial/Timer Control Register (Stcr)-H'ffc3

    7.2.5 Serial/Timer Control Register (STCR)—H'FFC3 — — — — — ICKS1 ICKS0 Initial value Read/Write — — — — — The STCR is an 8-bit readable/writable register that controls the serial communication interface and selects internal clock sources for the timer counters. The STCR is initialized to H'F8 at a reset.

  • Page 161: Operation

    7.3 Operation 7.3.1 TCNT Incrementation Timing The timer counter increments on a pulse generated once for each period of the selected (internal or external) clock source. Internal Clock: Internal clock sources are created from the system clock by a prescaler. Thecounter increments on an internal TCNT clock pulse generated from the falling edge of the prescaler output, as shown in figure 7-2.

  • Page 162: Compare Match Timing

    Ø External clock source TCNT clock pulse TCNT N – 1 N + 1 Figure 7-3. Count Timing for External Clock Input Ø TMCI Minimum TMCI Pulse Width (Single-Edge Incrementation) Ø TMCI Minimum TMCI Pulse Width (Double-Edge Incrementation) Figure 7-4. Minimum External Clock Pulse Widths (Example) 7.3.2 Compare Match Timing (1) Setting of Compare-Match Flags A and B (CMFA and CMFB): The compare-match flags are set to “1”...
  • Page 163 Accordingly, when the timer count matches one of the time constants, the compare-match signal is not generated until the next period of the clock source. Figure 7-5 shows the timing of the setting of the compare-match flags. Ø N + 1 TCNT TCOR Internal...

  • Page 164: External Reset Of Tcnt

    (3) Timing of Compare-Match Clear: Depending on the CCLR1 and CCLR0 bits in the TCR, the timer counter can be cleared when compare-match A or B occurs. Figure 7-7 shows the timing of this operation. Ø ø Internal compare-match signal TCNT H'00 Figure 7-7.

  • Page 165: Setting Of Tcsr Overflow Flag (Ovf)

    7.3.4 Setting of TCSR Overflow Flag (OVF) The overflow flag (OVF) is set to “1” when the timer count overflows (changes from H'FF to H'00). Figure 7-9 shows the timing of this operation. Ø ø TCNT H'FF H'00 Internal overflow signal...

  • Page 166: Interrupts

    7.4 Interrupts Each channel in the 8-bit timer can generate three types of interrupts: compare-match A and B (CMIA and CMIB), and overflow (OVI). Each interrupt is requested when the corresponding enable bits are set in the TCR and TCSR. Independent signals are sent to the interrupt controller for each interrupt.

  • Page 167: Application Notes

    7.6 Application Notes Application programmers should note that the following types of contention can occur in the 8-bit timer. (1) Contention between TCNT Write and Clear: If an internal counter clear signal is generated during the T state of a write cycle to the timer counter, the clear signal takes priority and the write is not performed.
  • Page 168 (2) Contention between TCNT Write and Increment: If a timer counter increment pulse is generated during the T state of a write cycle to the timer counter, the write takes priority and the timer counter is not incremented. Figure 7-12 shows this type of contention. Write cycle: CPU writes to TCNT Ø...
  • Page 169 Write cycle: CPU writes to TCORA or TCORB Ø Internal address TCOR address Internal write signal N + 1 TCNT TCORA or TCORB TCOR write data Compare-match A or B signal Inhibited Figure 7-13. Contention between TCOR Write and Compare-Match (4) Contention between Compare-Match A and Compare-Match B: If identical time constants are written in TCORA and TCORB, causing compare-match A and B to occur simultaneously, any conflict between the output selections for compare-match A and B is resolved by following the...
  • Page 170 (5) Incrementation Caused by Changing of Internal Clock Source: When an internal clock source is changed, the changeover may cause the timer counter to increment. This depends on the time at which the clock select bits (CKS1, CKS0) are rewritten, as shown in table 7-5. The pulse that increments the timer counter is generated at the falling edge of the internal clock source signal.
  • Page 171 Table 7-5. Effect of Changing Internal Clock Sources (cont.) Description Timing chart High → Low Old clock source Clock select bits are rewritten while old New clock clock source is High and source new clock source is Low. TCNT clock pulse TCNT N + 1...

  • Page 172: Section 8. Serial Communication Interface

    Section 8. Serial Communication Interface 8.1 Overview The H8/329 Series includes a serial communication interface (SCI) for transferring serial data to and from other chips. Either synchronous or asynchronous communication can be selected. 8.1.1 Features The features of the on-chip serial communication interface are: •...

  • Page 173: Block Diagram

    8.1.2 Block Diagram Figure 8-1 shows a block diagram of the serial communication interface. Internal data bus Module data bus Internal Ø Communi- clock Ø/4 Baud rate cation Ø/16 generator control Ø/64 Parity generate Clock Parity check External clock source RSR: Receive Shift Register (8 bits) Receive Data Register (8 bits)

  • Page 174: Input And Output Pins

    8.1.3 Input and Output Pins Table 8-1 lists the input and output pins used by the SCI module. Table 8-1. SCI Input/Output Pins Name Abbr. Function Serial clock Input/output Serial clock input and output. Receive data Input Receive data input. Transmit data Output Transmit data output.

  • Page 175: Register Descriptions

    8.2 Register Descriptions 8.2.1 Receive Shift Register (RSR) Read/Write — — — — — — — — The RSR receives incoming data bits. When one data character has been received, it is transferred to the receive data register (RDR). The CPU cannot read or write the RSR directly. 8.2.2 Receive Data Register (RDR)—H'FFDD Initial value Read/Write...

  • Page 176: Transmit Data Register (Tdr)-H'ffdb

    8.2.4 Transmit Data Register (TDR)—H'FFDB Initial value Read/Write The TDR is an 8-bit readable/writable register that holds the next character to be transmitted. When the TSR becomes empty, the character written in the TDR is transferred to the TSR. Continuous data transmission is possible by writing the next byte in the TDR while the current byte is being transmitted from the TSR.
  • Page 177 Bit 6—Character Length (CHR): This bit selects the character length in asynchronous mode. It is ignored in synchronous mode. The character length is always eight bits in synchronous mode. Bit 6 Description 8 bits per character. (Initial value) 7 bits per character. (Bits 0 to 6 in TDR and RDR are sent and received.) Bit 5—Parity Enable (PE): This bit selects whether to add a parity bit in asynchronous mode.
  • Page 178 Bit 3—Stop Bit Length (STOP): This bit selects the number of stop bits. It is ignored in the synchronous mode. Bit 3 STOP Description One stop bit (Initial value) Transmit: one stop bit is added. Receive: one stop bit is checked to detect framing errors. Two stop bits Transmit: two stop bits are added.

  • Page 179: Serial Control Register (Scr)-H'ffda

    8.2.6 Serial Control Register (SCR)—H'FFDA MPIE TEIE CKE1 CKE0 Initial value Read/Write The SCR is an 8-bit readable/writable register that enables or disables various SCI functions. It is initialized to H'00 at a reset and in the standby modes. Bit 7—Transmit Interrupt Enable (TIE): This bit enables or disables the TDR-empty interrupt (TXI) requested when the transmit data register empty (TDRE) bit in the serial status register (SSR) is set to “1.”...
  • Page 180 Bit 5—Transmit Enable (TE): This bit enables or disables the transmit function. When the transmit function is enabled, the TxD pin is automatically used for output. When the transmit function is disabled, the TxD pin can be used as a general-purpose I/O port. Bit 5 Description The transmit function is disabled.
  • Page 181 Bit 3—Multiprocessor Interrupt Enable (MPIE): When serial data are received in a multiprocessor format, this bit enables or disables the receive-end interrupt (RxI) and receive-error interrupt (ERI) until data with the multiprocessor bit set to “1” are received. It also enables or disables the transfer of received data from the RSR to the RDR, and enables or disables setting of the RDRF, FER, PER, and ORER bits in the serial status register (SSR).
  • Page 182 Bit 2—Transmit-End Interrupt Enable (TEIE): This bit enables or disables the TSR-empty interrupt (TEI) requested when the transmit-end bit (TEND) in the serial status register (SSR) is set to “1.” Bit 2 TEIE Description The TSR-empty interrupt request (TEI) is disabled. (Initial value) The TSR-empty interrupt request (TEI) is enabled.

  • Page 183: Serial Status Register (Ssr)-H'ffdc

    8.2.7 Serial Status Register (SSR)—H'FFDC TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Software can write a “0” to clear the flags, but cannot write a “1” in these bits. The SSR is an 8-bit register that indicates transmit and receive status. It is initialized to H'84 at a reset and in the standby modes.
  • Page 184 Bit 5—Overrun Error (ORER): This bit indicates an overrun error during reception. Bit 5 ORER Description To clear ORER, the CPU must read ORER after (Initial value) it has been set to “1,” then write a “0” in this bit. This bit is set to 1 if reception of the next character ends while the receive data register is still full (RDRF = “1”).
  • Page 185 Bit 2—Transmit End (TEND): This bit indicates that transmission of a character has ended and the serial communication interface has stopped transmitting because there is no valid data in the TDR. The TEND bit is also set to “1” when the TE bit in the serial control register (SCR) is cleared to “0.”...

  • Page 186: Bit Rate Register (Brr)-H'ffd9

    8.2.8 Bit Rate Register (BRR)—H'FFD9 Initial value Read/Write The BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in the SMR, determines the baud rate output by the baud rate generator. The BRR is initialized to H'FF (the slowest rate) at a reset and in the standby modes. Tables 8-3 and 8-4 show examples of BRR (N) and CKS (n) settings for commonly used bit rates.
  • Page 187 Table 8-3. Examples of BRR Settings in Asynchronous Mode (2) XTAL frequency (MHz) 4.9152 7.3728 Error Error Error Error rate 174 –0.26 +0.50 +0.70 +0.03 127 0 155 +0.16 +0.16 255 0 +0.16 +0.16 127 0 155 +0.16 +0.16 1200 +0.16 +0.16 2400...
  • Page 188 Table 8-3. Examples of BRR Settings in Asynchronous Mode (4) XTAL frequency (MHz) 14.7456 19.6608 Error Error Error Error rate 130 –0.07 141 +0.03 –0.26 +0.88 103 +0.16 +0.16 191 0 207 +0.16 +0.16 103 +0.16 +0.16 1200 191 0 207 +0.16 +0.16 2400...
  • Page 189 Table 8-4. Examples of BRR Settings in Synchronous Mode XTAL frequency (MHz) rate — — — — — — — — — — — — — — — — — — — — — — — — 2.5k 100k — —...

  • Page 190: Serial/Timer Control Register (Stcr)-H'ffc3

    8.2.9 Serial/Timer Control Register (STCR)—H'FFC3 — — — — — ICKS1 ICKS0 Initial value Read/Write — — — — — The STCR is an 8-bit readable/writable register that controls the operating mode of the serial communication interface and selects input clock sources for the 8-bit timer counters (TCNT). The STCR is initialized to H'F8 by a reset.

  • Page 191: Operation

    8.3 Operation 8.3.1 Overview The SCI supports serial data transfer in two modes. In asynchronous mode each character is synchronized individually. In synchronous mode communication is synchronized with a clock signal. The selection of asynchronous or synchronous mode and the communication format depend on settings in the SMR as indicated in table 8-5.
  • Page 192 Table 8-5. Communication Formats Used by SCI SMR settings Communication format Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 Data Multipro- Parity Stop-bit C/A CHR MP STOP Mode length cessor bit length Asynchronous mode 8 bits None None 1 bit 2 bits Present 1 bit...

  • Page 193: Asynchronous Mode

    8.3.2 Asynchronous Mode In asynchronous mode, each transmitted or received character is individually synchronized by framing it with a start bit and stop bit. Full duplex data transfer is possible because the SCI has independent transmit and receive sections. Double buffering in both sections enables data to be written and read during serial communication, for continuous data transfer.
  • Page 194 Table 8-7. Data Formats in Asynchronous Mode SMR Bits STOP 8-Bit data STOP 8-Bit data STOP STOP 8-Bit data STOP 8-Bit data STOP STOP 7-Bit data STOP 7-Bit data STOP STOP 7-Bit data STOP 7-Bit data STOP STOP — 8-Bit data STOP —...
  • Page 195 “0” “1” “1” One frame Figure 8-3. Phase Relationship between Clock Output and Transmit Data (Asynchronous Mode) (3) Transmitting and Receiving Data • SCI Initialization: Before transmitting or receiving, software must clear the TE and RE bits to “0” in the serial control register (SCR), then initialize the SCI as follows. Note: When changing the communication mode or format, always clear the TE and RE bits to “0”...
  • Page 196 Initialization Select the communication format in the serial mode register (SMR). Write the value corresponding to the bit rate in the bit rate register Clear TE and RE bits to (BRR). This step is not necessary when an external clock is used. “0”...
  • Page 197 • Transmitting Serial Data: Follow the procedure below for transmitting serial data. SCI initialization: the transmit data output function of the TxD pin is Initialize selected automatically. SCI status check and transmit data write: read the serial status Start transmitting register (SSR), check that the TDRE bit is “1,”...
  • Page 198 In transmitting serial data, the SCI operates as follows. 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to “0” the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from TDR into the transmit shift register (TSR).
  • Page 199 Figure 8-6 shows an example of SCI transmit operation in asynchronous mode. Start Parity Stop Start Parity Stop “1” Data Data “1” “0” “1” “0” “1” Mark (idle) state TDRE TEND TXI interrupt handler request writes data in TDR and request TEI request clears TDRE to “0”...
  • Page 200 • Receiving Serial Data: Follow the procedure below for receiving serial data. Initialize SCI initialization: the receive data function of the RxD pin is selected automatically. Start receiving SCI status check and receive data read: read the serial status register (SSR), check that RDRF is set to “1,” then read receive Read RDRF bit in SSR data from the receive data register (RDR) and clear RDRF to “0.”...
  • Page 201 In receiving, the SCI operates as follows. 1. The SCI monitors the receive data line and synchronizes internally when it detects a start bit. 2. Receive data are shifted into RSR in order from LSB to MSB. 3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following checks: (a) Parity check: the number of 1s in the receive data must match the even or odd parity setting of the O/E bit in SMR.
  • Page 202 Figure 8-8 shows an example of SCI receive operation in asynchronous mode. Table 8-8. Receive Error Conditions and SCI Operation Receive error Abbreviation Condition Data transfer Overrun error ORER Receiving of next data ends Receive data not loaded from while RDRF is still set to “1” RSR into RDR in SSR Framing error...
  • Page 203 (4) Multiprocessor Communication The multiprocessor communication function enables several processors to share a single serial communication line. The processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by an ID. A serial communication cycle consists of two cycles: an ID-sending cycle that identifies the receiving processor, and a data-sending cycle.
  • Page 204 • Transmitting Multiprocessor Serial Data: See figures 8-5 and 8-6. • Receiving Multiprocessor Serial Data: Follow the procedure below for receiving multiprocessor serial data. Initialize SCI initialization: the receive data function of the RxD pin is selected automatically. ID receive cycle: Set the MPIE bit in the serial control register Start receiving (SCR) to “1.”...
  • Page 205 Figure 8-11 shows an example of SCI receive operation using a multiprocessor format. Start Stop Start Stop Data (ID1) Data (Data2) “1” “1” “0” “1” “1” “0” “0” “1” Mark (idle) state MPIE RDRF RDR value RXI request, RXI handler reads Not own ID, so No RXI request, MPIE = “0”...

  • Page 206: Clocked Synchronous Operation

    8.3.3 Clocked Synchronous Operation (1) Overview: In clocked synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver share the same clock but are otherwise independent, so full duplex communication is possible.
  • Page 207 • Communication Format: The data length is fixed at eight bits. No parity bit or multiprocessor bit can be added. • Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected by clearing or setting the CKE1 bit in the serial control register (SCR).
  • Page 208 • Transmitting Serial Data: Follow the procedure below for transmitting serial data. SCI initialization: the transmit data output function of the TxD pin is Initialize selected automatically. SCI status check and transmit data write: read the serial status Start transmitting register (SSR), check that the TDRE bit is “1,”...
  • Page 209 In transmitting serial data, the SCI operates as follows. 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to “0” the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from TDR into the transmit shift register (TSR).
  • Page 210 Figure 8-14 shows an example of SCI transmit operation. Serial clock Data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request handler writes request data in TDR and request clears TDRE to “0” 1 frame Figure 8-14.
  • Page 211 • Receiving Serial Data: Follow the procedure below for receiving serial data. When switching from asynchronous mode to clocked synchronous mode, be sure to check that PER and FER are cleared to “0.” If PER or FER is set to “1” the RDRF bit will not be set and both transmitting and receiving will be disabled.
  • Page 212 In receiving, the SCI operates as follows. 1. If an external clock is selected, data are input in synchronization with the input clock. If clock output is selected, as soon as the RE bit is set to “1” the SCI begins outputting the serial clock and inputting data.
  • Page 213 Figure 8-16 shows an example of SCI receive operation. Serial clock Data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt request handler reads request Overrun error, data in RDR and ERI request clears RDRF to “0”...
  • Page 214 • Transmitting and Receiving Serial Data Simultaneously: Follow the procedure below for transmitting and receiving serial data simultaneously. If clock output mode is selected, output of the serial clock begins simultaneously with serial transmission. Initialize SCI initialization: the transmit data output function of the TxD pin and receive data input function of the RxD pin are selected, Start enabling simultaneous transmitting and receiving.

  • Page 215: Sci Interrupts

    8.4 SCI Interrupts The SCI can request four types of interrupts: ERI, RXI, TXI, and TEI. Table 8-9 indicates the source and priority of these interrupts. The interrupt sources can be enabled or disabled by the TIE, RIE, and TEIE bits in the SCR. Independent signals are sent to the interrupt controller for each interrupt source, except that the receive-error interrupt (ERI) is the logical OR of three sources: overrun error, framing error, and parity error.
  • Page 216 (2) Multiple Receive Errors: Table 8-10 lists the values of flag bits in the SSR when multiple receive errors occur, and indicates whether the RSR contents are transferred to the RDR. Table 8-10. SSR Bit States and Data Transfer When Multiple Receive Errors Occur RSR →...
  • Page 217 5 6 7 8 9 1112 1314 1516 1 2 3 4 5 6 7 8 9 10 11 131415 16 3 4 5 Basic clock –7.5 pulses +7.5 pulses Receive data Start bit Sync sampling Data sampling Figure 8-18. Sampling Timing (Asynchronous Mode) M = {(0.5 –...

  • Page 218: Section 9. A/D Converter

    Section 9. A/D Converter 9.1 Overview The H8/329 Series includes an analog-to-digital converter module with eight input channels. A/D conversion is performed by the successive approximations method with 8-bit resolution. 9.1.1 Features The features of the on-chip A/D module are: •...

  • Page 219: Block Diagram

    9.1.2 Block Diagram Internal Module data bus data bus 8 Bit Ø/8 Ø/16 Analog – multi- Control circuit plexer Comparator Sample and hold circuit Interrupt signal ADTRG ADCR: A/D Control Register (8 bits) ADCSR: A/D Control/Status Register (8 bits) ADDRA: A/D Data Register A (8 bits) ADDRB: A/D Data Register B (8 bits) ADDRC: A/D Data Register C (8 bits) ADDRD: A/D Data Register D (8 bits)

  • Page 220: Input Pins

    9.1.3 Input Pins Table 9-1 lists the input pins used by the A/D converter module. The eight analog input pins are divided into two groups, consisting of analog inputs 0 to 3 (AN ) and analog inputs 4 to 7 (AN to AN ), respectively.

  • Page 221: Register Descriptions

    9.2 Register Descriptions 9.2.1 A/D Data Registers (ADDR)—H'FFE0 to H'FFE6 ADDRn Initial value Read/Write (n = A to D) The four A/D data registers (ADDRA to ADDRD) are 8-bit read-only registers that store the results of A/D conversion. Each data register is assigned to two analog input channels as indicated in table 9-3.
  • Page 222 The ADCSR is initialized to H'00 at a reset and in the standby modes. Bit 7—A/D End Flag (ADF): This status flag indicates the end of one cycle of A/D conversion. Bit 7 Description To clear ADF, the CPU must read ADF after (Initial value) it has been set to “1,”...
  • Page 223 Bit 4—Scan Mode (SCAN): This bit selects the scan mode or single mode of operation. See section 9.3, “Operation” for descriptions of these modes. The mode should be changed only when the ADST bit is cleared to “0.” Bit 4 SCAN Description Single mode...

  • Page 224: A/D Control Register (Adcr)-H'ffea

    9.2.3 A/D Control Register (ADCR)—H'FFEA TRGE — — — — — — Initial value Read/Write — — — — — — The A/D control register (ADCR) is an 8-bit readable/writable register that enables or disables the A/D external trigger signal. The ADCR is initialized to H'7E at a reset and in the standby modes.

  • Page 225: Operation

    9.3 Operation The A/D converter performs 8 successive approximations to obtain a result ranging from H'00 (corresponding to AV ) to H'FF (corresponding to AV The A/D converter module can be programmed to operate in single mode or scan mode as explained below.
  • Page 226 The following example explains the A/D conversion process in single mode when channel 1 (AN1) is selected and the external trigger is disabled. Figure 9-2 shows the corresponding timing chart. (1) Software clears the ADST bit to “0,” then selects the single mode (SCAN = “0”) and channel 1 (CH2 to CH0 = “001”), enables the A/D interrupt request (ADIE = “1”), and sets the ADST bit to “1”...
  • Page 227 Interrupt (ADI) Set* ADIE Set* Set* A/D conversion starts ADST Clear* Clear* Channel 0 (AN Waiting Channel 1 (AN Waiting A/D conver- Waiting Waiting A/D conver- sion sion Channel 2 (AN Waiting Channel 3 (AN Waiting ADDRA Read result Read result ADDRB A/D conversion result A/D conversion result...

  • Page 228: Scan Mode (Scan = 1)

    9.3.2 Scan Mode (SCAN = 1) The scan mode can be used to monitor analog inputs on one or more channels. When the ADST bit is set to “1,” either by software or by a High-to-Low transition of the ADTRG signal (if enabled), A/D conversion starts from the first channel selected by the CH bits.
  • Page 229 (2) The A/D converter converts the voltage level at the AN input pin to a digital value, and transfers the result to register ADDRA. (3) Next the A/D converter converts AN and transfers the result to ADDRB. Then it converts and transfers the result to ADDRC.
  • Page 230 Continuous A/D conversion Clear ADST Clear A/D conversion time Channel 0 (AN A/D conver- A/D conver- Waiting Waiting Waiting sion sion Channel 1 (AN A/D conver- Waiting Waiting A/D conver- Waiting sion sion Channel 2 (AN Waiting A/D conver- Waiting sion Channel 3 (AN Waiting...

  • Page 231: Input Sampling Time And A/D Conversion Time

    9.3.3 Input Sampling Time and A/D Conversion Time The A/D converter includes a built-in sample-and-hold circuit. Sampling of the input starts at a time t after the ADST bit is set to “1.” The sampling process lasts for a time t .

  • Page 232: External Trigger Input Timing

    Table 9-4 (a). A/D Conversion Time (Single Mode) CKS = “0” CKS = “1” Item Symbol Synchronization delay — — Input sampling time — — — — Total A/D conversion time t — — CONV Table 9-4 (b). A/D Conversion Time (Scan Mode) CKS = “0”...

  • Page 233: Interrupts

    Ø ADTRG Internal trigger signal ADST A/D conversion Figure 9-5. External Trigger Input Timing 9.4 Interrupts The A/D conversion module generates an A/D-end interrupt request (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in the A/D control/status register (ADCSR).

  • Page 234: Section 10. Ram

    Section 10. RAM 10.1 Overview The H8/329 and H8/328 include 1k byte of on-chip static RAM. The H8/327 has 512 bytes. The H8/326 has 256 bytes. The on-chip RAM is connected to the CPU by a 16-bit data bus. Both byte and word access to the on-chip RAM are performed in two states, enabling rapid data transfer and instruction execution.

  • Page 235: Operation

    10.3 RAM Enable Bit (RAME) in System Control Register (SYSCR) The on-chip RAM is enabled or disabled by the RAME (RAM Enable) bit in the system control register (SYSCR). SSBY STS2 STS1 STS0 — NMIEG — RAME Initial value Read/Write —...

  • Page 236: Section 11. Rom

    Section 11. ROM 11.1 Overview The H8/329 includes 32k bytes of high-speed, on-chip ROM. The H8/328 has 24k bytes. The H8/327 has 16k bytes. The H8/326 has 8k bytes. The on-chip ROM is connected to the CPU via a 16-bit data bus. Both byte data and word data are accessed in two states, enabling rapid data transfer and instruction fetching.

  • Page 237: Block Diagram

    11.1.1 Block Diagram Figure 11-1 is a block diagram of the on-chip ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'0000 H'0001 H'0002 H'0003 On-chip ROM H'7FFE H'7FFF Even addresses Odd addresses Figure 11-1. Block Diagram of On-Chip ROM (H8/329) 11.2 PROM Mode (H8/329, H8/327) 11.2.1 PROM Mode Setup In the PROM mode of the PROM version of the H8/329 and H8/327, the usual microcomputer...

  • Page 238: Socket Adapter Pin Assignments And Memory Map

    11.2.2 Socket Adapter Pin Assignments and Memory Map The H8/329 and H8/327 can be programmed with a general-purpose PROM writer. Since the package has more than 32 pins, a socket adapter is necessary. Table 11-3 lists recommended socket adapters. Figure 11-2 shows the socket adapter pin assignments by giving the correspondence between H8/329 or H8/327 pins and HN27C256 pin functions.
  • Page 239 H8/329 or H8/327 EPROM Socket DC-64S HN27C256 (28 pins) CP-68 FP-64A DP-64S STBY Program voltage (12.5 V) — — EO to EO : Data input/output — — to EA : Address input — — Output enable — — Chip enable Note: All pins not listed in this figure should be left open.
  • Page 240 Address in MCU mode Address in PROM mode H'0000 H'0000 On-chip PROM H'7FFF H'7FFF Figure 11-3. Memory Map of H8/329 in PROM Mode Address in MCU mode Address in PROM mode H'0000 H'0000 On-chip PROM H'3FFF H'3FFF Note: If this area is read in PROM mode, “1”...

  • Page 241: Programming

    11.3 Programming The write, verify, and other sub-modes of the PROM mode are selected as shown in table 11-4. Table 11-4. Selection of Sub-Modes in PROM Mode Sub-Mode to EO to EA Write High Data input Address input Verify High Data output Address input Programming...
  • Page 242 START Set program/verify mode = 6.0V ±0.25V, V = 12.5V ±0.3V Address = 0 n = 0 n + 1 → n Write time t = 1 ms ±5% n < 25? Verify OK? Write t = 3n ms Address + 1 → Address Last address? Set read mode = 5.0V ±0.5V, V...
  • Page 243 Table 11-5. DC Characteristics (when V = 6.0V ±0.25V, V = 12.5V ±0.3V, V = 0V, Ta = 25˚C ±5˚C) Measurement Item Symbol Min Unit conditions Input High voltage – EO — + 0.3 V – EA OE, CE Input Low voltage –...
  • Page 244 Table 11-6. AC Characteristics (cont.) (when V = 6.0V ±0.25V, V = 12.5V ±0.3V, Ta = 25˚C ±5˚C) Measurement Item Symbol Unit conditions OE pulse width for 2.85 — 78.75 See figure 11-6* overwrite-programming setup time — — µs Data output delay time —...

  • Page 245: Notes On Writing

    Caution: Applied voltages in excess of the specified values can permanently destroy the chip. Be particularly careful about the PROM writer’s overshoot characteristics. If the PROM writer is set to Hitachi HN27256 or HN27C256 specifications, or to Intel specifications, V will be 12.5V.

  • Page 246: Erasing Of Data

    PROM writer and socket adapter for defects, using a microcomputer chip with a windowed package and on-chip EPROM. Please inform Hitachi of any abnormal conditions noted during programming or in screening of program data after high-temperature baking. 11.3.4 Erasing of Data The windowed package enables data to be erased by illuminating the window with ultraviolet light.

  • Page 247: Handling Of Windowed Packages

    11.4 Handling of Windowed Packages (1) Glass Erasing Window: Rubbing the glass erasing window of a windowed package with a plastic material or touching it with an electrically charged object can create a static charge on the window surface which may cause the chip to malfunction. If the erasing window becomes charged, the charge can be neutralized by a short exposure to ultraviolet light.

  • Page 248: Section 12. Power-Down State

    Section 12. Power-Down State 12.1 Overview The H8/329 Series has a power-down state that greatly reduces power consumption by stopping some or all of the chip functions. The power-down state includes three modes: (1) Sleep mode – a software-triggered mode in which the CPU halts but the rest of the chip remains active (2) Software standby mode –...

  • Page 249: System Control Register: Power-Down Control Bits

    12.2 System Control Register: Power-Down Control Bits Bits 7 to 4 of the system control register (SYSCR) concern the power-down state. Specifically, they concern the software standby mode. Table 12-2 lists the attributes of the system control register. Table 12-2. System Control Register Name Abbreviation Initial value Address...
  • Page 250 Bit 6 Bit 5 Bit 4 STS2 STS1 STS0 Description Settling time = 8192 states (Initial value) Settling time = 16384 states Settling time = 32768 states Settling time = 65536 states — — Settling time = 131072 states When the on-chip clock generator is used, the STS bits should be set to allow a settling time of at least 10ms.

  • Page 251: Sleep Mode

    12.3 Sleep Mode The sleep mode provides an effective way to conserve power while the CPU is waiting for an external interrupt or an interrupt from an on-chip supporting module. 12.3.1 Transition to Sleep Mode When the SSBY bit in the system control register is cleared to “0,” execution of the SLEEP instruction causes a transition from the program execution state to the sleep mode.

  • Page 252: Transition To Software Standby Mode

    12.4 Software Standby Mode In the software standby mode, the system clock stops and chip functions halt, including both CPU functions and the functions of the on-chip supporting modules. Power consumption is reduced to an extremely low level. The on-chip supporting modules and their registers are reset to their initial states, but as long as a minimum necessary voltage supply is maintained (at least 2V), the contents of the CPU registers and on-chip RAM remain unchanged.

  • Page 253: Application Note

    12.4.3 Sample Application of Software Standby Mode In this example the chip enters the software standby mode when NMI goes Low and exits when NMI goes High, as shown in figure 12-1. The NMI edge bit (NMIEG) in the system control register is originally cleared to “0,” selecting the falling edge.

  • Page 254: Hardware Standby Mode

    12.5 Hardware Standby Mode 12.5.1 Transition to Hardware Standby Mode Regardless of its current state, the chip enters the hardware standby mode whenever the STBY pin goes Low. The hardware standby mode reduces power consumption drastically by halting the CPU, stopping all the functions of the on-chip supporting modules, and placing I/O ports in the high-impedance state.

  • Page 255: Timing Relationships

    12.5.3 Timing Relationships Figure 12-2 shows the timing relationships in the hardware standby mode. In the sequence shown, first RES goes Low, then STBY goes Low, at which point the chip enters the hardware standby mode. To recover, first STBY goes High, then after the clock settling time, RES goes High.

  • Page 256: Section 13. Clock Pulse Generator

    Section 13. Clock Pulse Generator 13.1 Overview The H8/329 Series has a built-in clock pulse generator (CPG) consisting of an oscillator circuit, a system (Ø) clock divider, and a prescaler. The prescaler generates clock signals for the on-chip supporting modules.
  • Page 257 EXTAL XTAL = 10 to 22pF Figure 13-2. Connection of Crystal Oscillator (Example) Crystal Oscillator: Figure 15-3 shows an equivalent circuit of the external crystal. The external crystal should have the characteristics listed in table 13-1. Table 13-1. External Crystal Parameters Frequency (MHz) Rs max (Ω) (pF)
  • Page 258 Not allowed Signal A Signal B H8/327 XTAL EXTAL Figure 13-4. Notes on Board Design around External Crystal (2) Input of External Clock Signal Circuit Configuration: An external clock signal can be input as shown in the examples in figure 13-5. In example (b), the external clock should be held high during standby. EXTAL External clock input XTAL...

  • Page 259: System Clock Divider

    External Clock Input Frequency Double the system clock (Ø) frequency Duty factor 45% to 55% 13.3 System Clock Divider The system clock divider divides the crystal oscillator or external clock frequency by 2 to create the system clock (Ø).

  • Page 260: Section 14. Electrical Specifications

    14.2 Electrical Characteristics 14.2.1 DC Characteristics Table 14-2 lists the DC characteristics of the 5V versions of the H8/329 Series. Table 14-3 lists the DC characteristics of the 3V versions. Table 14-4 gives the allowable current output values of the...
  • Page 261 Table 14-2. DC Characteristics (5V Versions) Conditions: V = 5.0V ±10%, AV = 5.0V ±10%*, V = AV = 0V, Ta = –20 to 75˚C (regular specifications), Ta = –40 to 85˚C (wide-range specifications) Measurement Item Symbol Typ Max Unit conditions Schmitt trigger –...
  • Page 262 Table 14-2. DC Characteristics (5V Versions) (cont.) Conditions: V = 5.0V ±10%, AV = 5.0V ±10% = AV = 0V, Ta = –20 to 75˚C (regular specifications), Ta = –40 to 85˚C (wide-range specifications) Measurement Item Symbol Unit conditions Input capacitance –...
  • Page 263 Table 14-3. DC Characteristics (3V Versions) Conditions: V = 3.0V ±10%, AV = 5.0V ±10% = AV = 0V, Ta = –20 to 75˚C Measurement Item Symbol Unit conditions × 0.15 – T – Schmitt – P6 , P6 – ×...
  • Page 264 Table 14.3. DC Characteristics (3V Versions) (cont.) Conditions: V = 3.0V ±10%, AV = 5.0V ±10% = AV = 0V, Ta = –20 to 70˚C Measurement Item Symbol Unit conditions Input – – = 0V capacitance – – f = 1MHz All input pins –...
  • Page 265 Table 14-4. Allowable Output Current Values (5V Versions) Conditions: V = 5.0V ±10%, AV = 5.0V ±10%, V = AV = 0V, Ta = –20 to 75˚C (regular specifications), Ta = –40 to 85˚C (wide-range specifications) Item Symbol Unit Allowable output Low Ports 1 and 2 –...

  • Page 266: Ac Characteristics

    Figure 14-2. Example of Circuit for Driving an LED (5V Versions) 14.2.2 AC Characteristics The AC characteristics of the H8/329 Series are listed in three tables. Bus timing parameters are given in table 14-6, control signal timing parameters in table 14-7, and timing parameters of the on-...
  • Page 267 Table 14-6. Bus Timing Condition A: V = 5.0V ±10%, V = 0V, Ø = 0.5MHz to maximum operating frequency, Ta = –20 to 75˚C (regular specifications), Ta = –40 to 85˚C (wide-range specifications) Condition B: V = 3.0V ±10%, V = 0V, Ø...
  • Page 268 Table 14-7. Control Signal Timing Condition A: V = 5.0V ±10%, V = 0V, Ø = 0.5MHz to maximum operating frequency, Ta = –20 to 75˚C (regular specifications), Ta = –40 to 85˚C (wide-range specifications) Condition B: V = 3.0V ±10%, V = 0V, Ø...
  • Page 269 Table 14-8. Timing Conditions of On-Chip Supporting Modules Condition A: V = 5.0V ±10%, V = 0V, Ø = 0.5MHz to maximum operating frequency, Ta = –20 to 75˚C (regular specifications), Ta = –40 to 85˚C (wide-range specifications) Condition B: V = 3.0V ±10%, V = 0V, Ø...

  • Page 270: A/D Converter Characteristics

    • Measurement Conditions for AC Characteristics output pin 90 pF: Ports 1 – 4, 6 30 pF: Port 5 2.4 kΩ 12 kΩ Input/output timing reference levels Low: 0.8 V High: 2.0 V Figure 14-3. Output Load Circuit 14.2.3 A/D Converter Characteristics Table 14-9 lists the characteristics of the on-chip A/D converter.

  • Page 271: Mcu Operational Timing

    14.3 MCU Operational Timing This section provides the following timing charts: 14.3.1 Bus Timing Figures 14-4 to 14-5 14.3.2 Control Signal Timing Figures 14-6 to 14-9 14.3.3 16-Bit Free-Running Timer Timing Figures 14-10 to 14-11 14.3.4 8-Bit Timer Timing Figures 14-12 to 14-14 14.3.5 SCI Timing Figures 14-15 to 14-16 14.3.6 I/O Port Timing...

  • Page 272: Control Signal Timing

    (2) Basic Bus Cycle (with 1 Wait State) in Expanded Modes Ø to A AS, RD to D (Read) to D (Write) WAIT Figure 14-5. Basic Bus Cycle (with 1 Wait State) in Expanded Modes (Modes 1 and 2) 14.3.2 Control Signal Timing (1) Reset Input Timing Ø...
  • Page 273 (2) Interrupt Input Timing Ø NMIS NMIH (Edge) NMIS (Level) NMIW Note: i = 0 to 2; IRQ : IRQ when edge-sensed; IRQ : IRQ when level-sensed Figure 14-7. Interrupt Input Timing...
  • Page 274 Ø STBY OSC1 OSC1 Figure 14-8. Clock Setting Timing...

  • Page 275: 16-Bit Free-Running Timer Timing

    (4) Clock Settling Timing for Recovery from Software Standby Mode Ø OSC2 (i = 0, 1, 2) Figure 14-9. Clock Settling Timing for Recovery from Software Standby Mode 14.3.3 16-Bit Free-Running Timer Timing (1) Free-Running Timer Input/Output Timing Ø Free-running Compare-match timer counter FTOD...

  • Page 276: 8-Bit Timer Timing

    (2) External Clock Input Timing for Free-Running Timer Ø FTCS FTCI FTCWL FTCWH Figure 14-11. External Clock Input Timing for Free-Running Timer 14.3.4 8-Bit Timer Timing (1) 8-Bit Timer Output Timing Ø Timer Compare-match counter TMOD Figure 14-12. 8-Bit Timer Output Timing (2) 8-Bit Timer Clock Input Timing Ø...

  • Page 277: Serial Communication Interface Timing

    (3) 8-Bit Timer Reset Input Timing Ø TMRS TMRI TMRI Timer H'00 counter Figure 14-14. 8-Bit Timer Reset Input Timing 14.3.5 Serial Communication Interface Timing (1) SCI Input/Output Timing Scyc Serial clock (SCK) Transmit data (TxD) Receive data (RxD) Figure 14-15. SCI Input/Output Timing (Synchronous Mode)

  • Page 278: I/O Port Timing

    (2) SCI Input Clock Timing SCKW Scyc Figure 14-16. SCI Input Clock Timing 14.3.6 I/O Port Timing Ø Port 1 (Input) Port 7 Port 1 (Output) Port 6 Note: * Except P4 Figure 14-17. I/O Port Input/Output Timing...

  • Page 280: Appendix A. Cpu Instruction Set

    Appendix A. CPU Instruction Set A.1 Instruction Set List Operation Notation Rd8/16 General register (destination) (8 or 16 bits) Rs8/16 General register (source) (8 or 16 bits) Rn8/16 General register (8 or 16 bits) Condition code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR...
  • Page 281 W SP–2 → SP ◊ ◊ 0 PUSH Rs – – – 6 Rs16 → @SP MOVFPE @aa:16,Rd Not supported by the H8/329 Series. MOVTPE Rs,@aa:16 Not supported by the H8/329 Series. – √ EEPMOV – if R4L≠0 then – –...
  • Page 282 Table A-1. Instruction Set (cont.) Addressing mode/ instruction length Mnemonic Operation Condition code H N Z V C Rd8+#xx:8 → Rd8 ◊ ◊ ◊ ◊ ◊ ADD.B #xx:8,Rd – Rd8+Rs8 → Rd8 ◊ ◊ ◊ ◊ ◊ ADD.B Rs,Rd – W Rd16+Rs16 →...
  • Page 283 Table A-1. Instruction Set (cont.) Addressing mode/ instruction length Mnemonic Operation Condition code H N Z V C – ◊ ◊ ◊ ◊ SHAL.B Rd – – ◊ ◊ ◊ SHAR.B Rd – – ◊ ◊ ◊ SHLL.B Rd – ◊...
  • Page 284 Table A-1. Instruction Set (cont.) Addressing mode/ instruction length Mnemonic Operation Condition code H N Z V C (Rn8 of Rd8) ← (Rn8 of Rd8) BNOT Rn,Rd – – – – – – ← BNOT Rn,@Rd – – – – –...
  • Page 285 Table A-1. Instruction Set (cont.) Addressing mode/ instruction length Mnemonic Operation Condition code Branching condition H N Z V C C∨(#xx:3 of @Rd16) → C ◊ BIOR #xx:3,@Rd – – – – – C∨(#xx:3 of @aa:8) → C ◊ BIOR #xx:3, @aa:8 –...
  • Page 286 Set to “1” if decimal adjustment produces a carry; otherwise cleared to “0.” The number of states required for execution is 4n+8 (n = value of R4L) ∞ These instructions are not supported by the H8/329 Series. ± Set to “1” if the divisor is negative; otherwise cleared to “0.”...

  • Page 287: Operation Code Map

    A.2 Operation Code Map Table A-2 is a map of the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Some pairs of instructions have identical first bytes. These instructions are differentiated by the first bit of the second byte (bit 7 of the first instruction word).
  • Page 288 ADDS SLEEP XORC ANDC ADDX SHLL SHLR ROTXL ROTXR SUBS SUBX SHAL SHAR ROTL ROTR MULXU DIVXU BIST BNOT BTST BSET BCLR BXOR BAND Bit manipulation instruction EEPMOV BIOR BIXOR BIAND BILD ADDX SUBX...

  • Page 289: Number Of States Required For Execution

    A.3 Number of States Required for Execution The tables below can be used to calculate the number of states required for instruction execution. Table A-3 indicates the number of states required for each cycle (instruction fetch, branch address read, stack operation, byte data access, word data access, internal operation). Table A-4 indicates the number of cycles of each type occurring in each instruction.
  • Page 290 Table A-4. Number of Cycles in Each Instruction Instruction Branch Stack Byte data Word data Internal fetch addr. read operation access access operation Instruction Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDS.W #1/2, Rd ADDS ADDX ADDX.B #xx:8, Rd ADDX.B Rs, Rd AND.B #xx:8, Rd AND.B Rs, Rd...
  • Page 291 Table A-4. Number of Cycles in Each Instruction (cont.) Instruction Branch Stack Byte data Word data Internal fetch addr. read operation access access operation Instruction Mnemonic BIAND #xx:3, Rd BIAND BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 BILD #xx:3, Rd BILD BILD #xx:3, @Rd BILD #xx:3, @aa:8 BIOR #xx:3 Rd...
  • Page 292 Table A-4. Number of Cycles in Each Instruction (cont.) Instruction Branch Stack Byte data Word data Internal fetch addr. read operation access access operation Instruction Mnemonic BSR d:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BTST #xx:3, Rd BTST BTST #xx:3, @Rd BTST #xx:3, @aa:8...
  • Page 293 Table A-4. Number of Cycles in Each Instruction (cont.) Instruction Branch Stack Byte data Word data Internal fetch addr. read operation access access operation Instruction Mnemonic MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, Rd) MOV.B Rs, @–Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16...
  • Page 294 Table A-4. Number of Cycles in Each Instruction (cont.) Instruction Branch Stack Byte data Word data Internal fetch addr. read operation access access operation Instruction Mnemonic SHAL.B Rd SHAL SHAR.B Rd SHAR SHLL SHLL.B Rd SHLR.B Rd SHLR SLEEP SLEEP STC CCR, Rd SUB.B Rs, Rd SUB.W Rs, Rd...

  • Page 295: Appendix B. Register Field

    Appendix B. Register Field B.1 Register Addresses and Bit Names Addr. (last Register Bit names byte) name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'80 External H'81 addresses H'82 H'83 expanded H'84 modes)
  • Page 296 (Continued from previous page) Addr. (last Register Bit names byte) name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'A0 — — — — — — — — — H'A1 — —...
  • Page 297 (Continued from preceding page) Addr. (last Register Bit names byte) name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'C0 — — — — — — — — — — H'C1 —...
  • Page 298 (Continued from preceding page) Addr. (last Register Bit names byte) name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'E0 ADDRA H'E1 — — — — — — — — — H'E2 ADDRB H'E3...

  • Page 299: Register Descriptions

    B.2 Register Descriptions Register name Address onto which register is mapped Abbreviation of register name TIER—Timer Interrupt Enable Register H'FF90 Name of on-chip Bit No. supporting module ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE — Initial value Initial value Bit names (abbreviations). Read/Write —...
  • Page 300 TIER—Timer Interrupt Enable Register H'FF90 ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE — Initial value Read/Write — Overflow Interrupt Enable 0 Overflow interrupt request is disabled. 1 Overflow interrupt request is enabled. Output Compare Interrupt B Enable 0 Output compare interrupt request B is disabled. 1 Output compare interrupt request B is enabled.
  • Page 301 TCSR—Timer Control/Status Register H'FF91 ICFA ICFB ICFC ICFD OCFA OCFB CCLRA Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Counter Clear A 0 FRC count is not cleared. 1 FRC count is cleared by compare-match A. Timer Overflow Flag 0 Cleared when CPU reads OVF = “1,”...
  • Page 302 FRC (H and L)—Free-Running Counter H'FF92, H'FF93 Initial value Read/Write Count value OCRA (H and L)—Output Compare Register A H'FF94, H'FF95 Initial value Read/Write Continually compared with FRC. OCFA is set to “1” when OCRA = FRC. OCRB (H and L)—Output Compare Register B H'FF94, H'FF95 Initial value Read/Write...
  • Page 303 TCR—Timer Control Register H'FF96 IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0 Initial value Read/Write Clock Select 0 0 Internal clock source: Ø/2 0 1 Internal clock source: Ø/8 1 0 Internal clock source: Ø/32 1 1 External clock source: counted on rising edge Buffer Enable B 0 ICRD is used for input capture D.
  • Page 304 TOCR—Timer Output Compare Control Register H'FF97 — — — OCRS OLVLA OLVLB Initial value Read/Write — — — Output Level B 0 Compare-match B causes “0” output. 1 Compare-match B causes “1” output. Output Level A 0 Compare-match A causes “0” output. 1 Compare-match A causes “1”...
  • Page 305 ICRB (H and L)—Input Capture Register B H'FF9A, H'FF9B Initial value Read/Write Contains FRC count captured on FTIB input. ICRC (H and L)—Input Capture Register C H'FF9C, H'FF9D Initial value Read/Write Contains FRC count captured on FTIC input, or old ICRA value in buffer mode. ICRD (H and L)—Input Capture Register D H'FF9E, H'FF9F Initial value...
  • Page 306 P1PCR—Port 1 Input Pull-Up Control Register H'FFAC Port 1 PCR P1 PCR P1 PCR P1 PCR P1 PCR P1 PCR P1 PCR P1 Initial value Read/Write Port 1 Input Pull-Up Control 0 Input pull-up transistor is off. 1 Input pull-up transistor is on. P2PCR—Port 2 Input Pull-Up Control Register H'FFAD Port 2...
  • Page 307 P1DDR—Port 1 Data Direction Register H'FFB0 Port 1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 Mode 1 Initial value Read/Write — — — — — — — — Modes 2 and 3 Initial value Read/Write Port 1 Input/Output Control 0 Input port 1 Output port...
  • Page 308 P2DDR—Port 2 Data Direction Register H'FFB1 Port 2 DDR P2 DDR P2 DDR P2 DDR P2 DDR P2 DDR P2 DDR P2 Mode 1 Initial value Read/Write — — — — — — — — Modes 2 and 3 Initial value Read/Write Port 2 Input/Output Control 0 Input port...
  • Page 309 P3DR—Port 3 Data Register H'FFB6 Port 3 Initial value Read/Write P4DDR—Port 4 Data Direction Register H'FFB5 Port 4 DDR P4 DDR P4 DDR P4 DDR P4 DDR P4 DDR P4 DDR P4 Initial value Read/Write Port 4 Input/Output Control 0 Input port 1 Output port P4DR—Port 4 Data Register H'FFB7...
  • Page 310 P5DR—Port 5 Data Register H'FFBA Port 5 — — — — — Initial value Read/Write — — — — — P6DDR—Port 6 Data Direction Register H'FFB9 Port 6 DDR P6 DDR P6 DDR P6 DDR P6 DDR P6 DDR P6 DDR P6 Initial value Read/Write...
  • Page 311 STCR—Serial/Timer Control Register H'FFC3 TMR0/1 — — — — — ICKS1 ICKS0 Initial value Read/Write — — — — — Multiprocessor Enable 0 Multiprocessor communication function is disabled. 1 Multiprocessor communication function is enabled. Internal Clock Source Select See TCR under TMR0 and TMR1. SYSCR—System Control Register H'FFC4 System Control...
  • Page 312 MDCR—Mode Control Register H'FFC5 System Control — — — — — — MDS1 MDS0 Initial value Read/Write — — — — — — Mode Select Bits Value at mode pins. Note: * Determined by inputs at pins MD and MD ISCR—IRQ Sense Control Register H'FFC6 System Control...
  • Page 313 TCR—Timer Control Register H'FFC8 TMR0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value Read/Write Clock Select STCR CKS2 CKS1 CKS0 ICKS1 ICKS0 Description — — Timer stopped — Ø/8 internal clock, falling edge — Ø/2 internal clock, falling edge —...
  • Page 314 TCSR—Timer Control/Status Register H'FFC9 TMR0 CMFB CMFA — Initial value Read/Write R/(W) R/(W) R/(W) — Output Select 0 0 No change on compare-match A. 0 1 Output “0” on compare-match A. 1 0 Output “1” on compare-match A. 1 1 Invert (toggle) output on compare-match A. Output Select 0 0 No change on compare-match B.
  • Page 315 TCORA—Time Constant Register A H'FFCA TMR0 Initial value Read/Write The CMFA bit is set to “1” when TCORA = TCNT. TCORB—Time Constant Register B H'FFCB TMR0 Initial value Read/Write The CMFB bit is set to “1” when TCORB = TCNT. TCNT—Timer Counter H'FFCC TMR0...
  • Page 316 TCR—Timer Conrol Register H'FFD0 TMR1 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value Read/Write Clock Select STCR CKS2 CKS1 CKS0 ICKS1 ICKS0 Description — — Timer stopped — Ø/8 internal clock, falling edge — Ø/2 internal clock, falling edge —...
  • Page 317 TCSR—Timer Control/Status Register H'FFD1 TMR1 CMFB CMFA — Initial value Read/Write R/(W) R/(W) R/(W) — Notes: Bit functions are the same as for TMR0. *1 Software can write a “0” in bits 7 to 5 to clear the flags, but cannot write a “1” in these bits.
  • Page 318 SMR—Serial Mode Register H'FFD8 STOP CKS1 CKS0 Initial value Read/Write Clock Select Ø clock Ø/4 clock Ø/16 clock Ø/64 clock Multiprocessor Mode Multiprocessor function disabled Multiprocessor format selected Stop Bit Length One stop bit Two stop bits Parity Mode Even parity Odd parity Parity Enable Transmit: No parity bit added.
  • Page 319 BRR—Bit Rate Register H'FFD9 Initial value Read/Write Constant that determines the bit rate...
  • Page 320 SCR—Serial Control Register H'FFDA MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock Enable 0 Serial clock not output Serial clock output at SCK pin Clock Enable 1 Internal clock External clock Transmit End Interrupt Enable TSR-empty interrupt request is disabled. TSR-empty interrupt request is enabled.
  • Page 321 TDR—Transmit Data Register H’FFDB Initial value Read/Write Transmit data...
  • Page 322 SSR—Serial Status Register H'FFDC TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Multiprocessor Bit Transfer 0 Multiprocessor bit = “0” in transmit data. 1 Multiprocessor bit = “1” in transmit data. Multiprocessor Bit 0 Multiprocessor bit = “0” in receive data. 1 Multiprocessor bit = “1”...
  • Page 323 RDR—Receive Data Register H'FFDD Initial value Read/Write Receive data ADDRn—A/D Data Register n (n = A, B, C, D) H'FFE0, H'FFE2, H'FFE4, H'FFE6 Initial value Read/Write A/D conversion result...
  • Page 324 ADCSR—A/D Control/Status Register H'FFE8 ADIE ADST SCAN Initial value Read/Write R/(W)* Channel Select CH2 CH1 CH0 Single mode Scan mode , AN to AN to AN , AN to AN to AN Clock Select 0 Conversion time = 242 states (max) 1 Conversion time = 122 states (max) Scan Mode 0 Single mode...
  • Page 325 ADCR—A/D Control Register H'FFEA TRGE — — — — — — Initial value Read/Write — — — — — — Channel Select Reserved bit. Trigger Enable 0 ADTRG is disabled. 1 ADTRG is enabled. A/D conversion can be started by external trigger, or by software.
  • Page 326 Appendix C. Pin States C.1 Pin States in Each Mode Table C-1. Pin States Hardware Software Sleep Normal name mode Reset standby standby mode operation – P1 3-State Prev. state – A – A 3-State Low if (Addr. Addr. output DDR = 1, output pins: or input port Prev.
  • Page 327 Table C-1. Pin States (cont.) Hardware Software Sleep Normal name mode Reset standby standby mode operation – P4 High 3-State High High AS, WR, AS, WR, RD 3-State Prev. state Prev. state I/O port – P4 3-State 3-State Prev. state Prev.
  • Page 328 Appendix D. Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit cleared to “0” in SYSCR, drive the RES signal low 10 system clock cycles before the STBY signal goes low, as shown below. RES must remain low until STBY goes low (minimum delay from STBY low to RES high: 0 ns).

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