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26.7.4
Register Description
Drum Phase Preset Data Registers (DPPR1, DPPR2)
DPPR1
Bit :
—
Initial value :
—
R/W :
DPPR2
Bit :
15
DPPR15
Initial value :
R/W :
W
Bit :
DPPR7
Initial value :
R/W :
W
The 20-bit preset data that defines the specified drum phase is set in DPPR1 and DPPR2. The 20
bits are weighted as follows: bit 3 of DPPR1 is the MSB, and bit 0 of DPPR2 is the LSB. When
data is written to DPPR2, the 20-bit preset data, including DPPR1, is loaded into the preset circuit.
Write to DPPR1 first, and DPPR2 next. The preset data can be calculated from the following
equation by using H'8000* as the reference value.
Target phase difference = (reference signal frequency/2) − 6.5H
Drum phase preset data = H'80000 - (φs/n × target phase difference)
φs:
Servo clock frequency in Hz (fosc/2)
φs/n:
Clock source of selected counter
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. No
read is valid. If a read is attempted, an undetermined value is read out. DPPR1 and DPPR2 are
initialized to H'F0 and H'0000 by a reset, and in standby mode.
Note: The preset data value is calculated so that the counter will reach H'80000 when the error
value is zero. When the counter value is latched as error data in the drum phase error data
registers (DPER1 and DPER2), however, it is converted to a value referenced to H'00000.
Rev. 1.0, 02/00, page 632 of 1141
7
6
—
—
1
1
—
—
14
13
DPPR14
DPPR13
0
0
W
W
7
6
DPPR6
DPPR5
0
0
W
W
5
4
—
DPPR19
1
1
—
W
12
11
DPPR12
DPPR11
0
0
W
W
5
4
DPPR4
DPPR3
0
0
W
W
3
2
DPPR18
DPPR17
0
0
W
10
DPPR10
DPPR9
0
0
W
3
2
DPPR2
DPPR1
0
0
W
1
0
DPPR16
0
0
W
W
9
8
DPPR8
0
0
W
W
1
0
DPPR0
0
0
W
W
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