Capstan Speed Error Detector; Overview - Hitachi H8S/2199 Hardware Manual

26.8

Capstan Speed Error Detector

26.8.1

Overview

Capstan speed control holds the capstan motor at a constant revolution speed, by measuring the
period of the CFG signal. A digital counter detects the speed error against a preset value. The
speed error data is added to phase error data in a digital filter. This filter controls a pulse-width
modulated (PWM) output, which controls the revolution speed and phase of the capstan motor.
The CFG input signal is downloaded by the comparator circuit, then reshaped into a square wave
by a reshaping circuit, divided by the CFG divider, and sent to the speed error detector as the
DVCFG signal.
The speed error detector uses the system clock to measure the period of the DVCFG signal, and
detects the error against a preset data value. The preset data is the value that results from
measuring the DVCFG signal period with the clock signal when the capstan motor is running at
the correct speed.
The error detector operates by latching a counter value when it detects an edge of the DVCFG
signal. The latched count provides 16 bits of speed error data for the digital filter to operate on.
The digital filter adds the speed error data to phase error data from the capstan phase control
system, then sends the result to the PWM as capstan error data.
Rev. 1.0, 02/00, page 638 of 1141