Hitachi H8S/2199 Hardware Manual page 854

Bit 13    Interlaced/Noninterlaced Display Select Bit (LACEM): Selects interlaced or
noninterlaced text display mode. When noninterlaced text display is selected, the internally
generated Hsync and Vsync frequency can be modified. For details, refer to section 27.2.11,
Internal Sync Frequency Register (INFRQR).
Bit 13
LACEM Description
0 Noninterlaced display is selected
1 Interlaced display is selected
Bit 12    Blinking Period Select Bit (BLKS): Selects the character blinking period. The duty is
50%. The blinking period differs somewhat depending on the TV format selected by the TVM2 bit
of the OSD format register (either a 525-line system or a 625-line system).
DFORM DCNTL
Bit 15 Bit 12
TVM2 BLKS
0 0
1
1 0
1
Note: fv is the vertical sync signal frequency.
Bit 11    OSD Display Start Bit (OSDON): Starts OSD display. When the OSD display start bit
is 0, the OSD internal display circuit stops operation. In conjunction with the OSD C.Video
display enable bit (bit 15), changes operation as follows. When accessing character data ROM
(OSDROM) from the CPU, this bit should always be cleared to 0. If this bit is set to 1, access by
the CPU is not guaranteed.
Bit 15 Bit 11
CDSPON OSDON
0/1 0
0 1
1 1
Description (Blinking Period)
Approx. 0.5 sec (32/fv = 0.53 sec)
Approx. 1.0 sec (64/fv = 1.07 sec)
Approx. 0.5 sec (32/fv = 0.64 sec)
Approx. 1.0 sec (64/fv = 1.28 sec)
Description
OSD display is stopped (C.Video output and digital output both off)
OSD display is started (digital output only)
OSD display is started (both C.Video output and digital output
enabled)
Rev. 1.0, 02/00, page 851 of 1141
(Initial value)
(Initial value)
(Initial value)
(Initial value)