Hitachi H8S/2199 Hardware Manual page 686

Bit 3    High Impedance (HiZ): Set to 1 when the intermediate level is generated by an external
circuit.
Bit 3
HiZ Description
0 Vpulse is a three-level output pin
1 Vpulse is a three-state output pin (high, low, or high-impedance)
Bits 2 to 0    Additional V Output Control (CUT, VPON, POL): These bits control the output
at the additional V pin.
Bit 2 Bit 1
CUT VPON
0 0
1
1 *
Note: * Don't care.
Rev. 1.0, 02/00, page 680 of 1141
Bit 0
POL Description
* Low level
0 Negative polarity (see figure 26.46)
1 Positive polarity (see figure 26.45)
0 Intermediate level (high impedance if HiZ bit = 1)
1 High level
(Initial value)
(Initial value)