26.15.7 Activation Of The Sync Signal Detector - Hitachi H8S/2199 Hardware Manual

Single-chip microcomputer
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26.15.7 Activation of the Sync Signal Detector

After release of reset or transition from the power down mode to the active mode, the sync signal
detector starts operation by a sync signal input after release of module stop. The pulse of the
polarity specified by the SYCT bit of the sync signal control register (SYNCR) is input to the
detector. The detector starts operation even if this pulse is a noise pulse with a width smaller than
the regular width. The minimum pulse width which can activate the detector is not constant
depending on the internal operation of the input circuit. Accordingly, if the assured activation of
the detector is required, input a pulse with a width greater than 4/φs (φs = fosc/2 (Hz)). In such a
case, care is required to noise, because even a pulse with a width smaller than 4φ/s may cause
activation.
Rev. 1.0, 02/00, page 747 of 1141

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