Register Configuration - Hitachi H8S/2199 Hardware Manual

23.1.4

Register Configuration

Table 23.2 summarizes the registers of the I
Table 23.2 Register Configuration
Channel Name
2
0 I C bus control register
2
I C bus status register
2
I C bus data register
2
I C bus mode register
Slave address register
Second slave address register
2
1 I C bus control register
2
I C bus status register
2
I C bus data register
2
I C bus mode register
Slave address register
Second slave address register
0 and 1 DDC switch register
Module stop control register
Notes: 1. Lower 16 bits of the address.
2. The registers that can be read from or written to depend on the ICE bit in the I
control register. The slave address registers can be accessed when ICE = 0, and the
2
I C bus mode registers can be accessed when ICE = 1.
Rev. 1.0, 02/00, page 462 of 1141
2
C bus interface.
Abbrev.
ICCR0
ICSR0
ICDR0
ICMR0
SAR0
SARX0
ICCR1
ICSR1
ICDR1
ICMR1
SAR1
SARX1
DDCSWR
MSTPCRH
MSTPCRL
R/W Initial Value
R/W H'01
R/W H'00

R/W
R/W H'00
R/W H'00
R/W H'01
R/W H'01
R/W H'00

R/W
R/W H'00
R/W H'00
R/W H'01
R/W H'0F
R/W H'FF
H'FF
*1
Address
H'D0E8
H'D0E9
2
H'D0EE*
2
H'D0EF*
2
H'D0EF*
2
H'D0EE*
H'D158
H'D159
2
H'D15E*
2
H'D15F*
2
H'D15F*
2
H'D15E*
H'D0E5
H'FFEC
H'FFED
2
C bus