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4.9
Subactive Mode
4.9.1
Subactive Mode
If a SLEEP instruction is executed in high-speed mode when the SSBY bit in SBYCR, the DTON
bit in LPWRCR, and the TMA3 bit in TMA (timer A) are all set to 1, the CPU will make a
transition to subactive mode. When an interrupt is generated in watch mode, if the LSON bit in
LPWRCR is set to 1, a transition is made to subactive mode. When an interrupt is generated in
subsleep mode, a transition is made to subactive mode.
In subactive mode, the CPU performs sequential program execution at low speed on the subclock.
In this mode, all on-chip supporting modules other than timer A stop.
4.9.2
Clearing Subactive Mode
Subsleep mode is cleared by a SLEEP instruction, or by means of the 5(6 pin.
Clearing with a SLEEP Instruction: When a SLEEP instruction is executed while the SSBY bit
in SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the TMA3 bit in TMA (timer
A) is set to 1, subactive mode is cleared and a transition is made to watch mode. When a SLEEP
instruction is executed while the SSBY bit in SBYCR is cleared to 0, the LSON bit in LPWRCR is
set to 1, and the TMA3 bit in TMA (timer A) is set to 1, a transition is made to subsleep mode.
When a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the DTON bit is
set to 1 and the LSON bit is cleared to 0 in LPWRCR, and the TMA3 bit in TMA (timer A) is set
to 1, a transition is made directly to high-speed or medium-speed mode.
For details of direct transition, see section 4.10, Direct Transition.
Clearing with the 5(6
5(6 Pin: See (2) Clearing with the 5(6 Pin in section 4.6.2, Clearing Standby
5(6
5(6
Mode.
Rev. 1.0, 02/00, page 85 of 1141
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