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A.5
Bus Status during Instruction Execution
Table A.13 indicates execution status of each instruction available in this LSI. For the number of
states required for each execution status, see table A.11, Number of States Required for Each
Execution Status (Cycle).
Interpreting the Table
Instruction
1
JMP@aa:24
R:W 2nd
R : B
R : W
W : B
W : W
: M
2nd
3rd
4th
5th
NEXT
EA
VEC
Rev. 1.0, 02/00, page 958 of 1141
2
3
Internal operation
R:W EA
1 state
Read by byte
Read by word
Write by byte
Write by word
Bus not transferred immediately after this cycle
Address of the 2nd word (3rd and 4th bytes)
Address of the 3rd word (5th and 6th bytes)
Address of the 4th word (7th and 8th bytes)
Address of the 5th word (9th and 10th bytes)
The head address of the instruction immediately after the instruction
currently being executed
Execution address
Vector address
Order of execution
4
5
End of instruction
Effective address is read by word.
Read/write not executed
The 2nd word of the instruction currently being
executed is read by word.
6
7
8
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