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13.2.8
Module Stop Control Register (MSTPCR)
Bit :
7
MSTP15
Initial value :
1
R/W
R/W :
The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode.
When the MSTP13 bit is set to 1, timer J stops its operation at the ending point of the bus cycle to
shift to the module stop mode. For more information, see section 4.5, Module Stop Mode.
When reset, the MSTPCR is initialized to H'FFFF.
Bit 5 Module Stop (MSTP13): This bit works to designate the module stop mode for the Timer
J.
MSTPCRH
Bit 5
MSTP13
Description
0
Cancels the module stop mode of timer J
1
Sets the module stop mode of timer J
MSTPCRH
6
5
4
3
MSTP14
MSTP13
MSTP12
MSTP11
MSTP10
1
1
1
1
R/W
R/W
R/W
R/W
2
1
0
7
MSTP9
MSTP8
MSTP7
MSTP6
1
1
1
1
R/W
R/W
R/W
R/W
R/W
MSTPCRL
6
5
4
3
2
MSTP5
MSTP4
MSTP3
MSTP2
1
1
1
1
1
R/W
R/W
R/W
R/W
Rev. 1.0, 02/00, page 273 of 1141
1
0
MSTP1
MSTP0
1
1
R/W
R/W
(Initial value)
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