Field Detection Window Register (Fwidr) - Hitachi H8S/2199 Hardware Manual

Single-chip microcomputer

Table of Contents

Digital H separation

(V sampling clock)

V complement and

mask counter

Figure 27.10 AFCV Generation Timing When V Complement Function Is Enabled

Field Detection Window Register (FWIDR)

Initial value :

The FWIDR is a 4-bit write-only register for specifying the field detection window timing in units

of 16 × fh (fh: horizontal sync signal frequency). The field detection window signal is reset to 0

when the AFC dividing counter value matches the FWIDR value, and the signal is again set to 1

when 1/2 the Hsync signal period has passed. At a rising edge of the AFCV signal while the field

detection window signal is 1, the field is determined as an odd one, and the field detection flag

(FLD) is set to 1. At a rising edge of the AFCV signal while the field detection window signal is 0,

the field is determined as an even one, and the FLD is cleared to 0. The value set to the FWIDR

depends on the setting of the V complement function control (VCMPON) bit (bit 4) of the

SEPCR. When the VCMPON is cleared to 0, that is, when the V complement function is not

operating, the FWIDR must be set so that the rising edge of the SEPV signal, which is generated

when the V separation counter value reaches the specified threshold value, comes to the center of

the field detection window period. When the VCMPON is set to 1, that is, when the V

complement function is operating, the FWIDR must be set so that the dividing counter overflow

timing comes to the center of the field detection window period. When reset, the FWIDR is

initialized to H'F0.

(1) Bit 0 of SEPACR Register

Rev. 1.0, 02/00, page 775 of 1141