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• Internal latches which holds the register read information to set or clear the flags in ICMR,
ICCR, ICSR, and DDCSWR
• Bit counter (BC2 to BC0) value in ICMR
• Sources of interrupts generated (interrupts that has been transferred to the interrupt
controller)
(2) Notes on Initialization
• Interrupt flags and interrupt sources are not cleared; clear them by software if necessary.
• Other register flags cannot be assumed to be cleared, either; clear them by software if
necessary.
• When initialization is specified by the DDCSWR settings, the data written to the CLR3 to
CLR0 bits are not held. When initializing the IIC, be sure to use the MOV instruction to
write to all the CLR3 to CLR0 bits at the same time; do not use bit manipulation
instructions such as BCLR. When reinitializing the module status, all the CLR3 to CLR0
bits must be rewritten to at the same time.
• If a flag is cleared during transfer, the IIC module stops transfer immediately, and releases
the control of the SCL and SDA pins. Before starting again, set the registers to appropriate
values to make a correct communication if necessary.
This module initializing function does not modify the BBSY bit value, but in some cases,
depending on the SCL and SDA pin status and the release timing, the signal waveforms at the
SCL and SDA pins may indicate the stop condition, and accordingly the BBSY bit may be
cleared. Other bits or flags may be affected in the same way by module initialization.
To avoid these problems, take the following procedure to initialize the IIC:
1. Initialize the IIC by setting the CLR3 to CLR0 bits or the ICE bit.
2. Execute a stop condition issuing instruction to clear the BBSY bit to 0 (writing 0 to BBSY and
SCP), and wait for two cycles of the transfer clock.
3. Initialize the IIC again by setting the CLR3 to CLR0 bits or the ICE bit.
4. Set the registers in IIC to appropriate values.
Rev. 1.0, 02/00, page 508 of 1141
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