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Hitachi H8S/2378, H8S/2378R Series Hardware Manual

16 bit single-chip microcomputer
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Hitachi 16 Bit Single-Chip Microcomputer
H8S/2378, H8S/2378R Series
ADE-602-260
Rev. 1.0
9/25/01
Hitachi, Ltd.
H8S/2377R F-ZTAT™
HD64F2377R
H8S/2376R F-ZTAT™
HD64F2376R
H8S/2377 F-ZTAT™
HD64F2377
H8S/2376 F-ZTAT™
HD64F2376
Hardware Manual

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  Summary of Contents for Hitachi H8S/2378, H8S/2378R Series

  • Page 1 Hitachi 16 Bit Single-Chip Microcomputer H8S/2378, H8S/2378R Series H8S/2377R F-ZTAT™ HD64F2377R H8S/2376R F-ZTAT™ HD64F2376R H8S/2377 F-ZTAT™ HD64F2377 H8S/2376 F-ZTAT™ HD64F2376 Hardware Manual ADE-602-260 Rev. 1.0 9/25/01 Hitachi, Ltd.
  • Page 2 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
  • Page 3 General Precautions on the Handling of Products 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are not connected to any of the internal circuitry; they are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
  • Page 4 Configuration of this Manual This manual comprises the following items: 1. Precautions in Relation to this Product 2. Configuration of this Manual 3. Overview 4. Table of Contents 5. Summary 6. Description of Functional Modules • CPU and System-Control Modules •...
  • Page 5 This is particularly applicable to application devices with specifications that will most probably change. Note: * F-ZTAT is a trademark of Hitachi, Ltd. Target Users: This manual was written for users who will be using the H8S/2378 Series in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers.
  • Page 6 ADE No. H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor ADE-702-247 User's Manual H8S, H8/300 Series Simulator/Debugger User’s Manual ADE-702-037 H8S, H8/300 Series Hitachi Embedded Workshop, Hitachi Debugging ADE-702-231 Interface Tutorial Hitachi Embedded Workshop User's Manual ADE-702-201 Application note: Manual Title ADE No.
  • Page 7: Table Of Contents

    Contents Section 1 Overview................... 1 Features ..........................1 Block Diagram ........................2 Pin Description........................3 1.3.1 Pin Arrangement ....................3 1.3.2 Pin Arrangement in Each Operating Mode ............4 1.3.3 Pin Functions......................10 Section 2 CPU....................17 Features ..........................17 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ........18 2.1.2 Differences from H8/300 CPU................19 2.1.3...
  • Page 8 Processing States.......................50 Usage Notes ........................51 2.9.1 Note on Bit Manipulation Instructions..............51 Section 3 MCU Operating Modes ..............53 Operating Mode Selection....................53 Register Descriptions ......................54 3.2.1 Mode Control Register (MDCR) .................54 3.2.2 System Control Register (SYSCR) ..............54 Operating Mode Descriptions ...................56 3.3.1 Mode 1 .........................56 3.3.2 Mode 2 .........................56...
  • Page 9 5.3.7 Software Standby Release IRQ Enable Register (SSIER) ........88 Interrupt Sources .......................88 5.4.1 External Interrupts....................88 5.4.2 Internal Interrupts....................89 Interrupt Exception Handling Vector Table ..............90 Interrupt Control Modes and Interrupt Operation .............95 5.6.1 Interrupt Control Mode 0 ..................95 5.6.2 Interrupt Control Mode 2 ..................97 5.6.3 Interrupt Exception Handling Sequence ..............98 5.6.4...
  • Page 10 6.5.2 Valid Strobes......................143 6.5.3 Basic Timing ......................143 6.5.4 Wait Control......................150 Read Strobe ( RD ) Timing ..................153 6.5.5 Extension of Chip Select ( CS ) Assertion Period..........154 6.5.6 DRAM Interface .......................155 6.6.1 Setting DRAM Space...................155 6.6.2 Address Multiplexing...................156 6.6.3 Data Bus.......................157 6.6.4 Pins Used for DRAM Interface................158 6.6.5...
  • Page 11 6.10 Write Data Buffer Function....................230 6.11 Bus Release ........................231 6.11.1 Operation......................231 6.11.2 Pin States in External Bus Released State............233 6.11.3 Transition Timing ....................234 6.12 Bus Arbitration........................236 6.12.1 Operation......................236 6.12.2 Bus Transfer Timing ....................236 6.13 Bus Controller Operation in Reset ..................238 6.14 Usage Notes ........................238 6.14.1 External Bus Release Function and All-Module-Clocks-Stopped Mode .....238 6.14.2 External Bus Release Function and Software Standby ........238...
  • Page 12 7.5.12 Multi-Channel Operation ..................307 7.5.13 Relation between DMAC and External Bus Requests, Refresh Cycles, and EXDMAC .....................308 7.5.14 DMAC and NMI Interrupts..................309 7.5.15 Forced Termination of DMAC Operation............309 7.5.16 Clearing Full Address Mode ................310 Interrupt Sources .......................311 Usage Notes ........................312 7.7.1 DMAC Register Access during Operation............312 7.7.2...
  • Page 13 8.6.2 Module Stop State ....................376 EDREQ Pin Falling Edge Activation..............376 8.6.3 8.6.4 Activation Source Acceptance ................376 8.6.5 Enabling Interrupt Requests when IRF = 1 in EDMDR........377 ETEND Pin and CBR Refresh Cycle ..............377 8.6.6 Section 9 Data Transfer Controller (DTC) ............379 Features ..........................379 Register Configuration ......................380 9.2.1...
  • Page 14 10.1 Port 1..........................408 10.1.1 Port 1 Data Direction Register (P1DDR) .............408 10.1.2 Port 1 Data Register (P1DR)................408 10.1.3 Port 1 Register (PORT1)..................409 10.1.4 Pin Functions .......................409 10.2 Port 2..........................419 10.2.1 Port 2 Data Direction Register (P2DDR) .............419 10.2.2 Port 2 Data Register (P2DR)................419 10.2.3 Port 2 Register (PORT2)..................420 10.2.4 Pin Functions .......................421 10.3 Port 3..........................429...
  • Page 15 10.9.5 Port A Open Drain Control Register (PAODR) ...........456 10.9.6 Port Function Control Register 1 (PFCR1) ............456 10.9.7 Pin Functions......................458 10.9.8 Port A MOS Input Pull-Up States ................459 10.10 Port B ..........................460 10.10.1 Port B Data Direction Register (PBDDR)............460 10.10.2 Port B Data Register (PBDR)................461 10.10.3 Port B Register (PORTB)..................461 10.10.4 Port B MOS Pull-Up Control Register (PBPCR)..........462 10.10.5 Pin Functions......................462...
  • Page 16 10.16 Port H ..........................488 10.16.1 Port H Data Direction Register (PHDDR) ............488 10.16.2 Port H Data Register (PHDR) ................490 10.16.3 Port H Register (PORTH) ..................490 10.16.4 Pin Functions .......................491 Section 11 16-Bit Timer Pulse Unit (TPU) ............493 11.1 Features ..........................493 11.2 Input/Output Pins ......................497 11.3 Register Descriptions ......................498 11.3.1 Timer Control Register (TCR) ................499...
  • Page 17 11.10.10 Contention between Buffer Register Write and Input Capture ......568 11.10.11 Contention between Overflow/Underflow and Counter Clearing ....569 11.10.12 Contention between TCNT Write and Overflow/Underflow ......570 11.10.13 Multiplexing of I/O Pins ..................570 11.10.14 Interrupts and Module Stop Mode ..............570 Section 12 Programmable Pulse Generator (PPG) ........... 571 12.1 Features ..........................571 12.2 Input/Output Pins ......................573 12.3 Register Descriptions ......................573...
  • Page 18 13.5.3 Timing of Timer Output when Compare-Match Occurs........601 13.5.4 Timing of Compare Match Clear .................602 13.5.5 Timing of TCNT External Reset................602 13.5.6 Timing of Overflow Flag (OVF) Setting .............603 13.6 Operation with Cascaded Connection ................603 13.6.1 16-Bit Counter Mode ...................603 13.6.2 Compare Match Count Mode................604 13.7 Interrupts ...........................604 13.7.1 Interrupt Sources and DTC Activation..............604...
  • Page 19 15.3.2 Receive Data Register (RDR) ................630 15.3.3 Transmit Data Register (TDR) ................630 15.3.4 Transmit Shift Register (TSR) ................630 15.3.5 Serial Mode Register (SMR)................630 15.3.6 Serial Control Register (SCR)................633 15.3.7 Serial Status Register (SSR).................638 15.3.8 Smart Card Mode Register (SCMR) ..............645 15.3.9 Bit Rate Register (BRR)..................646 15.3.10 IrDA Control Register (IrCR) ................655 15.3.11 Serial Extension Mode Register (SEMR) ............656...
  • Page 20 15.10.2 Break Detection and Processing................701 15.10.3 Mark State and Break Sending................701 15.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)..............701 15.10.5 Relation between Writes to TDR and the TDRE Flag .........701 15.10.6 Restrictions on Use of DMAC or DTC ..............702 15.10.7 Operation in Case of Mode Transition..............702 Section 16 I C Bus Interface2 (IIC2) (Option) ............707...
  • Page 21 17.4.4 External Trigger Input Timing ................746 17.5 Interrupts ...........................747 17.6 A/D Conversion Precision Definitions................747 17.7 Usage Notes ........................749 17.7.1 Module Stop Mode Setting ..................749 17.7.2 Permissible Signal Source Impedance ..............749 17.7.3 Influences on Absolute Precision.................749 17.7.4 Setting Range of Analog Power Supply and Other Pins ........750 17.7.5 Notes on Board Design ..................750 17.7.6 Notes on Noise Countermeasures ................750 Section 18 D/A Converter.................
  • Page 22 20.9 Program/Erase Protection....................788 20.9.1 Hardware Protection ....................788 20.9.2 Software Protection....................788 20.9.3 Error Protection....................788 20.10 Programmer Mode ......................789 20.11 Power-Down States for Flash Memory ................789 20.12 Usage Notes ........................789 Section 21 Clock Pulse Generator ..............793 21.1 Register Description......................793 21.1.1 System Clock Control Register (SCKCR) ............793 21.1.2 PLL Control Register (PLLCR) ................795 21.2 Oscillator...........................795 21.2.1 Connecting a Crystal Oscillator ................796...
  • Page 23 Section 23 List of Registers ................815 23.1 Register Addresses (Address Order) .................815 23.2 Register Bits ........................827 23.3 Register States in Each Operating Mode................841 Section 24 Electrical Characteristics ..............851 24.1 Absolute Maximum Ratings....................851 24.2 DC Characteristics......................852 24.3 AC Characteristics......................855 24.3.1 Clock Timing .......................856 24.3.2 Control Signal Timing ..................858 24.3.3 Bus Timing......................860...
  • Page 24 Rev. 1.0, 09/01, page xxiv of xliv...
  • Page 25: Overview

    Figures of Contents Section 2 Overview Figure 1.1 Internal Block Diagram ....................2 Figure 1.2 Pin Arrangement......................3 Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode) ..............21 Figure 2.2 Stack Structure in Normal Mode .................21 Figure 2.3 Exception Vector Table (Advanced Mode) ..............22 Figure 2.4 Stack Structure in Advanced Mode ................23 Figure 2.5 Memory Map .......................24 Figure 2.6 CPU Internal Registers ....................25...
  • Page 26 Figure 6.4 RAS Signal Assertion Timing (2-State Column Address Output Cycle, Full Access)..........128 Figure 6.5 CAS Latency Control Cycle Disable Timing during Continuous Synchronous DRAM Space Write Access (for CAS Latency 2) ....131 Figure 6.6 Area Divisions ......................136 Figure 6.7 CSn Signal Output Timing (n = 0 to 7) ..............141 Figure 6.8 Access Sizes and Data Alignment Control (8-Bit Access Space)......142 Figure 6.9 Access Sizes and Data Alignment Control (16-bit Access Space) ......142 Figure 6.10 Bus Timing for 8-Bit, 2-State Access Space ............144...
  • Page 27 Figure 6.41 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1 (RAST = 0, CAST = 0) ...................178 Figure 6.42 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0 (RAST = 0, CAST = 1) ....................179 Figure 6.43 Relationship between φ...
  • Page 28 Figure 6.72 Example of Synchronous DRAM Full Access after External Read (CAS Latency 2) ......................219 Figure 6.73 Example of Idle Cycle Operation in RAS Down Mode (Read in Different Area) (IDLC = 0, CAS Latency 2)..................220 Figure 6.74 Example of Idle Cycle Operation in RAS Down Mode (Read in Different Area) (IDLC = 1, CAS Latency 2)..................221 Figure 6.75 Example of Idle Cycle Operation in RAS Down Mode (Write after Read) (IDLC = 0, CAS Latency 2)..................222...
  • Page 29 Figure 7.16 Example of Block Transfer Mode Setting Procedure ..........291 Figure 7.17 Example of DMA Transfer Bus Timing ..............292 Figure 7.18 Example of Short Address Mode Transfer ..............293 Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal)...........294 Figure 7.20 Example of Full Address Mode Transfer (Burst Mode) ..........295 Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode)......296 Figure 7.22 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer ....297 Figure 7.23 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer ..298...
  • Page 30 Figure 8.16 Example of Normal Transfer Mode (Burst Mode) Transfer........350 Figure 8.17 Example of Block Transfer Mode (Cycle Steal Mode) Transfer......350 Figure 8.18 Example of Normal Mode Transfer Activated by EDREQ Pin Falling Edge ..351 Figure 8.19 Example of Block Transfer Mode Transfer Activated by EDREQ Pin Falling Edge ......................352 Figure 8.20 Example of Normal Mode Transfer Activated by EDREQ Pin Low Level.....353 Figure 8.21 Example of Block Transfer Mode Transfer Activated by EDREQ Pin Low Level.354...
  • Page 31 Figure 8.42 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Dual Address Mode/Low Level Sensing/BGUP = 1) .......369 Figure 8.43 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 1) ......370 Figure 8.44 External Request/Cycle Steal Mode/Block Transfer Mode (Contention with Another Channel/Dual Address Mode/Low Level Sensing) ..371 Figure 8.45 Transfer End Interrupt Logic ...................374 Figure 8.46 Example of Procedure for Restarting Transfer on Channel in which...
  • Page 32 Figure 11.20 Example of PWM Mode Setting Procedure ............545 Figure 11.21 Example of PWM Mode Operation (1) ..............546 Figure 11.22 Example of PWM Mode Operation (2) ..............546 Figure 11.23 Example of PWM Mode Operation (3) ..............547 Figure 11.24 Example of Phase Counting Mode Setting Procedure ...........548 Figure 11.25 Example of Phase Counting Mode 1 Operation ............549 Figure 11.26 Example of Phase Counting Mode 2 Operation ............550 Figure 11.27 Example of Phase Counting Mode 3 Operation ............551...
  • Page 33 Figure 12.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary) ....587 Figure 12.10 Inverted Pulse Output (Example) ................588 Figure 12.11 Pulse Output Triggered by Input Capture (Example) ..........589 Section 13 8-Bit Timers (TMR) Figure 13.1 Block Diagram of 8-Bit Timer Module ..............592 Figure 13.2 Example of Pulse Output ..................600 Figure 13.3 Count Timing for Internal Clock Input..............600 Figure 13.4 Count Timing for External Clock Input..............601...
  • Page 34 Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1) ........674 Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2) ........675 Figure 15.14 Data Format in Clocked Synchronous Communication (For LSB-First) ....676 Figure 15.15 Sample SCI Initialization Flowchart..............677 Figure 15.16 Sample SCI Transmission Operation in Clocked Synchronous Mode ....679 Figure 15.17 Sample Serial Transmission Flowchart ..............680 Figure 15.18 Example of SCI Operation in Reception ...............681 Figure 15.19 Sample Serial Reception Flowchart...............682...
  • Page 35 Figure 16.12 Slave Receive Mode Operation Timing 2..............728 Figure 16.13 Block Diagram of Noise Conceler.................729 Figure 16.14 Sample Flowchart for Master Transmit Mode............730 Figure 16.15 Sample Flowchart for Master Receive Mode ............731 Figure 16.16 Sample Flowchart for Slave Transmit Mode ............732 Figure 16.17 Sample Flowchart for Slave Receive Mode............733 Figure 16.18 Timing of the Bit Synchronous Circuit..............735 Section 17 A/D Converter...
  • Page 36: Electrical Characteristics

    Figure 22.2 Software Standby Mode Application Example............811 Figure 22.3 Hardware Standby Mode Timing ................812 Section 24 Electrical Characteristics Figure 24.1 Output Load Circuit....................855 Figure 24.2 System Clock Timing ....................856 Figure 24.3 SDRAM φ Timing* ....................857 Figure 24.4 (1) Oscillation Stabilization Timing ................857 Figure 24.4 (2) Oscillation Stabilization Timing ................858 Figure 24.5 Reset Input Timing ....................859 Figure 24.6 Interrupt Input Timing .....................859...
  • Page 37 Figure 24.40 WDT Output Timing .....................888 Figure 24.41 SCK Clock Input Timing..................888 Figure 24.42 SCI Input/Output Timing: Synchronous Mode............888 Figure 24.43 A/D Converter External Trigger Input Timing ............889 Figure 24.44 I C Bus Interface Input/Output Timing (Option)...........889 Rev. 1.0, 09/01, page xxxvii of xliv...
  • Page 38 Rev. 1.0, 09/01, page xxxviii of xliv...
  • Page 39 Tables of Contents Section 1 Overview Table 1.1 Pin Arrangement in Each Operating Mode ..............4 Table 1.2 Pin Functions.......................10 Section 2 CPU Table 2.1 Instruction Classifcation....................33 Table 2.2 Operation Notation......................34 Table 2.3 Data Transfer Instructions...................35 Table 2.4 Arithmetic Operations Instructions (1) ...............36 Table 2.4 Arithmetic Operations Instructions (2) ...............37 Table 2.5...
  • Page 40 Table 6.6 DRAM Interface Pins....................158 Table 6.7 Relation between Settings of Bits RMTS2 to RMTS0 and Synchronous DRAM Space ......................180 Table 6.8 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing..181 Table 6.9 Synchronous DRAM Interface Pins................183 Table 6.10 Setting CAS Latency.....................186 Table 6.11 Idle Cycles in Mixed Accesses to Normal Space and DRAM...
  • Page 41 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.1 TPU Functions ......................494 Table 11.2 Pin Configuration ....................497 Table 11.3 CCLR2 to CCLR0 (Channels 0 and 3)..............501 Table 11.4 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)............501 Table 11.5 TPSC2 to TPSC0 (Channel 0)................502 Table 11.6 TPSC2 to TPSC0 (Channel 1)................502 Table 11.7...
  • Page 42 Table 13.4 Timer Output Priorities ..................608 Table 13.5 Switching of Internal Clock and TCNT Operation ..........610 Section 14 Watchdog Timer Table 14.1 WDT Pin .......................614 Table 14.2 WDT Interrupt Source ..................620 Section 15 Serial Communication Interface (SCI, IrDA) Table 15.1 Pin Configuration....................628 Table 15.2 Relationships between N Setting in BRR and Bit Rate B ........646...
  • Page 43 Section 20 Flash Memory (F-ZTAT Version) Table 20.1 Differences between Boot Mode and User Program Mode........767 Table 20.2 Pin Configuration ....................772 Table 20.3 Erase Blocks......................775 Table 20.4 Setting On-Board Programming Modes..............778 Table 20.5 Boot Mode Operation....................780 Table 20.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible .........................780 Table 20.7 Flash Memory Operating States ................789...
  • Page 44 Rev. 1.0, 09/01, page xliv of xliv...
  • Page 45: Section 1 Overview

    Section 1 Overview Features High-speed H8S/2000 central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 65 basic instructions Various peripheral functions DMA controller (DMAC) EXDMA controller (EXDMAC) Data transfer controller (DTC) 16-bit timer-pulse unit (TPU) Programmable pulse generator (PPG)
  • Page 46: Block Diagram

    Block Diagram Port D Port E PA7/A23/ PA6/A22/ DCTL PA5/A21/ EXTAL PA4/A20/ XTAL PA3/A19 EMLE PA2/A18 PA1/A17 H8S/2000 CPU PA0/A16 Clock PB7/A15 pulse PB6/A14 generator PB5/A13 PB4/A12 PF7/øF Interrupt controller PB3/A11 PF6/ PB2/A10 PF5/ PB1/A9 PF4/ PB0/A8 PF3/ DMAC PC7/A7 PF2/ /DQML PC6/A6...
  • Page 47: Pin Description

    Pin Description 1.3.1 Pin Arrangement PG2/ PG3/ PE7/D7 AVcc Vref PE6/D6 P40/AN0 PE5/D5 P41/AN1 PE4/D4 P42/AN2 PE3/D3 P43/AN3 PE2/D2 P44/AN4 PE1/D1 P45/AN5 PE0/D0 P46/AN6/DA0 DCTL P47/AN7/DA1 P85/( )/SCK3/ P90/AN8 P84/( P91/AN9 P83/( )/RXD3/ P92/AN10 P27/PO7/TIOCB5/( P93/AN11 P26/PO6/TIOCA5/( P94/AN12/DA2 P25/PO5/TIOCB4/( P95/AN13/DA3 LQFP-144 P24/PO4/TIOCA4/RXD4/( P96/AN14/DA4...
  • Page 48: Pin Arrangement In Each Operating Mode

    1.3.2 Pin Arrangement in Each Operating Mode Table 1.1 Pin Arrangement in Each Operating Mode Pin Name Mode 7 Flash Memory Programmer Modes 1 and 5 Modes 2 and 6 Mode 4 EXPE = 1 EXPE = 0 Mode P80/(I RQ 0)/ P80/(I RQ 0)/ P80/(I RQ 0)/ P80/(I RQ 0)/...
  • Page 49 Pin Name Mode 7 Flash Memory Programmer Modes 1 and 5 Modes 2 and 6 Mode 4 EXPE = 1 EXPE = 0 Mode A20/I RQ 4 A20/I RQ 4 PA4/A20/I RQ 4 PA4/A20/I RQ 4 PA4/I RQ 4 PA5/A21/I RQ 5 PA5/A21/I RQ 5 PA5/A21/I RQ 5 PA5/A21/I RQ 5...
  • Page 50 Pin Name Mode 7 Flash Memory Programmer Modes 1 and 5 Modes 2 and 6 Mode 4 EXPE = 1 EXPE = 0 Mode P17/PO15/ P17/PO15/ P17/PO15/ P17/PO15/ P17/PO15/ TIOCB2/TCLKD/ED TIOCB2/TCLKD/ED TIOCB2/TCLKD/ED TIOCB2/TCLKD/ED TIOCB2/TCLKD/ED RA K 3 RA K 3 RA K 3 RA K 3 RA K 3...
  • Page 51 Pin Name Mode 7 Flash Memory Programmer Modes 1 and 5 Modes 2 and 6 Mode 4 EXPE = 1 EXPE = 0 Mode PE5/D5 PE5/D5 PE5/D5 PE6/D6 PE6/D6 PE6/D6 PE7/D7 PE7/D7 PE7/D7 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 P60/TMRI0/ P60/TMRI0/...
  • Page 52 Pin Name Mode 7 Flash Memory Programmer Modes 1 and 5 Modes 2 and 6 Mode 4 EXPE = 1 EXPE = 0 Mode XTAL XTAL XTAL XTAL XTAL XTAL EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL STBY STBY STBY STBY STBY P63/TMCI1/ P63/TMCI1/...
  • Page 53 Pin Name Mode 7 Flash Memory Programmer Modes 1 and 5 Modes 2 and 6 Mode 4 EXPE = 1 EXPE = 0 Mode P93/AN11 P93/AN11 P93/AN11 P93/AN11 P93/AN11 P94/AN12/DA2 P94/AN12/DA2 P94/AN12/DA2 P94/AN12/DA2 P94/AN12/DA2 P95/AN13/DA3 P95/AN13/DA3 P95/AN13/DA3 P95/AN13/DA3 P95/AN13/DA3 P96/AN14/DA4 P96/AN14/DA4 P96/AN14/DA4 P96/AN14/DA4...
  • Page 54: Pin Functions

    1.3.3 Pin Functions Table 1.2 Pin Functions Type Symbol Pin No. Function Power 4, 41, 72, Input For connection to the power supply. V pins should 98, 99 be connected to the system power supply. 2, 10, 18, Input For connection to ground. V pins should be 25, 50, 70, connected to the system power supply (0 V).
  • Page 55 Type Symbol Pin No. Function Address bus A23 to A0 31 to 26, Output These pins output an address. 24 to 19, 17 to 11, 9 to 5 Data bus D15 to 80 to 73, Input/ These pins constitute a bidirectional data bus. output 69 to 63 Bus control...
  • Page 56 Type Symbol Pin No. Function Bus control 109, 110, Output Row address strobe signal for the synchronous RA S/RA S 35, 36 DRAM interface. RA S3 to RA S signal is a row address strobe signal when RA S5 areas 2 to 5 are set to the continuous DRAM space. Output Row address strobe signal for the synchronous RA S DRAM of the synchronous DRAM interface.
  • Page 57 Type Symbol Pin No. Function EXDMA Output These signals indicate the end of EXDMAC data ETEN D 3, controller transfer. ETEN D 2 (EXDMAC) Output EXDMAC single address transfer acknowledge ED A CK 3, signals. ED A CK 2 Output These signals notify an external device of ED RA K 3, acceptance and start of execution of a DMA transfer ED RA K 2...
  • Page 58 Type Symbol Pin No. Function Serial commu- TxD4 Output Data output pins. nication TxD3 interface TxD2 133, (SCI)/smart TxD1 141, card interface TxD0/ (SCI_0 with IrTxD IrDA function) RxD4 Input Data input pins. RxD3 RxD2 134, RxD1 139, RxD0/ IrRxD SCK4 138, Input/...
  • Page 59 Type Symbol Pin No. Function I/O ports P17 to 49 to 42 Input/ Eight-bit input/output pins. output P27 to 58 to 51 Input/ Eight-bit input/output pins. output P35 to 137 to 142 Input/ Six-bit input/output pins. output P47 to 120 to 113 Input Eight-bit input pins.
  • Page 60 Rev. 1.0, 09/01, page 16 of 904...
  • Page 61: Section 2 Cpu

    Section 2 CPU The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2000 CPU.
  • Page 62: Differences Between H8S/2600 Cpu And H8S/2000 Cpu

    • Two CPU operating modes  Normal mode*  Advanced mode Note: For this LSI, normal mode is not available. • Power-down state  Transition to power-down state by SLEEP instruction  Selectable CPU clock speed 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
  • Page 63: Differences From H8/300 Cpu

    2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers  Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been added.
  • Page 64: Cpu Operating Modes

    CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte address space. The mode is selected by the LSI's mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU in normal mode.
  • Page 65: Advanced Mode

    H'0000 Reset exception vector H'0001 H'0002 (Reserved for system use) H'0003 H'0004 H'0005 (Reserved for system use) H'0006 Exception H'0007 vector table H'0008 Exception vector 1 H'0009 H'000A Exception vector 2 H'000B Figure 2.1 Exception Vector Table (Normal Mode) EXR* (16 bits) Reserved* SP *...
  • Page 66 • Exception vector table and memory indirect branch addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table in 32-bit units. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (see figure 2.3).
  • Page 67 EXR* Reserved Reserved* (24 bits) (24 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used, it is not stored on the stack. SP when EXR is not used. Ignored when returning. Figure 2.4 Stack Structure in Advanced Mode Rev.
  • Page 68: Address Space

    Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product.
  • Page 69: Register Configuration

    Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and an 8-bit condition code register (CCR). General Registers (Rn) and Extended Registers (En) ER7 (SP) Control Registers...
  • Page 70: General Registers

    2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers.
  • Page 71: Program Counter (Pc)

    Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched for read, the least significant PC bit is regarded as 0.) 2.4.3 Extended Control Register (EXR)
  • Page 72: Condition-Code Register (Ccr)

    2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions.
  • Page 73 Bit Name Initial Value R/W Description R/W Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. For details, refer to section 5, Interrupt Controller.
  • Page 74: Initial Register Values

    2.4.5 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace (T) bit in EXR to 0, and sets the interrupt mask (I) bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized.
  • Page 75 Data Type Register Number Data Image Word data Word data Longword data Legend : General register ER : General register E : General register R : General register RH : General register RL : Most significant bit : Least significant bit Figure 2.9 General Register Data Formats (2) Rev.
  • Page 76: Memory Data Formats

    2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address.
  • Page 77: Instruction Set

    Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1. Table 2.1 Instruction Classifcation Function Instructions Size Types Data transfer B/W/L POP* , PUSH* LDM, STM MOVFPE* , MOVTPE* Arithmetic ADD, SUB, CMP, NEG B/W/L...
  • Page 78: Table Of Instructions Classified By Function

    2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description General register (destination)* General register (source)* General register* General register (32-bit register) (EAd)
  • Page 79 Table 2.3 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE Cannot be used in this LSI. MOVTPE Cannot be used in this LSI.
  • Page 80 Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Subtraction on immediate data and data in a general register cannot be performed in bytes.
  • Page 81 Table 2.4 Arithmetic Operations Instructions (2) Instruction Size* Function Rd ÷ Rs → Rd DIVXS Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.
  • Page 82 Table 2.5 Logic Operations Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
  • Page 83 Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
  • Page 84 Table 2.7 Bit Manipulation Instructions (2) Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR Logically exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ⊕...
  • Page 85 Table 2.8 Branch Instructions Instruction Size Function – Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never C ∨ Z = 0 High C ∨...
  • Page 86 Table 2.9 System Control Instructions Instruction Size* Function TRAPA – Starts trap-instruction exception handling. – Returns from an exception-handling routine. SLEEP – Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR Moves the memory operand contents or immediate data to CCR or EXR.
  • Page 87: Basic Instruction Formats

    Table 2.10 Block Data Transfer Instructions Instruction Size Function if R4L ≠ 0 then EEPMOV.B – Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next: if R4 ≠ 0 then EEPMOV.W – Repeat @ER5+ → @ER6+ R4–1 →...
  • Page 88: Addressing Modes And Effective Address Calculation

    (1) Operation field only NOP, RTS (2) Operation field and register fields ADD.B Rn, Rm (3) Operation field, register fields, and effective address extension MOV.B @(d:16, Rn), Rm EA (disp) (4) Operation field, effective address extension, and condition field EA (disp) BRA d:16 Figure 2.11 Instruction Formats (Examples) Addressing Modes and Effective Address Calculation...
  • Page 89: Register Direct-Rn

    2.7.1 Register Direct—Rn The register field of the instruction code specifies an 8-, 16-, or 32-bit general register which contains the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2.7.2 Register Indirect—@ERn The register field of the instruction code specifies an address register (ERn) which contains the...
  • Page 90: Immediate-#Xx:8, #Xx:16, Or #Xx:32

    A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.12 Absolute Address Access Ranges Absolute Address Normal Mode Advanced Mode Data address 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16)
  • Page 91: Memory Indirect-@@Aa:8

    In normal mode, the memory operand is a word operand and the branch address is 16 bits long. In advanced mode, the memory operand is a longword operand, the first byte of which is assumed to be 0 (H'00). Note that the top area of the address range in which the branch address is stored is also used for the exception vector area.
  • Page 92 Table 2.13 Effective Address Calculation (1) Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Register direct (Rn) Operand is general register contents. Register indirect (@ERn) General register contents General register contents Sign extension Register indirect with post-increment or pre-decrement •Register indirect with post-increment @ERn+ General register contents...
  • Page 93 Table 2.13 Effective Address Calculation (2) Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address Sign extension Immediate Operand is immediate data. Program-counter relative @(d:8,PC)/@(d:16,PC) PC contents Sign extension Memory indirect @@aa:8 • Normal mode* Memory contents •...
  • Page 94: Processing States

    Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. • Reset state In this state the CPU and internal peripheral modules are all initialized and stopped. When the 5(6 input goes low, all current processing stops and the CPU enters the reset state.
  • Page 95: Usage Notes

    End of bus request Bus request Program execution state Bus-released state Sleep mode External interrupt request Exception Software standby handling state mode = High = High, = Low Hardware standby Reset state mode Reset state Power down state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever goes low.
  • Page 96 Rev. 1.0, 09/01, page 52 of 904...
  • Page 97: Section 3 Mcu Operating Modes

    Section 3 MCU Operating Modes Operating Mode Selection The H8S/2378 Series has seven operating modes (modes 1 to 7). For each operating mode, pins are given with different functions. An operating mode is selected by the setting of mode pins (MD2 to MD0).
  • Page 98: Register Descriptions

    Register Descriptions The following registers are related to the operating mode. • Mode control register (MDCR) • System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR monitors the current operating mode of the H8S/2378 Series chip. Bit Name Initial Value Descriptions −...
  • Page 99 Bit Name Initial Value Descriptions − Reserved − The initial value should not be modified. − Reserved − The initial value should not be modified. FLSHE Flash Memory Control Register Enable Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). If this bit is set to 1, the flash memory control registers can be read/written to.
  • Page 100: Operating Mode Descriptions

    Operating Mode Descriptions 3.3.1 Mode 1 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B, and C function as an address bus, ports D and E function as a data bus, and parts of ports F, G, and H carry bus control signals.
  • Page 101: Mode 6

    Ports A, B, and C function as an address bus, ports D and E function as a data bus, and parts of ports F, G and H carry bus control signals. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. The program in an external ROM connected to the first half of area 0 is executed.
  • Page 102: Pin Functions

    3.3.8 Pin Functions Table 3.2 shows the pin functions in each operating mode. Table 3.2 Pin Functions in Each Operating Mode Mode Mode Mode Mode Mode Mode Mode Port Port A PA7 to PA4 to Port B Port C Port D Port E Port F PF7,...
  • Page 103: Memory Map In Each Operating Mode

    Memory Map in Each Operating Mode Figures 3.1 to 3.4 show memory maps for each product. Mode 1 and 2 Mode 3 Mode 4 (Expanded mode with (Boot mode) (Expanded mode with on-chip ROM disabled) on-chip ROM enabled) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM...
  • Page 104 Mode 7 Mode 5 and 6 (External ROM activatin (Single-chip activation expanded mode, expanded mode, with on-chip enabled) with on-chip ROM enabled) H'000000 H'000000 External address External adderss space space H'060000 H'100000 On-chip ROM External address space/ reserved area H'160000 External address space H'FF4000...
  • Page 105 Mode 1 and 2 Mode 3 Mode 4 (Expanded mode with (Boot mode) (Expanded mode with on-chip ROM disabled) on-chip ROM enabled) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM External address space H'060000 H'060000 External address External address space/ space Reserved area H'FF4000 H'FF4000...
  • Page 106 Mode 5 and 6 Mode 7 (External ROM activation (Single-chip activation expanded mode, expanded mode, with on-chip ROM enabled) with on-chip ROM enabled) H'000000 H'000000 On-chip RAM External address space H'060000 H'100000 On-chip RAM External address space/ reserved area H'160000 External address space H'FF8000...
  • Page 107: Section 4 Exception Handling

    Section 4 Exception Handling Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
  • Page 108 Table 4.2 Exception Handling Vector Table Vector Address* Exception Source Vector Number Normal Mode* Advanced Mode Power-on reset H'0000 to H'0001 H'0000 to H'0003 Manual reset * H'0002 to H'0003 H'0004 to H'0007 Reserved for system use H'0004 to H'0005 H'0008 to H'000B H'0006 to H'0007 H'000C to H'000F...
  • Page 109: Reset

    Vector Address* Exception Source Vector Number Normal Mode* Advanced Mode Internal interrupt* H'0040 to H'0041 H'0080 to H'0083    H'00EC to H'00ED H'01D8 to H'01DB Notes: 1. Lower 16 bits of the address. 2. Not available in this LSI. 3.
  • Page 110 Prefetch of first Internal Vector fetch program instruction processing φ Internal address bus Internal read signal Internal write High signal Internal data (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Figure 4.1 Reset Sequence (Advanced Mode with On-chip ROM Enabled)
  • Page 111: Interrupts After Reset

    Internal Prefetch of first processing program instruction Vector fetch Address bus High D15 to D0 (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Note: * Seven program wait states are inserted.
  • Page 112: Traces

    Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details on interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction.
  • Page 113: Trap Instruction

    Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling is as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended register (EXR) are saved in the stack.
  • Page 114: Stack Status After Exception Handling

    Stack Status after Exception Handling Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. (a) Normal Modes Reserved* CCR* CCR* PC (16 bits) PC (16 bits) Interrupt control mode 0 Interrupt control mode 2 (b) Advanced Modes Reserved* PC (24 bits)
  • Page 115: Usage Notes

    Usage Notes When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W (or MOV.W Rn, @-SP)
  • Page 116 Rev. 1.0, 09/01, page 72 of 904...
  • Page 117: Section 5 Interrupt Controller

    Section 5 Interrupt Controller Features • Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the interrupt control register (INTCR). • Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI.
  • Page 118 A block diagram of the interrupt controller is shown in figure 5.1. INTM1 INTM0 INTCR NMIEG NMI input NMI input unit Interrupt request IRQ input unit IRQ input Vector number Priority SSIER ITSR ISCR determination Internal interrupt sources I2 to I0 SWDTEND to IICI1 Interrupt controller...
  • Page 119: Input/Output Pins

    Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Name Function Input Nonmaskable external interrupt Rising or falling edge can be selected. ,5448 to ,543 Input Maskable external interrupts Rising, falling, or both edges, or level sensing, can be selected.
  • Page 120: Interrupt Control Register (Intcr)

    5.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit Name Initial Value Description − − Reserved − − These bits are always read as 0 and cannot be modified. INTM1 Interrupt Control Select Mode 1 and 0 INTM0 These bits select either of two interrupt control modes for the interrupt controller.
  • Page 121 Bit Name Initial Value Description − − Reserved This bit is always read as 0 and cannot be modified. IPR14 Sets the priority of the corresponding interrupt IPR13 source. IPR12 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5...
  • Page 122: Irq Enable Register (Ier)

    Bit Name Initial Value Description − − Reserved This bit is always read as 0 and cannot be modified. IPR2 Sets the priority of the corresponding interrupt IPR1 source. IPR0 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5...
  • Page 123 Bit Name Initial Value Description IRQ9E IRQ9 Enable The IRQ9 interrupt request is enabled when this bit is 1. IRQ8E IRQ8 Enable The IRQ8 interrupt request is enabled when this bit is 1. IRQ7E IRQ7 Enable The IRQ7 interrupt request is enabled when this bit is 1.
  • Page 124: Irq Sense Control Registers H And L (Iscrh, Iscrl)

    5.3.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCR select the source that generates an interrupt request at pins ,5448 to ,543. • ISCRH Bit Name Initial Value Description IRQ15SCB IRQ15 Sense Control B IRQ15SCA IRQ15 Sense Control A 00: Interrupt request generated at ,5448 input low level 01: Interrupt request generated at falling edge...
  • Page 125 Bit Name Initial Value Description IRQ12SCB IRQ12 Sense Control B IRQ12SCA IRQ12 Sense Control A 00: Interrupt request generated at ,5445 input low level 01: Interrupt request generated at falling edge of ,5445 input 10: Interrupt request generated at rising edge of ,5445 input 11: Interrupt request generated at both falling and rising edges of ,5445 input...
  • Page 126 Bit Name Initial Value Description IRQ8SCB IRQ8 Sense Control B IRQ8SCA IRQ8 Sense Control A 00: Interrupt request generated at ,54; input low level 01: Interrupt request generated at falling edge of ,54; input 10: Interrupt request generated at rising edge of ,54;...
  • Page 127 Bit Name Initial Value Description IRQ5SCB IRQ5 Sense Control B IRQ5SCA IRQ5 Sense Control A 00: Interrupt request generated at ,548 input low level 01: Interrupt request generated at falling edge of ,548 input 10: Interrupt request generated at rising edge of ,548 input 11: Interrupt request generated at both falling and rising edges of ,548 input...
  • Page 128 Bit Name Initial Value Description IRQ2SCB IRQ2 Sense Control B IRQ2SCA IRQ2 Sense Control A 00: Interrupt request generated at ,545 input low level 01: Interrupt request generated at falling edge of ,545 input 10: Interrupt request generated at rising edge of ,545 input 11: Interrupt request generated at both falling and rising edges of ,545 input...
  • Page 129: Irq Status Register (Isr)

    5.3.5 IRQ Status Register (ISR) ISR is an IRQ15 to IRQ0 interrupt request flag register. Bit Name Initial Value Description IRQ15F R/(W)* [Setting conditions] IRQ14F R/(W)* When the interrupt source selected by ISCR IRQ13F R/(W)* occurs IRQ12F R/(W)* [Clearing conditions] IRQ11F R/(W)* •...
  • Page 130: Irq Pin Select Register (Itsr)

    5.3.6 IRQ Pin Select Register (ITSR) ITSR selects input pins ,5448 to ,543. Bit Name Initial Value Description Selects ,5448 input pin. ITS15 0: PF2 1: P27 Selects ,5447 input pin. ITS14 0: PF1 1: P26 Selects ,5446 input pin. ITS13 0: P65 1: P25...
  • Page 131 Bit Name Initial Value Description Selects ,548 input pin. ITS5 0: PA5 1: P85 Selects ,547 input pin. ITS4 0: PA4 1: P84 Selects ,546 input pin. ITS3 0: P53 1: P83 Selects ,545 input pin. ITS2 0: P52 1: P82 Selects ,544 input pin.
  • Page 132: Software Standby Release Irq Enable Register (Ssier)

    5.3.7 Software Standby Release IRQ Enable Register (SSIER) SSIER selects the ,54 pins used to recover from the software standby state. Bit Name Initial Value Description SSI15 Software Standby Release IRQ Setting SSI14 These bits select the ,54Q pins used to recover SSI13 from the software standby state.
  • Page 133: Internal Interrupts

    When IRQ15 to IRQ0 interrupt requests occur at low level of ,54Q, the corresponding ,54 should be held low until an interrupt handling starts. Then the corresponding ,54 should be set to high in the interrupt handling routine and clear the IRQnF bit (n = 0 to 15) in ISR to 0. Interrupts may not be executed when the corresponding ,54#is set to high before the interrupt handling starts.
  • Page 134: Interrupt Exception Handling Vector Table

    Interrupt Exception Handling Vector Table Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. When interrupt control mode 2 is set, priorities among modules can be set by means of the IPR. Modules set at the same priority will conform to their default priorities.
  • Page 135 Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector Address* Origin of Interrupt Interrupt Vector Advanced DMAC Source Mode Source Number Priority Activation Activation External H'001C — High — — IRQ0 H'0040 IPRA14 to IPRA12 — IRQ1 H'0044 IPRA10 to IPRA8 —...
  • Page 136 Vector Address* Origin of Interrupt Interrupt Vector Advanced DMAC Source Source Number Mode Priority Activation Activation TPU_0 TGI0D H'00AC High — TCI0V H'00B0 — — — Reserved for H’00B4 IPRF6 to IPRF4 — — system use H’00B8 — — H’00BC —...
  • Page 137 Vector Address* Origin of Interrupt Interrupt Vector Advanced DMAC Source Source Number Mode Priority Activation Activation High — — — Reserved for H’012C system use TMR_1 CMIA1 H'0130 IPRH10 to IPRH8 — — CMIB1 H'0134 — — OVI1 H'0138 — —...
  • Page 138 Vector Address* Origin of Interrupt Interrupt Vector Advanced DMAC Source Source Number Mode Priority Activation Activation SCI_4 ERI4 H’01A0 IPRJ2 to IPRJ0 High — — RXI4 — — H’01A4 TXI4 H’01A8 — — TEI4 — — H’01AC Reserved for H’01B0 IPRK14 to IPRK12 —...
  • Page 139: Interrupt Control Modes And Interrupt Operation

    Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by INTCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2.
  • Page 140 Program execution status Interrupt generated? I = 0 Hold pending IRQ0 IRQ1 IICI1 Save PC and CCR I ← 1 Read vector address Branch to interrupt handling routine Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev.
  • Page 141: Interrupt Control Mode 2

    5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting. Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case.
  • Page 142: Interrupt Exception Handling Sequence

    Program execution status Interrupt generated? Level 7 interrupt? Level 6 interrupt? Mask level 6 or below? Level 1 interrupt? Mask level 5 or below? Mask level 0? Hold Save PC, CCR, and EXR pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance...
  • Page 143 Figure 5.5 Interrupt Exception Handling Rev. 1.0, 09/01, page 99 of 904...
  • Page 144: Interrupt Response Times

    5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.4 are explained in table 5.5. This LSI is capable of fast word transfer to on-chip memory, and have the program area in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing.
  • Page 145: Dtc And Dmac Activation By Interrupt

    Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8 Bit Bus 16 Bit Bus Internal 2-State 3-State 2-State 3-State Symbol Memory Access Access Access Access Instruction fetch S 6+2m Branch address read S Stack manipulation S Legend: m: Number of wait states in an external device access.
  • Page 146: Usage Notes

    Usage Notes 5.7.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to mask interrupts, the masking becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction.
  • Page 147: Instructions That Disable Interrupts

    5.7.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends.
  • Page 148 Rev. 1.0, 09/01, page 104 of 904...
  • Page 149: Section 6 Bus Controller (Bsc)

    Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the bus masters—the CPU, DMA controller (DMAC), EXDMA controller (EXDMAC), and data transfer controller (DTC).
  • Page 150 A block diagram of the bus controller is shown in figure 6.1. EXDMAC address bus Address Area decoder selector Internal address bus External bus controller Internal bus master bus request signal External bus EXDMAC bus request signal arbiter External bus Internal bus master bus acknowledge signal control signals EXDMAC bus acknowledge signal...
  • Page 151: Input/Output Pins

    Input/Output Pins Table 6.1 summarizes the pin configuration of the bus controller. Table 6.1 Pin Configuration Name Symbol Function Address strobe Output Strobe signal indicating that normal space is accessed and address output on address bus is enabled. Read Output Strobe signal indicating that normal space is being read.
  • Page 152 Name Symbol Function &67/ Chip select 4/row address Output Strobe signal indicating that area 4 is 5$67/ strobe 4/write enable selected, DRAM row address strobe signal when area 4 is DRAM space, or write enable signal of the synchronous DRAM when the synchronous DRAM interface is selected.
  • Page 153: Register Descriptions

    Name Symbol Function %5(42 Bus request output Output External bus request signal used when internal bus master accesses external address space when external bus is released. '$&.4 Data transfer acknowledge Output Data transfer acknowledge signal for single 1 (DMAC) address transfer by DMAC channel 1. '$&.3 '$&.3 Data transfer acknowledge...
  • Page 154: Bus Width Control Register (Abwcr)

    • Refresh time constant register (RTCOR) 6.3.1 Bus Width Control Register (ABWCR) ABWCR designates each area in the external address space as either 8-bit access space or 16-bit access space. Bit Name Initial Value* Description ABW7 Area 7 to 0 Bus Width Control ABW6 These bits select whether the corresponding ABW5...
  • Page 155: Wait Control Registers Ah, Al, Bh, And Bl (Wtcrah, Wtcral, Wtcrbh, And Wtcrbl)

    6.3.3 Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH, and WTCRBL) WTCRA and WTCRB select the number of program wait states for each area in the external address space. In addition, CAS latency is set when a synchronous DRAM is connected. •...
  • Page 156 Bit Name Initial Value Description Area 6 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 6 while AST6 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted...
  • Page 157 Bit Name Initial Value Description − Reserved This bit is always read as 0 and cannot be modified. Area 4 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 4 while AST4 bit in ASTCR = 1.
  • Page 158 Bit Name Initial Value Description Area 2 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 2 while AST2 bit in ASTCR = 1. A CAS latency is set when the synchronous DRAM is connected*.
  • Page 159 • WTCRBL Bit Name Initial Value Description − Reserved This bit is always read as 0 and cannot be modified. Area 1 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 1 while AST1 bit in ASTCR = 1.
  • Page 160: Read Strobe Timing Control Register (Rdncr)

    6.3.4 Read Strobe Timing Control Register (RDNCR) RDNCR selects the read strobe signal (5') negation timing in a basic bus interface read access. Bit Name Initial Value Description RDN7 Read Strobe Timing Control 7 to 0 RDN6 These bits set the negation timing of the read RDN5 strobe in a corresponding area read access.
  • Page 161: Cs Assertion Period Control Registers H, L (Csacrh, Csacrl)

    &6 Assertion Period Control Registers H, L (CSACRH, CSACRL) &6 &6 &6 6.3.5 CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip select signals (&6Q) and address signals is to be extended. Extending the assertion period of the &6Q and address signals allows flexible interfacing to external I/O devices.
  • Page 162 Bus cycle Address Read Data Write Data Figure 6.3 &6 &6 and Address Assertion Period Extension (Example of 3-State Access Space &6 &6 and RDNn = 0) Rev. 1.0, 09/01, page 118 of 904...
  • Page 163: Area 0 Burst Rom Interface Control Register (Bromcrh) Area 1 Burst Rom Interface Control Register (Bromcrl)

    6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1 Burst ROM Interface Control Register (BROMCRL) BROMCRH and BROMCRL are used to make burst ROM interface settings. Area 0 and area 1 burst ROM interface settings can be made independently in BROMCRH and BROMCRL, respectively.
  • Page 164: Bus Control Register (Bcr)

    6.3.7 Bus Control Register (BCR) BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of :$,7 pin input. Bit Name Initial Value Description BRLE Bus Release Enable...
  • Page 165 Bit Name Initial Value Description ICIS0 Idle Cycle Insert 0 When an external read cycle and external write cycle are performed consecutively, an idle cycle can be inserted between the bus cycles. 0: Idle cycle not inserted 1: Idle cycle inserted WDBE Write Data Buffer Enable The write data buffer function can be used for...
  • Page 166: Dram Control Register (Dramcr)

    6.3.8 DRAM Control Register (DRAMCR) DRAMCR is used to make DRAM/synchronous DRAM* interface settings. Note: * The synchronous DRAM interface is not supported in the H8S/2378 Serise. Bit Name Initial Value Description 2( Output Enable The OE signal used when EDO page mode DRAM is connected can be output from the (OE) pin.
  • Page 167 Bit Name Initial Value Description CAST Column Address Output Cycle Number Select Selects whether the column address output cycle in DRAM access comprises 3 states or 2 states. The setting of this bit applies to all areas designated as DRAM space. 0: 2 states 1: 3 states −...
  • Page 168 Bit Name Initial Value Description Burst Access Enable Selects enabling or disabling of burst access to areas designated as DRAM/continuous synchronous DRAM space. DRAM/continuous synchronous DRAM space burst access is performed in fast page mode. When using EDO page mode DRAM, the 2( signal must be connected.
  • Page 169 Bit Name Initial Value Description DMAC Single Address Transfer Option Selects whether full access is always performed or burst access is enabled when DMAC single address transfer is performed on the DRAM/synchronous DRAM . When the BE bit is cleared to 0 in DRAMCR, disabling DRAM/synchronous DRAM burst access, DMAC single address transfer is performed in full access mode regardless of the...
  • Page 170 Bit Name Initial Value Description MXC2 Address Multiplex Select MXC1 These bits select the size of the shift toward the MXC0 lower half of the row address in row address/column address multiplexing. In burst operation on the DRAM/synchronous DRAM interface, these bits also select the row address bits to be used for comparison.
  • Page 171 Bit Name Initial Value Description 011: 11-bit shift • When 8-bit access space is designated: Row address bits A23 to A11 used for comparison When 16-bit access space is designated: Row address bits A23 to A12 used for comparison Synchronous DRAM interface 100: 8-bit shift •...
  • Page 172 Bit Name Initial Value Description 111: 11-bit shift • When 8-bit access space is designated: Row address bits A23 to A11 used for comparison • When 16-bit access space is designated: Row address bits A23 to A12 used for comparison The precharge-sel is A15 to A12 of the column address.
  • Page 173: Dram Access Control Register (Draccr)

    6.3.9 DRAM Access Control Register (DRACCR) DRACCR is used to set the DRAM/synchronous DRAM interface bus specifications. Note: *The synchronous DRAM interface is not supported in the H8S/2378 series. Bit Name Initial Value Description DRMI Idle Cycle Insertion An idle cycle can be inserted after a DRAM/synchronous DRAM access cycle when a continuous normal space access cycle follows a DRAM/synchronous DRAM access cycle.
  • Page 174 Bit Name Initial Value Description RCD1 RAS-CAS Wait Control RCD0 These bits select a wait cycle to be inserted between the 5$6 assert cycle and &$6 assert cycle. A 1- to 4-state wait cycle can be inserted. 00: Wait cycle not inserted 01: 1-state wait cycle inserted 10: 2-state wait cycle inserted 11: 3-state wait cycle inserted...
  • Page 175 ø Address bus Column address Column address Row address Precharge-sel Row address SDWCD 0 High Data bus PALL ACTV WRIT Address bus Column address Column address Row address Precharge-sel Row address SDWCD 1 High Data bus PALL ACTV WRIT Figure 6.5 CAS Latency Control Cycle Disable Timing during Continuous Synchronous DRAM Space Write Access (for CAS Latency 2) Rev.
  • Page 176: Refresh Control Register (Refcr)

    6.3.10 Refresh Control Register (REFCR) REFCR specifies DRAM/synchronous DRAM interface refresh control. Note: *The synchronous DRAM interface is not supported in the H8S/2378 series. Bit Name Initial Value Description R/(W)* Compare Match Flag Status flag that indicates a match between the values of RTCNT and RTCOR.
  • Page 177 Bit Name Initial Value Description − Reserved This bit is always read as 0. The initial value should not be changed. RTCK2 Refresh Counter Clock Select RTCK1 These bits select the clock to be used to RTCK0 increment the refresh counter. When the input clock is selected with bits RTCK2 to RTCK0, the refresh counter begins counting up.
  • Page 178 Bit Name Initial Value Description RLW1 Refresh Cycle Wait Control RLW0 These bits select the number of wait states to be inserted in a DRAM interface CAS-before- RAS refresh cycle/synchronous DRAM interface auto-refresh cycle. This setting applies to all areas designated as DRAM/continuous synchronous DRAM space.
  • Page 179: Refresh Timer Counter (Rtcnt)

    6.3.11 Refresh Timer Counter (RTCNT) RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits RTCK2 to RTCK0 in REFCR. When RTCNT matches RTCOR (compare match), the CMF flag in REFCR is set to 1 and RTCNT is cleared to H'00.
  • Page 180 H'000000 H'0000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'FFFF H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 Mbytes) H'DFFFFF H'E00000...
  • Page 181: Bus Specifications

    6.4.2 Bus Specifications The external address space bus specifications consist of five elements: bus width, number of access states, number of program wait states, read strobe timing, and chip select (&6) assertion period extension states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller.
  • Page 182: Memory Interfaces

    Table 6.2 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WTCRA, WTCRB Bus Specifications (Basic Bus Interface) Access Program Wait ABWn ASTn Bus Width States States — — — — — — (n = 0 to 7) Read Strobe Timing: RDNCR can be used to select either of two negation timings (at the end of the read cycle or one half-state before the end of the read cycle) for the read strobe (5') used in the basic bus interface space.
  • Page 183 ROM interface that allows direct connection of burst ROM. The interface can be selected independently for each area. An area for which the basic bus interface is designated functions as normal space, an area for which the DRAM interface is designated functions as DRAM space, an area for which the synchronous DRAM interface is designated functions as continuous synchronous DRAM space, and an area for which the burst ROM interface is designated functions as burst ROM space.
  • Page 184: Chip Select Signals

    Only the basic bus interface can be used for area 6. Area 7: Area 7 includes the on-chip RAM and internal/O registers. In externally expanded mode, the space excluding the on-chip RAM and internal I/O registers is external address space. The on- chip RAM is enabled when the RAME bit is set to 1 in the system control register (SYSCR);...
  • Page 185: Basic Bus Interface

    Bus cycle ø Address bus Area n external address Figure 6.7 &6Q &6Q &6Q Signal Output Timing (n = 0 to 7) &6Q Basic Bus Interface The basic bus interface enables direct connection of ROM, SRAM, and so on. 6.5.1 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword.
  • Page 186 Upper data bus Lower data bus D8 D7 Byte size 1st bus cycle Word size 2nd bus cycle 1st bus cycle 2nd bus cycle Longword size 3rd bus cycle 4th bus cycle Figure 6.8 Access Sizes and Data Alignment Control (8-Bit Access Space) 16-Bit Access Space: Figure 6.9 illustrates data alignment control for the 16-bit access space.
  • Page 187: Valid Strobes

    6.5.2 Valid Strobes Table 6.3 shows the data buses used and valid strobes for the access spaces. In a read, the 5' signal is valid for both the upper and the lower half of the data bus. In a write, the +:5 signal is valid for the upper half of the data bus, and the /:5 signal for the lower half.
  • Page 188 Bus cycle ø Address bus D15 to D8 Valid Read D7 to D0 Invalid High Write D15 to D8 Valid High impedance D7 to D0 Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.10 Bus Timing for 8-Bit, 2-State Access Space Rev.
  • Page 189 8-Bit, 3-State Access Space: Figure 6.11 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The /:5 pin is always fixed high. Wait states can be inserted. Bus cycle ø...
  • Page 190 16-Bit, 2-State Access Space: Figures 6.12 to 6.14 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for odd addresses, and the lower half (D7 to D0) for even addresses. Wait states cannot be inserted.
  • Page 191 Bus cycle ø Address bus D15 to D8 Invalid Read D7 to D0 Valid High Write High impedance D15 to D8 D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access) Rev.
  • Page 192 Bus cycle ø Address bus D15 to D8 Valid Read D7 to D0 Valid Write D15 to D8 Valid D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.14 Bus Timing for 16-Bit, 2-State Access Space (Word Access) Rev.
  • Page 193 16-Bit, 3-State Access Space: Figures 6.15 to 6.17 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted.
  • Page 194 Bus cycle ø Address bus D15 to D8 Invalid Read D7 to D0 Valid High Write High impedance D15 to D8 D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access) Rev.
  • Page 195: Wait Control

    Bus cycle ø Address bus D15 to D8 Valid Read D7 to D0 Valid Write D15 to D8 Valid D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.17 Bus Timing for 16-Bit, 3-State Access Space (Word Access) 6.5.4 Wait Control...
  • Page 196 Program Wait Insertion: From 0 to 7 wait states can be inserted automatically between the T state and T state on an individual area basis in 3-state access space, according to the settings in WTCRA and WTCRB. Pin Wait Insertion: Setting the WAITE bit to 1 in BCR enables wait input by means of the :$,7 pin.
  • Page 197: Read Strobe ( Rd ) Timing

    By program wait ø Address bus Read Data bus Read data Write Data bus Write data Notes: 1. Downward arrows indicate the timing of pin sampling. 2. When RDN = 0 Figure 6.18 Example of Wait State Insertion Timing 5') Timing 6.5.5 Read Strobe (5' The read strobe (5') timing can be changed for individual areas by setting bits RDN7 to RDN0 to...
  • Page 198: Extension Of Chip Select ( Cs ) Assertion Period

    Bus cycle ø Address bus RDNn = 0 Data bus RDNn = 1 Data bus Figure 6.19 Example of Read Strobe Timing &6) Assertion Period &6 &6 6.5.6 Extension of Chip Select (&6 Some external I/O devices require a setup time and hold time between address and &6 signals and strobe signals such as 5', +:5, and /:5.
  • Page 199: Dram Interface

    Bus cycle ø Address bus Read (when RDNn = 0) Data bus Read data Write Data bus Write data Figure 6.20 Example of Timing when Chip Select Assertion Period is Extended Both extension state T inserted before the basic bus cycle and extension state T inserted after the basic bus cycle, or only one of these, can be specified for individual areas.
  • Page 200: Address Multiplexing

    Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), four areas (areas 2 to 5), and continuous area (areas 2 to 5). Table 6.4 Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space RMTS2 RMTS1 RMTS0...
  • Page 201: Data Bus

    Table 6.5 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing DRAMCR Address Pins MXC2 MXC1 MXC0 Shift Size A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 8 bits A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 address 9 bits...
  • Page 202: Pins Used For Dram Interface

    6.6.4 Pins Used for DRAM Interface Table 6.6 shows the pins used for DRAM interfacing and their functions. Since the &65 to &68 pins are in the input state after a reset, set the corresponding DDR to 1 when 5$65 to 5$68 signals are output.
  • Page 203: Basic Timing

    6.6.5 Basic Timing Figure 6.21 shows the basic access timing for DRAM space. The four states of the basic timing consist of one T (precharge cycle) state, one T (row address output cycle) state, and the T and two T (column address output cycle) states.
  • Page 204: Column Address Output Cycle Control

    from both the 5' pin and the (2() pin, but in external read cycles for other than DRAM space, the signal is output only from the 5' pin. 6.6.6 Column Address Output Cycle Control The column address output cycle can be changed from 2 states to 3 states by setting the CAST bit to 1 in DRAMCR.
  • Page 205: Row Address Output State Control

    6.6.7 Row Address Output State Control If the RAST bit is set to 1 in DRAMCR, the 5$6 signal goes low from the beginning of the T state, and the row address hold time and DRAM read access time are changed relative to the fall of the 5$6 signal.
  • Page 206 If a row address hold time or read access time is necessary, making a setting in bits RCD1 and RCD0 in DRACCR allows from one to three T states, in which row address output is maintained, cycle, in which the 5$6 signal goes low, and the T to be inserted between the T cycle, in which the column address is output.
  • Page 207: Precharge State Control

    6.6.8 Precharge State Control When DRAM is accessed, a 5$6 precharge time must be secured. With this LSI, one T state is always inserted when DRAM space is accessed. From one to four T states can be selected by setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of T cycles according to the DRAM connected and the operating frequency of this LSI.
  • Page 208: Wait Control

    6.6.9 Wait Control There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and pin wait insertion using the :$,7 pin. Wait states are inserted to extend the &$6 assertion period in a read access to DRAM space, and to extend the write data setup time relative to the falling edge of &$6 in a write access.
  • Page 209 By program wait ø Row address Column address Address bus High Read Data bus Write High Data bus Note: Downward arrows indicate the timing of pin sampling. n = 2 to 5 Figure 6.26 Example of Wait State Insertion Timing (2-State Column Address Output) Rev.
  • Page 210 By program wait ø Row address Column address Address bus High Read Data bus Write High Data bus Note: Downward arrows indicate the timing of pin sampling. n = 2 to 5 Figure 6.27 Example of Wait State Insertion Timing (3-State Column Address Output) Rev.
  • Page 211: Byte Access Control

    6.6.10 Byte Access Control When DRAM with a ×16-bit configuration is connected, the 2-CAS access method is used for the control signals needed for byte access. Figure 6.28 shows the control timing for 2-CAS access, and figure 6.29 shows an example of 2-CAS DRAM connection. ø...
  • Page 212: Burst Operation

    This LSI 2-CAS type 16-Mbit DRAM 1-Mbyte × 16-bit configuration (Address shift size set to 10 bits) 10-bit column address Row address input: A9 to A0 Column address input: A9 to A0 D15 to D0 D15 to D0 Figure 6.29 Example of 2-CAS DRAM Connection 6.6.11 Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting a...
  • Page 213 ø Row address Column address 1 Column address 2 Address bus High Read Data bus Write High Data bus Note: n = 2 to 5 Figure 6.30 Operation Timing in Fast Page Mode (RAST = 0, CAST = 0) Rev. 1.0, 09/01, page 169 of 904...
  • Page 214 ø Row address Column address 1 Column address 2 Address bus High Read Data bus Write High Data bus Note: n = 2 to 5 Figure 6.31 Operation Timing in Fast Page Mode (RAST = 0, CAST = 1) The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion method and timing are the same as for full access.
  • Page 215  the RCDM bit or BE bit is cleared to 0 If a transition is made to the all-module-clocks-stopped mode in the 5$6 down state, the clock will stop with 5$6 low. To enter the all-module-clocks-stopped mode with 5$6 high, the RCDM bit must be cleared to 0 before executing the SLEEP instruction.
  • Page 216: Refresh Control

    • RAS Up Mode To select RAS up mode, clear the RCDM bit to 0 in DRAMCR. Each time access to DRAM space is interrupted and another space is accessed, the 5$6 signal goes high again. Burst operation is only performed if DRAM space is continuous. Figure 6.33 shows an example of the timing in RAS up mode.
  • Page 217 CAS-before-RAS (CBR) Refreshing: To select CBR refreshing, set the RFSHE bit to 1 in REFCR. With CBR refreshing, RTCNT counts up using the input clock selected by bits RTCK2 to RTCK0 in REFCR, and when the count matches the value set in RTCOR (compare match), refresh control is performed.
  • Page 218 ø Figure 6.36 CBR Refresh Timing A setting can be made in bits RCW1 and RCW0 in REFCR to delay 5$6 signal output by one to three cycles. Use bits RLW1 and RLW0 in REFCR to adjust the width of the 5$6 signal. The settings of bits RCW1, RCW0, RLW1, and RLW0 are valid only in refresh operations.
  • Page 219 Normal space access request ø A23 to A0 Refresh period Figure 6.38 Example of CBR Refresh Timing (CBRM = 1) Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM. To select self-refreshing, set the RFSHE bit and SLFRF bit to 1 in REFCR.
  • Page 220 Software standby ø High Note: n = 2 to 5 Figure 6.39 Self-Refresh Timing In some DRAMs provided with a self-refresh mode, the 5$6 signal precharge time immediately after self-refreshing is longer than the normal precharge time. A setting can be made in bits TPCS2 to TPCS0 in REFCR to make the precharge time immediately after self-refreshing from 1 to 7 states longer than the normal precharge time.
  • Page 221: Dmac And Exdmac Single Address Transfer Mode And Dram Interface

    Software DRAM space write standby ø Address bus Data bus Note: n = 2 to 5 Figure 6.40 Example of Timing when Precharge Time after Self-Refreshing Is Extended by 2 States Refreshing and All-Module-Clocks-Stopped Mode: In this LSI, if the ACSE bit is set to 1 in MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR = H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE, EXMSTPCR = H'FFFF), and a transition is made to the...
  • Page 222 When DDS = 1 or EDDS = 1: Burst access is performed by determining the address only, irrespective of the bus master. With the DRAM interface, the '$&. or ('$&. output goes low from the T state. Figure 6.41 shows the '$&. or ('$&. output timing for the DRAM interface when DDS = 1 or EDDS = 1.
  • Page 223 In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used when accessing DRAM space. Figure 6.42 shows the '$&. or ('$&. output timing for the DRAM interface when DDS = 0 or EDDS = 0. ø...
  • Page 224: Synchronous Dram Interface

    Synchronous DRAM Interface In the H8S/2378R Series, external address space areas 2 to 5 can be designated as continuous synchronous DRAM space, and synchronous DRAM interfacing performed. The synchronous DRAM interface allows synchronous DRAM to be directly connected to this LSI. A synchronous DRAM space of up to 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR.
  • Page 225: Address Multiplexing

    6.7.2 Address Multiplexing With continuous synchronous DRAM space, the row address and column address are multiplexed. In address multiplexing, the size of the shift of the row address is selected with bits MXC2 to MXC0 in DRAMCR. The address-precharge-setting command (Prechrge-sel) can be output on the upper column address.
  • Page 226: Data Bus

    6.7.3 Data Bus If the ABW2 bit in ABWCR corresponding to an area designated as continuous synchronous DRAM space is set to 1, area 2 to 5 are designated as 8-bit continuous synchronous DRAM space; if the bit is cleared to 0, the areas are designated as 16-bit continuous synchronous DRAM space. In 16-bit continuous synchronous DRAM space, ×16-bit configuration synchronous DRAM can be connected directly.
  • Page 227 Table 6.9 Synchronous DRAM Interface Pins With Synchronous DRAM Setting Name Function &65 Row address strobe Output Row address strobe when areas 2 to 5 are designated as continuous synchronous DRAM space &66 &$6 Column address strobe Output Column address strobe when areas 2 to 5 are designated as continuous synchronous DRAM space...
  • Page 228: Synchronous Dram Clock

    6.7.5 Synchronous DRAM Clock When the DCTL pin is fixed to 1, synchronous clock (SDRAMφ) is output from the &68 pin. When the frequency multiplication factor of the PLL circuit of this LSI is set to ×1 or ×2, SDRAMφ is 90° phase shift from φ. Therefore, a stable margin is ensured for the synchronous DRAM that operates at the rising edge of clocks.
  • Page 229 ø SDRAMø Address bus Column address Row address Column address Precharge-sel Row address Read High DQMU, DQML Data bus PALL ACTV READ Write High DQMU, DQML Data bus PALL ACTV WRIT Figure 6.44 Basic Access Timing of Synchronous DRAM (CAS Latency 1) Rev.
  • Page 230: Cas Latency Control

    6.7.7 CAS Latency Control CAS latency is controlled by settings of the W22 to W20 bits of WTCRB. Set the CAS latency count, as shown in table 6.10, by the setting of synchronous DRAM. Depending on the setting, the CAS latency control cycle (T ) is inserted.
  • Page 231 ø SDRAMø Address bus Column address Row address Column address Precharge-sel Row address Read High DQMU, DQML Data bus PALL ACTV READ Write High DQMU, DQML Data bus PALL ACTV WRIT Figure 6.45 CAS Latency Control Timing (SDWCD = 0, CAS Latency 3) Rev.
  • Page 232: Row Address Output State Control

    6.7.8 Row Address Output State Control When the command interval specification from the ACTV command to the next READ/WRIT command cannot be satisfied, 1 to 3 states (Trw) that output the NOP command can be inserted between the Tr cycle that outputs the ACTV command and the Tc1 cycle that outputs the column address by setting the RCD1 and RCD0 bits of DRACCR.
  • Page 233 ø ø SDRAM Column Address bus Row address Column address address Row address Precharge-sel Read High DQMU, DQML Data bus PALL ACTV READ Write High DQMU, DQML Data bus PALL ACTV WRIT Figure 6.46 Example of Access Timing when Row Address Output Hold State is 1 State (RCD1 = 0, RCD0 = 1, SDWCD = 0, CAS Latency 2) Rev.
  • Page 234: Precharge State Count

    6.7.9 Precharge State Count When the interval specification from the PALL command to the next ACTV/REF command cannot be satisfied, from one to four T states can be selected by setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of T cycles according to the synchronous DRAM connected and the operating frequency of this LSI.
  • Page 235 The setting of bits TPC1 and TPC0 is also valid for T states in refresh cycles. ø ø SDRAM Address bus Column address Row address Column address Row address Precharge-sel Read High DQMU, DQML Data bus PALL ACTV READ Write High DQMU, DQML Data bus...
  • Page 236: Bus Cycle Control In Write Cycle

    6.7.10 Bus Cycle Control in Write Cycle By setting the SDWCD bit of the DRACCR to 1, the CAS latency control cycle (Tc1) that is inserted by the WTCRB register in the write access of the synchronous DRAM can be disabled. Disabling the CAS latency control cycle can reduce the write-access cycle count as compared to synchronous DRAM read access.
  • Page 237: Byte Access Control

    6.7.11 Byte Access Control When synchronous DRAM with a ×16-bit configuration is connected, DQMU and DQML are used for the control signals needed for byte access. Figures 6.49 and 6.50 show the control timing for DQM, and figure 6.51 shows an example of connection of byte control by DQMU and DQML.
  • Page 238 ø SDRAMø Address bus Column address Row address Column address Precharge-sel Row address High DQMU High DQML Upper data bus High-Z Lower data bus PALL ACTV READ Figure 6.50 DQMU and DQML Control Timing (Lower Byte Read Access: CAS Latency 2) Rev.
  • Page 239: Burst Operation

    16-Mbit synchronous DRAM This LSI 1 Mword × 16 bits × 4-bank configuration (Address shift size set to 8 bits) 8-bit column address (DQMU) DQMU (DQML) DQML (SDRAMø) A13 (BS1) A12 (BS0) Row address input: A11 to A0 Column address input: A7 to A0 Bank select address: A13/A12...
  • Page 240 DQM has the 2-cycle latency when synchronous DRAM is read. Therefore, the DQM signal cannot be specified to the Tc2 cycle data output if Tc1 cycle is performed for second or following column address when the CAS latency is set to 1 to issue the READ command. Do not set the BE bit to 1 when synchronous DRAM of CAS latency 1 is connected.
  • Page 241 ø ø SDRAM Column Address bus Row address Column address Column address 2 address 1 Row address Precharge-sel Read High DQMU, DQML Data bus PALL ACTV READ READ Write High DQMU, DQML Data bus PALL ACTV WRIT WRIT Figure 6.52 Operation Timing of Burst Access (BE = 1, SDWCD = 0, CAS Latency 2) RAS Down Mode: Even when burst operation is selected, it may happen that access to continuous synchronous DRAM space is not continuous, but is interrupted by access to another space.
  • Page 242 Note, however, the next continuous synchronous DRAM space access is a full access if: • a refresh operation is initiated in the RAS down state • self-refreshing is performed • the chip enters software standby mode • the external bus is released •...
  • Page 243: Refresh Control

    6.7.13 Refresh Control This LSI is provided with a synchronous DRAM refresh control function. Auto refreshing is used. In addition, self-refreshing can be executed when the chip enters the software standby state. Refresh control is enabled when any area is designated as continuous synchronous DRAM space in accordance with the setting of bits RMTS2 to RMTS0 in DRAMCR.
  • Page 244 T Rp T Rr T Rc1 T Rc2 SDRAM Address bus Precharge-sel High PALL Figure 6.54 Auto Refresh Timing When the interval specification from the PALL command to the REF command cannot be satisfied, setting the RCW1 and RCW0 bits of REFCR enables one to three wait states to be inserted after the T cycle that is set by the TPC1 and TPC0 bits of DRACCR.
  • Page 245 ø SDRAMø Address bus Precharge-sel High PALL Figure 6.55 Auto Refresh Timing (TPC = 1, TPC0 = 1, RCW1 = 0, RCW0 = 1) When the interval specification from the REF command to the ACTV cannot be satisfied, setting the RLW1 and RLW0 bits of REFCR enables one to three wait states to be inserted in the refresh cycle.
  • Page 246 ø SDRAMø Address bus Precharge-sel High PALL Figure 6.56 Auto Refresh Timing (TPC = 0, TPC0 = 0, RLW1 = 0, RLW0 = 1) Self-Refreshing: A self-refresh mode (battery backup mode) is provided for synchronous DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the synchronous DRAM.
  • Page 247 Software standby SDRAMø Address bus Precharge-sel PALL SELF Figure 6.57 Self-Refresh Timing (TPC1 = 1, TPC0 = 0, RCW1 = 0, RCW0 = 0, RLW1 = 0, RLW0 = 0) In some synchronous DRAMs provided with a self-refresh mode, the interval between clearing self-refreshing and the next command is specified.
  • Page 248: Mode Register Setting Of Synchronous Dram

    Continuous synchronous DRAM space write Software standby ø ø SDRAM Address bus Column address Row address Column address Precharge-sel Row address DQMU, DQML Data bus PALL ACTV Figure 6.58 Example of Timing when Precharge Time after Self-Refreshing Is Extended by 2 States (TPCS2 to TPCS0 = H'2, TPC1 = 0, TPC0 = 0, CAS Latency 2) Refreshing and All-Module-Clocks-Stopped Mode: In this LSI, if the ACSE bit is set to 1 in MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR = H'FFFF) or for operation of the 8-bit...
  • Page 249 by writing to the continuous synchronous DRAM space of address H'400000 + X for 8-bit bus configuration synchronous DRAM and by writing to the continuous synchronous DRAM space of address H'400000 + 2X for 16-bit bus configuration synchronous DRAM. The value of the address signal is fetched at the issuance time of the MRS command as the setting value of the mode register in the synchronous DRAM.
  • Page 250: Dmac And Exdmac Single Address Transfer Mode And Synchronous Dram Interface

    6.7.15 DMAC and EXDMAC Single Address Transfer Mode and Synchronous DRAM Interface When burst mode is selected on the synchronous DRAM interface, the '$&. and ('$&. output timing can be selected with the DDS and EDDS bits in DRAMCR. When continuous synchronous DRAM space is accessed in DMAC/EXDMAC single address mode at the same time, these bits select whether or not burst access is to be performed.
  • Page 251 ø SDRAMø Address bus Column address Row address Column address Precharge-sel Row address Read High DQMU, DQML Data bus PALL ACTV READ Write High DQMU, DQML Data bus PALL ACTV WRIT Figure 6.60 Example of '$&. '$&./('$&. ('$&. Output Timing when DDS = 1 or EDDS = 1 '$&.
  • Page 252 When DDS = 0 or EDDS = 0: When continuous synchronous DRAM space is accessed in DMAC or EXDMAC single address transfer mode, full access (normal access) is always performed. With the synchronous DRAM interface, the '$&. or ('$&. output goes low from the T state.
  • Page 253 ø SDRAMø Address bus Column address Row address Column address Precharge-sel Row address Read High DQMU, DQML Data bus PALL ACTV READ Write High DQMU, DQML Data bus PALL ACTV WRIT Figure 6.61 Example of '$&. '$&./('$&. ('$&. Output Timing when DDS = 0 or EDDS = 0 '$&.
  • Page 254 (2) Read Data Extension If the CKSPE bit is set to 1 in DRACCR when the continuous synchronous DRAM space is read- accessed in DMAC/EXDMAC single address mode, the establishment time for the read data can be extended by clock suspend mode. The number of states for insertion of the read data extension cycle (Tsp) is set in bits RDXC1 and RDXC0 in DRACCR.
  • Page 255: Burst Rom Interface

    Burst ROM Interface In this LSI, external address space areas 0 and 1 can be designated as burst ROM space, and burst ROM interfacing performed. The burst ROM space enables ROM with burst access capability to be accessed at high speed. Areas 1 and 0 can be designated as burst ROM space by means of bits BSRM1 and BSRM0 in BROMCR.
  • Page 256 Full access Burst access ø Upper address bus Lower address bus Data bus Note: n = 1 and 0 Figure 6.63 Example of Burst ROM Access Timing (ASTn = 1, 2-State Burst Cycle) Rev. 1.0, 09/01, page 212 of 904...
  • Page 257: Wait Control

    Full access Burst access ø Upper address bus Lower address bus Data bus Note: n = 1 and 0 Figure 6.64 Example of Burst ROM Access Timing (ASTn = 0, 1-State Burst Cycle) 6.8.2 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the :$,7 pin can be used in the initial cycle (full access) on the burst ROM interface.
  • Page 258: Idle Cycle

    Idle Cycle 6.9.1 Operation When this LSI accesses external address space, it can insert an idle cycle (T ) between bus cycles in the following three cases: (1) when read accesses in different areas occur consecutively, (2) when a write cycle occurs immediately after a read cycle, and (3) when a read cycle occurs immediately after a write cycle.
  • Page 259 Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1 in BCR, an idle cycle is inserted at the start of the write cycle. Figure 6.66 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle.
  • Page 260 Bus cycle A Bus cycle B Bus cycle A Bus cycle B ø ø Address bus Address bus (area A) (area A) (area B) (area B) Data bus Data bus Data collision Idle cycle Long output floating time (a) No idle cycle insertion (b) Idle cycle insertion (ICIS2 = 0) (ICIS2 = 1, initial value)
  • Page 261 Bus cycle A Bus cycle B Bus cycle A Bus cycle B ø ø Address bus Address bus (area A) (area A) (area B) (area B) Idle cycle Overlap period between (area B) may occur (b) Idle cycle insertion (a) No idle cycle insertion (ICIS1 = 1, initial value) (ICIS1 = 0) &6) and Read (5'...
  • Page 262 In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid and an idle cycle is inserted. The timing in this case is illustrated in figures 6.70 and 6.71. DRAM space read External read DRAM space read ø...
  • Page 263 Idle Cycle in Case of Continuous Synchronous DRAM Space Access after Normal Space Access: In a continuous synchronous DRAM space access following a normal space access, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads in different areas, for example, if the second read is a full access to continuous synchronous DRAM space, only Tp cycle is inserted, and Ti cycle is not.
  • Page 264 Continuous synchronous Continuous synchronous DRAM space read External space read DRAM space read ø Column Address bus Column address 1 External address Column address 2 address address Precharge-sel External address address High DQMU, DQML High Data bus PALL ACTV READ READ Idle cycle Figure 6.73 Example of Idle Cycle Operation in RAS Down Mode...
  • Page 265 Continuous synchronous Continuous synchronous DRAM space read External space read DRAM space read ø Column Address bus Column address 1 External address Column address 2 address address External address Precharge-sel address High DQMU, DQML High Data bus PALL ACTV READ READ Idle cycle Figure 6.74 Example of Idle Cycle Operation in RAS Down Mode...
  • Page 266 Continuous synchronous Continuous synchronous DRAM space read External space read DRAM space write ø Column Column address 1 External address Column address 2 Address bus address address External address Precharge-sel address High DQMU, DQML High Data bus PALL ACTV READ WRIT Idle cycle Figure 6.75 Example of Idle Cycle Operation in RAS Down Mode...
  • Page 267 DRAM space read External address space read DRAM space read ø Address bus Data bus Idle cycle Figure 6.76 Example of Idle Cycle Operation after DRAM Access (Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0) DRAM space read External address space write DRAM space read...
  • Page 268 • Normal space access after DRAM space write access While the ICIS2 bit is set to 1 in BCR and a normal space read access occurs after DRAM space write access, idle cycle is inserted in the first read cycle. The number of states of the idle cycle to be inserted is in accordance with the setting of the IDLC bit.
  • Page 269 Continuous synchronous Continuous synchronous DRAM space read External space read DRAM space read ø Column Column address 1 External address Column address 2 Address bus address address External address Precharge-sel address High DQMU, DQML Data bus PALL ACTV READ READ Idle cycle Figure 6.79 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space Read Access (Read between Different Area) (IDLC = 0, CAS Latency 2)
  • Page 270 Continuous synchronous Synchronous DRAM space write External address space read DRAM space read ø Column Column Address bus External address Column address 2 address address address Precharge-sel External address address High DQMU, DQML Data bus PALL ACTV NOP WRIT READ Idle cycle Figure 6.80 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space Write Access (IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2)
  • Page 271 Table 6.11 Idle Cycles in Mixed Accesses to Normal Space and DRAM Continuous Synchronous DRAM Space Previous Access Next Access ICIS2* ICIS1 ICIS0 DRMI IDLC Idle cycle Normal space read Normal space read — — — — Disabled (different area) —...
  • Page 272 Previous Access Next Access ICIS2* ICIS1 ICIS0 DRMI IDLC Idle cycle DRAM/continuous Normal space read — — — — Disabled synchronous — — — 1 state inserted DRAM* 2 states inserted space write DRAM/continuous — — — — Disabled synchronous DRAM* —...
  • Page 273 Continuous synchronous Continuous synchronous DRAM space read DRAM space write ø Column Column External address Address bus address address address Precharge-sel High DQMU, DQML Data bus PALL ACTV READ WRIT Idle cycle Figure 6.82 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and Write Accesses to Continuous Synchronous DRAM Space in RAS Down Mode (SDWCD = 1, CAS Latency 2) Rev.
  • Page 274: Pin States In Idle Cycle

    6.9.2 Pin States in Idle Cycle Table 6.12 shows the pin states in an idle cycle. Table 6.12 Pin States in Idle Cycle Pins Pin State A23 to A0 Contents of following bus cycle D15 to D0 High impedance &6Q (n = 7 to 0) High* 8&$6, /&$6 High*...
  • Page 275: Bus Release

    On-chip memory read Internal I/O register read External write cycle Internal address bus Internal memory Internal I/O register address Internal read signal External address A23 to A0 External space write D15 to D0 Figure 6.83 Example of Timing when Write Data Buffer Function is Used 6.11 Bus Release This LSI can release the external bus in response to a bus request from an external device.
  • Page 276 In the external bus released state, internal bus masters except the EXDMAC can perform accesses using the internal bus. When an internal bus master wants to make an external access, it temporarily defers initiation of the bus cycle, and waits for the bus request from the external bus master to be canceled.
  • Page 277: Pin States In External Bus Released State

    6.11.2 Pin States in External Bus Released State Table 6.13 shows pin states in the external bus released state. Table 6.13 Pin States in Bus Released State Pins Pin State A23 to A0 High impedance D15 to D0 High impedance &6Q (n = 7 to 0) High impedance 8&$6, /&$6...
  • Page 278: Transition Timing

    6.11.3 Transition Timing Figure 6.84 shows the timing for transition to the bus released state. External space access cycle cycle External bus released state ø High-Z Address bus High-Z Data bus High-Z High-Z High-Z [1] Low level of signal is sampled at rise of ø. [2] Bus control signal returns to be high at end of external space access cycle.
  • Page 279 Figure 6.85 shows the timing for transition to the bus released state with the synchronous DRAM interface. External space read cycle External bus released state ø SDRAMø High-Z Address bus High-Z Data bus High-Z Precharge-sel address High-Z High-Z High-Z High-Z High-Z DQMU, DQML PALL...
  • Page 280: Bus Arbitration

    6.12 Bus Arbitration This LSI has a bus arbiter that arbitrates bus master operations (bus arbitration). There are four bus masters—the CPU, DTC, DMAC, and EXDMAC—that perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal.
  • Page 281 CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, DMAC, or EXDMAC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is as follows: •...
  • Page 282: Bus Controller Operation In Reset

    External Bus Release: When the %5(4 pin goes low and an external bus release request is issued while the BRLE bit is set to 1 in BCR, a bus request is sent to the bus arbiter. External bus release can be performed on completion of an external bus cycle. 6.13 Bus Controller Operation in Reset In a reset, this LSI, including the bus controller, enters the reset state immediately, and any...
  • Page 283: Breqo Output Timing

    %5(42 Output Timing %5(42 %5(42 %5(42 6.14.4 When the BREQOE bit is set to 1 and the %5(42 signal is output, %5(42 may go low before the %$&. signal. This will occur if the next external access request or CBR refresh request occurs while internal bus arbitration is in progress after the chip samples a low level of %5(4.
  • Page 284 Rev. 1.0, 09/01, page 240 of 904...
  • Page 285: Section 7 Dma Controller (Dmac)

    Section 7 DMA Controller (DMAC) This LSI has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4 channels. Features • Choice of short address mode or full address mode Short address mode Maximum of 4 channels can be used Dual address mode or single address mode can be selected In dual address mode, one of the two addresses, transfer source and transfer destination, is specified as 24 bits and the other as 16 bits...
  • Page 286 A block diagram of the DMAC is shown in figure 7.1. Internal address bus Internal interrupts TGI0A Address buffer TGI1A TGI2A Processor TGI3A TGI4A TGI5A MAR_0AH MAR_0AL TXI0 IOAR_0A RXI0 Control logic TXI1 ETCR_0A RXI1 MAR_0BH MAR_0BL External pins IOAR_0B ETCR_0B DMAWER MAR_1AH...
  • Page 287: Input/Output Pins

    Input/Output Pins Table 7.1 summarizes the pins of the interrupt controller. Table 7.1 Pin Configuration Channel Pin Name Symbol Function '5(43 DMA request 0 Input Channel 0 external request DMA transfer acknowledge 0 '$&.3 Output Channel 0 single address transfer acknowledge 7(1'3 DMA transfer end 0 Output...
  • Page 288: Memory Address Registers (Mara And Marb)

    • DMA band control register H (DMABCRH) • DMA band control register L (DMABCRL) • DMA write enable register (DMAWER) • DMA terminal control register (DMATCR) The functions of MAR, IOAR, ETCR, DMACR, and DMABCR differ according to the transfer mode (short address mode or full address mode).
  • Page 289: I/O Address Registers (Ioara And Ioarb)

    MAR is not initialized by a reset or in standby mode. Short Address Mode: In short address mode, MARA and MARB operate independently. Whether MAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. MAR is incremented or decremented each time a byte or word transfer is executed, so that the address specified by MAR is constantly updated.
  • Page 290 Short Address Mode: The function of ETCR in sequential mode and idle mode differs from that in repeat mode. In sequential mode and idle mode, ETCR functions as a 16-bit transfer counter. ETCR is decremented by 1 each time a transfer is performed, and when the count reaches H'00, the DTE bit in DMABCRL is cleared, and transfer ends.
  • Page 291: Dma Control Registers (Dmacra And Dmacrb)

    7.3.4 DMA Control Registers (DMACRA and DMACRB) DMACR controls the operation of each DMAC channel. The DMA has four DMACR registers: DMACR_0A in channel 0 (channel 0A), DMACR_0B in channel 0 (channel 0B), DMACR_1A in channel 1 (channel 1A), and DMACR_1B in channel 1 (channel 1B).
  • Page 292 Bit Name Initial Value Description Repeat Enable Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle, or repeat) in which transfer is to be performed. • When DTIE = 0 (no transfer end interrupt) 0: Transfer in sequential mode 1: Transfer in repeat mode •...
  • Page 293 Bit Name Initial Value Description • Channel A 0000: Setting prohibited 0001: Activated by A/D converter conversion end interrupt 0010: Setting prohibited 0011: Setting prohibited 0100: Activated by SCI channel 0 transmission complete interrupt 0101: Activated by SCI channel 0 reception complete interrupt 0110: Activated by SCI channel 1 transmission complete interrupt...
  • Page 294 Bit Name Initial Value Description • Channel B 0000: Setting prohibited 0001: Activated by A/D converter conversion end interrupt 0010: Activated by '5(4 pin falling edge input (detected as a low level in the first transfer after transfer is enabled) 0011: Activated by '5(4 pin low-level input 0100: Activated by SCI channel 0 transmission complete interrupt...
  • Page 295 Full Address Mode: • DMACR_0A and DMACR_1A Bit Name Initial Value Description DTSZ Data Transfer Size Selects the size of data to be transferred at one time. 0: Byte-size transfer 1: Word-size transfer SAID Source Address Increment/Decrement SAIDE Source Address Increment/Decrement Enable These bits specify whether source address register MARA is to be incremented, decremented, or left unchanged, when data...
  • Page 296 Bit Name Initial Value Description  Reserved These bits can be read from or written to. Legend x: Don't care • DMACR_0B and DMACR_1B Bit Name Initial Value Description  Reserved These bits can be read from or written to. DAID Destination Address Increment/Decrement DAIDE...
  • Page 297 Bit Name Initial Value Description • Normal Mode 0000: Setting prohibited 0001: Setting prohibited 0010: Activated by '5(4 pin falling edge input 0011: Activated by '5(4 pin low-level input 010x: Setting prohibited 0110: Auto-request (cycle steal) 0111: Auto-request (burst) 1xxx: Setting prohibited •...
  • Page 298: Dma Band Control Registers H And L (Dmabcrh And Dmabcrl)

    Bit Name Initial Value Description The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.12, Multi-Channel Operation. Legend x: Don't care 7.3.5...
  • Page 299 Bit Name Initial Value Description SAE0 Single Address Enable 0 Specifies whether channel 0B is to be used for transfer in dual address mode or single address mode. This bit is invalid in full address mode. 0: Dual address mode 1: Single address mode DTA1B Data Transfer Acknowledge 1B...
  • Page 300 • DMABCRL Bit Name Initial Value Description DTE1B Data Transfer Enable 1B DTE1A Data Transfer Enable 1A DTE0B Data Transfer Enable 0B DTE0A Data Transfer Enable 0A If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC.
  • Page 301 Bit Name Initial Value Description DTIE1B Data Transfer End Interrupt Enable 1B DTIE1A Data Transfer End Interrupt Enable 1A DTIE0B Data Transfer End Interrupt Enable 0B DTIE0A Data Transfer End Interrupt Enable 0A These bits enable or disable an interrupt to the CPU or DTC when transfer ends.
  • Page 302 Full Address Mode: • DMABCRH Bit Name Initial Value Description FAE1 Full Address Enable 1 Specifies whether channel 1 is to be used in short address mode or full address mode. In full address mode, channels 1A and 1B are used together as channel 1.
  • Page 303 Bit Name Initial Value Description DTA1 Data Transfer Acknowledge 1 These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR of channel 1. It the DTA1 bit is set to 1 when DTE1 = 1, the internal interrupt source is cleared automatically by DMA transfer.
  • Page 304 Bit Name Initial Value Description DTA0 Data Transfer Acknowledge 0 These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR of channel 0. It the DTA0 bit is set to 1 when DTE0 = 1, the internal interrupt source is cleared automatically by DMA transfer.
  • Page 305 • DMABCRL Bit Name Initial Value Description DTME1 Data Transfer Master Enable 1 Together with the DTE1 bit, this bit controls enabling or disabling of data transfer on channel 1. When both the DTME1 bit and DTE1 bit are set to 1, transfer is enabled for channel If channel 1 is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME1 bit is cleared, the transfer is interrupted,...
  • Page 306 Bit Name Initial Value Description DTE1 Data Transfer Enable 1 Enables or disables DMA transfer for the activation source selected by the DTF3 to DTF0 bits in DMACR of channel 1. When DTE1 = 0, data transfer is disabled and the activation source is ignored.
  • Page 307 Bit Name Initial Value Description DTME0 Data Transfer Master Enable 0 Together with the DTE0 bit, this bit controls enabling or disabling of data transfer on channel 0. When both the DTME0 bit and DTE0 bit are set to 1, transfer is enabled for channel If channel 0 is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME0 bit is cleared, the transfer is interrupted,...
  • Page 308 Bit Name Initial Value Description DTE0 Data Transfer Enable 0 Enables or disables DMA transfer for the activation source selected by the DTF3 to DTF0 bits in DMACR of channel 0. When DTE0 = 0, data transfer is disabled and the activation source is ignored.
  • Page 309 Bit Name Initial Value Description DTIE1A Data Transfer End Interrupt Enable 1A Enables or disables an interrupt to the CPU or DTC when transfer ends. If the DTIE1A bit is set to 1 when DTE1 = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC.
  • Page 310: Dma Write Enable Register (Dmawer)

    7.3.6 DMA Write Enable Register (DMAWER) The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and then reactivate the DTC. DMAWER applies restrictions for changing all bits of DMACR, and specific bits for DMATCR and DMABCR for the specific channel, to prevent inadvertent rewriting of registers other than those for the channel concerned.
  • Page 311 MAR_0A First transfer area IOAR_0A ETCR_0A MAR_0B IOAR_0B ETCR_0B MAR_1A IOAR_1A ETCR_1A MAR_1B IOAR_1B ETCR_1B DMAWER DMATCR DMACR_0A DMACR_0B DMACR_1A DMACR_1B Second transfer area DMABCR using chain transfer Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A) Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the DMAWER settings.
  • Page 312: Dma Terminal Control Register (Dmatcr)

    7.3.7 DMA Terminal Control Register (DMATCR) DMATCR controls enabling or disabling of output from the DMAC transfer end pin. A port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit. Bit Name Initial Value Description ...
  • Page 313: Activation Sources

    Activation Sources DMAC activation sources consist of internal interrupt requests, external requests, and auto- requests. The DMAC activation sources that can be specified depend on the transfer mode and channel, as shown in table 7.3. Table 7.3 DMAC Activation Sources Short Address Mode Full Address Mode Block...
  • Page 314: Activation By External Request

    If the DMAC is activated by a CPU interrupt source or an interrupt request that is not used as a DTC activation source (DTA = 1), the interrupt request flag is cleared automatically by the DMA transfer. With TXI and RXI interrupts, however, the interrupt source flag is not cleared unless the relevant register is accessed in a DMA transfer.
  • Page 315: Operation

    Operation 7.5.1 Transfer Modes Table 7.4 lists the DMAC transfer modes. Table 7.4 DMAC Transfer Modes Transfer Mode Transfer Source Remarks • • Short Dual address mode TPU channel 0 to 5 Up to 4 channels can address compare match/input operate independently (1) Sequential mode mode...
  • Page 316 Transfer Mode Transfer Source Remarks • Single address mode External request • 1-byte or 1-word transfer for a single transfer request • 1-bus cycle transfer by means of '$&. pin instead of using address for specifying I/O • Sequential mode, idle mode, or repeat mode can be specified •...
  • Page 317: Sequential Mode

    7.5.2 Sequential Mode Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR.
  • Page 318 Transfer Address T IOAR 1 byte or word transfer performed in response to 1 transfer request Legend Address T = L DTID DTSZ Address B = L + (–1) · (2 · (N – 1)) Where : L = Value set in MAR Address B N = Value set in ETCR Figure 7.3 Operation in Sequential Mode...
  • Page 319: Idle Mode

    [1] Set each bit in DMABCRH. Sequential mode setting • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Set DMABCRH [2] Set the transfer source address and transfer destination address in MAR and IOAR.
  • Page 320 by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.6 summarizes register functions in idle mode. Table 7.6 Register Functions in Idle Mode Function Register DTDIR = 0 DTDIR = 1 Initial Setting Operation Source Destination Start address of...
  • Page 321: Repeat Mode

    [1] Set each bit in DMABCRH. Idle mode setting • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Set DMABCRH [2] Set the transfer source address and transfer destination address in MAR and IOAR.
  • Page 322 their original settings and operation continues. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.7 summarizes register functions in repeat mode. Table 7.7 Register Functions in Repeat Mode Function Register DTDIR = 0 DTDIR = 1 Initial Setting...
  • Page 323 not sent to the CPU or DTC. By setting the DTE bit to 1 again after it has been cleared, the operation can be restarted from the transfer after that terminated when the DTE bit was cleared. Figure 7.7 illustrates operation in repeat mode. Address T Transfer IOAR...
  • Page 324: Single Address Mode

    [1] Set each bit in DMABCRH. Repeat mode setting • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Set DMABCRH [2] Set the transfer source address and transfer destination address in MAR and IOAR.
  • Page 325 One address is specified by MAR, and the other is set automatically to the data transfer acknowledge pin ('$&.). The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.8 summarizes register functions in single address mode. Table 7.8 Register Functions in Single Address Mode Function...
  • Page 326 Transfer Address T 1 byte or word transfer performed in response to 1 transfer request Legend Address T = L DTID DTSZ Address B = L + (–1) · (2 · (N – 1)) Where : L = Value set in MAR Address B N = Value set in ETCR Figure 7.9 Operation in Single Address Mode (When Sequential Mode is Specified)
  • Page 327: Normal Mode

    [1] Set each bit in DMABCRH. Single address • Clear the FAE bit to 0 to select short address mode setting mode. • Set the SAE bit to 1 to select single address mode. • Specify enabling or disabling of internal Set DMABCRH interrupt clearing with the DTA bit.
  • Page 328 to a single transfer request, and this is executed the number of times specified in ETCRA. The transfer source is specified by MARA, and the transfer destination by MARB. Table 7.9 summarizes register functions in normal mode. Table 7.9 Register Functions in Normal Mode Register Function Initial Setting...
  • Page 329 Transfer Address T Address T Address B Address B Legend Address Address SAID DTSZ Address + SAIDE · (–1) · (2 · (N – 1)) DAID DTSZ Address + DAIDE · (–1) · (2 · (N – 1)) Where : = Value set in MARA = Value set in MARB = Value set in ETCRA...
  • Page 330: Block Transfer Mode

    [1] Set each bit in DMABCRH. Normal mode setting • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Set DMABCRH [2] Set the transfer source address in MARA, and the transfer destination address in MARB.
  • Page 331 ETCRB. The transfer source is specified by MARA, and the transfer destination by MARB. Either the transfer source or the transfer destination can be selected as a block area (an area composed of a number of bytes or words). Table 7.10 summarizes register functions in block transfer mode. Table 7.10 Register Functions in Block Transfer Mode Register Function...
  • Page 332 Address T Address T 1st block Block area Transfer Address B Consecutive transfer of M bytes or words is performed in response to one request 2nd block Nth block Address B Legend Address Address SAID DTSZ Address + SAIDE · (–1) ·...
  • Page 333 Address T Address T Block area 1st block Transfer Consecutive transfer Address B of M bytes or words is performed in response to one request 2nd block Nth block Address B Legend Address Address SAID DTSZ Address + SAIDE · (–1) ·...
  • Page 334 Figure 7.15 shows the operation flow in block transfer mode. Start (DTE = DTME = 1) Transfer request? Acquire bus Read address specified by MARA SAID DTSZ MARA = MARA + SAIDE·(–1) ·2 Write to address specified by MARB DAID DTSZ MARB = MARB + DAIDE·(–1) ·2...
  • Page 335 Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. Figure 7.16 shows an example of the setting procedure for block transfer mode. [1] Set each bit in DMABCRH.
  • Page 336: Basic Bus Cycles

    7.5.8 Basic Bus Cycles An example of the basic DMAC bus cycle timing is shown in figure 7.17. In this example, word- size transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed.
  • Page 337 read read read write write write dead ø Address bus Bus release Bus release Bus release Last transfer cycle release Figure 7.18 Example of Short Address Mode Transfer A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released.
  • Page 338 read write read write read write dead ø Address bus Bus release Bus release Bus release Last transfer cycle release Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal) A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released.
  • Page 339 read write read write read write dead ø Address bus Last transfer cycle Bus release Bus release Burst transfer Figure 7.20 Example of Full Address Mode Transfer (Burst Mode) In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle.
  • Page 340 read write read write dead read write read write dead ø Address bus Bus release Block transfer Bus release Last block transfer release Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode) A one-block transfer is performed for a single transfer request, and after the transfer the bus is released.
  • Page 341 Bus release read write release read write release ø Address Transfer source Transfer destination Transfer source Transfer destination Idle Read Write Idle Read Write Idle control Channel Request clear period Request Request clear period Request Minimum Minimum of 2 cycles of 2 cycles Acceptance resumes Acceptance resumes...
  • Page 342 1 block transfer 1 block transfer Bus release read write dead release read write dead release ø Address Transfer source Transfer destination Transfer source Transfer destination Idle Read Write Dead Idle Read Write Dead Idle control Request clear period Request clear period Channel Request Request...
  • Page 343 release read write release read write release ø Address Transfer source Transfer destination Transfer source Transfer destination Idle Read Write Idle Read Write Idle control Channel Request clear period Request clear period Request Request Minimum Minimum of 2 cycles of 2 cycles Acceptance resumes Acceptance resumes Acceptance after transfer enabling;...
  • Page 344: Dma Transfer (Single Address Mode) Bus Cycles

    1 block transfer 1 block transfer Bus release read write dead release read write dead release ø Address Transfer source Transfer source Transfer destination Transfer destination Idle Read Write Dead Idle Read Write Dead Idle control Request clear period Request clear period Channel Request Request...
  • Page 345 DMA read DMA read DMA read DMA read dead ø Address bus Last transfer release release release release cycle release Figure 7.26 Example of Single Address Mode Transfer (Byte Read) Figure 7.27 shows a transfer example in which 7(1' output is enabled and word-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device.
  • Page 346 In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. Single Address Mode (Write): Figure 7.28 shows a transfer example in which 7(1' output is enabled and byte-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space.
  • Page 347 DMA write DMA write DMA write dead ø Address bus Last transfer release release release cycle release Figure 7.29 Example of Single Address Mode Transfer (Word Write) A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released.
  • Page 348 Bus release DMA single Bus release DMA single Bus release ø Transfer source/ Transfer source/ Address bus destination destination DMA control Idle Single Idle Single Idle Request clear Request clear Channel Request Request period period Minimum of Minimum of 2 cycles 2 cycles Acceptance resumes Acceptance resumes...
  • Page 349 Figure 7.31 shows an example of single address mode transfer activated by the '5(4 pin low level. Bus release DMA single Bus release DMA single release ø Transfer source/ Transfer source/ Address bus destination destination Single DMA control Idle Idle Single Idle Request clear...
  • Page 350: Write Data Buffer Function

    7.5.11 Write Data Buffer Function DMAC internal-to-external dual address transfers and single address transfers can be executed at high speed using the write data buffer function, enabling system throughput to be improved. When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles and internal accesses (on-chip memory or internal I/O registers) are executed in parallel.
  • Page 351: Multi-Channel Operation

    read single read single read ø Internal address Internal read signal External address Figure 7.33 Example of Single Address Transfer Using Write Data Buffer Function When the write data buffer function is activated, the DMAC recognizes that the bus cycle concerned has ended, and starts the next operation.
  • Page 352: Relation Between Dmac And External Bus Requests, Refresh Cycles, And Exdmac

    read DMA read DMA write DMA read DMA write DMA read DMA write ø Address bus DMA control Idle Read Write Idle Read Write Idle Read Write Read Channel 0A Request clear Request clear Request Selection Channel 0B hold Request clear Request Request Non-...
  • Page 353: Dmac And Nmi Interrupts

    7.5.14 DMAC and NMI Interrupts When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An NMI interrupt does not affect the operation of the DMAC in other modes. In full address mode, transfer is enabled for a channel when both the DTE bit and DTME bit are set to 1.
  • Page 354: Clearing Full Address Mode

    [1] Clear the DTE bit in DMABCRL to 0. Forced termination To prevent interrupt generation after forced of DMAC termination of DMAC operation, clear the DTIE bit to 0 at the same time. Clear DTE bit to 0 Forced termination Figure 7.36 Example of Procedure for Forcibly Terminating DMAC Operation 7.5.16 Clearing Full Address Mode...
  • Page 355: Interrupt Sources

    [1] Clear both the DTE bit and DTME bit in Clearing full DMABCRL to 0, or wait until the transfer ends address mode and the DTE bit is cleared to 0, then clear the DTME bit to 0. Also clear the corresponding DTIE bit to 0 at the same time.
  • Page 356: Usage Notes

    Enabling or disabling of each interrupt source is set by means of the DTIE bit in DMABCRL for the corresponding channel in DMABCRL, and interrupts from each source are sent to the interrupt controller independently. The priority of transfer end interrupts on each channel is decided by the interrupt controller, as shown in table 7.12.
  • Page 357 DMA last transfer cycle DMA transfer cycle dead DMA read DMA read DMA write DMA write ø DMA Internal Transfer Transfer Transfer Transfer destination source source destination address Read Idle Idle Write Idle Read DMA control Write Dead DMA register [2'] operation [1] Transfer source address register MAR operation (incremented/decremented/fixed)
  • Page 358: Module Stop

    7.7.2 Module Stop When the MSTP13 bit in MSTPCRH is set to 1, the DMAC clock stops, and the module stop state is entered. However, 1 cannot be written to the MSTP13 bit if any of the DMAC channels is enabled.
  • Page 359: Activation By Falling Edge On Dreq Pin

    4. Bus release cycle 5. CBR refresh cycle Figure 7.41 shows an example in which a low level is not output from the 7(1' pin in case 2 above. If the last transfer cycle is an external address cycle, a low level is output at the 7(1' pin in synchronization with the bus cycle.
  • Page 360: Activation Source Acceptance

    After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer is enabled is performed on detection of a low level. 7.7.6 Activation Source Acceptance At the start of activation source acceptance, a low level is detected in both '5(4 pin falling edge sensing and low level sensing.
  • Page 361: Section 8 Exdma Controller

    Section 8 EXDMA Controller This LSI has a built-in dual-channel external bus transfer DMA controller (EXDMAC). The EXDMAC can carry out high-speed data transfer, in place of the CPU, to and from external devices and external memory with a DACK (DMA transfer notification) facility. Features •...
  • Page 362 Bus controller Data buffer External pins Control logic Address buffer Processor EDSAR Interrupt request EDDAR signals to CPU EDMDR for individual EDTCR EDACR channels Internal data bus Legend EDSAR: EXDMA source address register EDDAR: EXDMA destination address register EDTCR: EXDMA transfer count register EDMDR: EXDMA mode control register EDACR:...
  • Page 363: Input/Output Pins

    Input/Output Pins Table 8.1 summarizes the pins of the EXDMAC. Table 8.1 Pin Configuration Abbre- Channel Name viation Function ('5(45 EXDMA transfer request 2 Input Channel 2 external request ('$&.5 EXDMA transfer Output Channel 2 single address transfer acknowledge 2 acknowledge (7(1'5 EXDMA transfer end 2...
  • Page 364: Exdma Source Address Register (Edsar)

    8.3.1 EXDMA Source Address Register (EDSAR) EDSAR is a 32-bit readable/writable register that specifies the transfer source address. An address update function is provided that updates the register contents to the next transfer source address each time transfer processing is performed. In single address mode, the EDSAR value is ignored when a device with '$&.
  • Page 365: Exdma Transfer Count Register (Edtcr)

    8.3.3 EXDMA Transfer Count Register (EDTCR) EDTCR specifies the number of transfers. The function differs according to the transfer mode. Do not write to EDTCR for a channel on which EXDMA transfer is in progress. Normal Transfer Mode: Bit Name Initial Value Description —...
  • Page 366 Block Transfer Mode: Bit Name Initial Value Description — — Reserved These bits are always read as 0 and cannot be modified. Undefined Block Size These bits specify the block size (number of bytes or number of words) for block transfer. Setting H'01 specifies one as the block, while setting H'00 specifies the maximum block size, that is 256.
  • Page 367: Exdma Mode Control Register (Edmdr)

    8.3.4 EXDMA Mode Control Register (EDMDR) EDMDR controls EXDMAC operations. Bit Name Initial Value Description R/(W) EXDMA Active Enables or disables data transfer on the corresponding channel. When this bit is set to 1, this indicates that an EXDMA operation is in progress.
  • Page 368 Bit Name Initial Value Description R/(W)* Block Transfer Error Flag Flag that indicates the occurrence of an error during block transfer. If an NMI interrupt is generated during block transfer, the EXDMAC immediately terminates the EXDMA operation and sets this bit to 1. The address registers indicate the next transfer addresses, but the data for which transfer has been performed within the block size is lost.
  • Page 369 Bit Name Initial Value Description MDS1 Mode Select 1 and 0 MDS0 These bits specify the activation source, bus mode, and transfer mode. 00: Auto request, cycle steal mode, normal transfer mode 01: Auto request, burst mode, normal transfer mode 10: External request, cycle steal mode, normal transfer mode 11: External request, cycle steal mode, block...
  • Page 370 Bit Name Initial Value Description TCEIE Transfer Counter End Interrupt Enable Enables or disables transfer end interrupt requests by the transfer counter. When transfer ends according to the transfer counter while this bit is set to 1, the IRF bit is set to 1, indicating that an interrupt request has occurred.
  • Page 371: Exdma Address Control Register (Edacr)

    8.3.5 EXDMA Address Control Register (EDACR) EDACR specifies address register incrementing/decrementing and use of the repeat area function. Bit Name Initial Value Description SAT1 Source Address Update Mode SAT0 These bits specify incrementing/decrementing of the transfer source address (EDSAR). When an external device with DACK is designated as the transfer source in single address mode, the specification by these bits is ignored.
  • Page 372 Bit Name Initial Value Description Source Address Repeat Area SARA4 SARA3 These bits specify the source address (EDSAR) SARA2 repeat area. The repeat area function updates SARA1 the specified lower address bits, leaving the SARA0 remaining upper address bits always the same. A repeat area size of 2 bytes to 8 Mbytes can be specified.
  • Page 373 Bit Name Initial Value Description DAT1 Destination Address Update Mode DAT0 These bits specify incrementing/decrementing of the transfer destination address (EDDAR). When an external device with DACK is designated as the transfer destination in single address mode, the specification by these bits is ignored.
  • Page 374 Bit Name Initial Value Description DARA4 Destination Address Repeat Area DARA3 These bits specify the destination address DARA2 (EDDAR) repeat area. The repeat area function DARA1 updates the specified lower address bits, DARA0 leaving the remaining upper address bits always the same.
  • Page 375: Operation

    Operation 8.4.1 Transfer Modes The transfer modes of the EXDMAC are summarized in table 8.2. Table 8.2 EXDMAC Transfer Modes Address Registers Transfer Number of Transfer Mode Origin Transfers Source Destination Dual Normal Auto request mode Auto 1 to EDSAR EDDAR address transfer...
  • Page 376: Address Modes

    In block transfer mode, a transfer of the specified block size is executed in response to one transfer request. The block size can be from 1 to 256 bytes or words. Within a block, transfer can be performed at the same high speed as in block transfer mode. When the “no specification”...
  • Page 377 EXDMA EXDMA read cycle write cycle ø Address bus EDSAR EDDAR Figure 8.2 Example of Timing in Dual Address Mode Single Address Mode: In single address mode, the ('$&. signal is used instead of the source or destination address register to transfer data directly between an external device and external memory.
  • Page 378 External External address bus data bus Microcomputer External memory EXDMAC External device with DACK Data flow Figure 8.3 Data Flow in Single Address Mode Rev. 1.0, 09/01, page 334 of 904...
  • Page 379 Transfer from external memory to external device with DACK EXDMA cycle ø Address to external memory space Address bus EDSAR signal to external memory space Data output from external memory Data bus Transfer from external device with DACK to external memory EXDMA cycle ø...
  • Page 380: Dma Transfer Requests

    8.4.3 DMA Transfer Requests Auto Request Mode: In auto request mode, transfer request signals are automatically generated within the EXDMAC in cases where a transfer request signal is not issued from outside, such as in transfer between two memories, or between a peripheral module that is not capable of generating transfer requests and memory.
  • Page 381 If a transfer request occurs in another channel during DMA transfer, the bus is temporarily released, then transfer is performed on the channel for which the transfer request was issued. If there is no external space bus request from another bus master, a one-cycle bus release interval is inserted.
  • Page 382: Transfer Modes

    Bus cycle EXDMAC EXDMAC EXDMAC CPU cycle not generated Transfer conditions: Auto request mode, BGUP = 0 Bus cycle EXDMAC EXDMAC EXDMAC EXDMAC operates alternately with CPU Transfer conditions: Auto request mode, BGUP = 1 Figure 8.6 Examples of Timing in Burst Mode 8.4.5 Transfer Modes There are two transfer modes: normal transfer mode and block transfer mode.
  • Page 383 EXDMA Last EXDMA transfer cycle transfer cycle Bus cycle Read Write Read Write Transfer conditions: Dual address mode, auto request mode Bus cycle EXDMA EXDMA Transfer conditions: Single address mode, external request mode Figure 8.7 Examples of Timing in Normal Transfer Mode Block Transfer Mode: In block transfer mode, the number of bytes or words specified by the block size is transferred in response to one transfer request.
  • Page 384: Repeat Area Function

    Block transfer is aborted if an NMI interrupt is generated. See section 8.4.12, Ending DMA Transfer, for details. Figure 8.8 shows an example of DMA transfer timing in block transfer mode. One-block transfer cycle Bus cycle EXDMAC EXDMAC EXDMAC CPU cycle not generated Transfer conditions: ·...
  • Page 385 IRF bit is set to 1 and the EDA bit cleared to 0 in EDMDR, and transfer is terminated. If EDIE = 1 in EDMDR, an interrupt is requested. If the DARIE bit in EDACR is set to 1, the above applies to the destination address register.
  • Page 386: Registers During Dma Transfer Operation

    When lower 3 bits (8-byte area) of EDSAR are designated as repeat area (SARA4 to SARA0 = 3), and block size of 5 (EDTCR[23–16] = 5) is set in block transfer mode External memory Range of First block Second block EDSAR values transfer transfer...
  • Page 387 When EDSAR is read during a transfer operation, a longword access must be used. During a transfer operation, EDSAR may be updated without regard to accesses from the CPU, and the correct values may not be read if the upper and lower words are read separately. In a longword access, the EXDMAC buffers the EDSAR value to ensure that the correct value is output.
  • Page 388 In block transfer mode, the upper 8 bits are never updated, so there is no problem with using word access. Do not write to EDTCR for a channel on which a transfer operation is in progress. If there is contention between an address update associated with DMA transfer and a write by the CPU, the CPU write has priority.
  • Page 389 • When an NMI interrupt is generated, and transfer halts • A reset • Hardware standby mode • When 0 is written to the EDA bit, and transfer halts When transfer is halted by writing 0 to the EDA bit, the EDA bit remains at 1 during the DMA transfer period.
  • Page 390: Channel Priority Order

    of transfers is carried out, a block-size transfer is always executed, except in the event of a reset, transition to standby mode, or generation of an NMI interrupt. If an NMI interrupt is generated during block transfer, operation is halted midway through a block-size transfer and the EDA bit is cleared to 0, terminating the transfer operation.
  • Page 391 Channel 0 transfer Channel 1 transfer Channel 2 transfer ø Channel 0 Channel 1 Channel 2 Address bus release release Idle Channel 0 Channel 1 Channel 2 EXDMA control Request cleared Channel 0 Request Selected Request cleared Channel 1 held Request Request Channel 2...
  • Page 392 Conditions (1) Channel 0: Auto request, cycle steal mode Channel 1: External request, cycle steal mode, low level activation Channel 0 Channel 0 Channel 0 Channel 1 Channel 1 Channel 0 EDA bit Channel 1/ Conditions (2) Channel 1: External request, cycle steal mode, low level activation Channel 2: Auto request, cycle steal mode Channel 2 Channel 2...
  • Page 393: Exdmac Bus Cycles (Dual Address Mode)

    8.4.9 EXDMAC Bus Cycles (Dual Address Mode) Normal Transfer Mode (Cycle Steal Mode): Figure 8.15 shows an example of transfer when (7(1' output is enabled, and word-size, normal transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. After one byte or word has been transferred, the bus is released.
  • Page 394 DMA read DMA write DMA read DMA write DMA read DMA write ø Address bus Last transfer cycle release release Burst transfer Figure 8.16 Example of Normal Transfer Mode (Burst Mode) Transfer If an NMI interrupt is generated while a channel designated for burst transfer is enabled for transfer, the EDA bit is cleared and transfer is disabled.
  • Page 395 ('5(4 ('5(4 Pin Falling Edge Activation Timing: Figure 8.18 shows an example of normal mode ('5(4 ('5(4 transfer activated by the ('5(4 pin falling edge. DMA write Bus release Bus release DMA read DMA write Bus release DMA read ø Transfer Transfer Address bus...
  • Page 396 One block transfer One block transfer Bus release DMA read DMA write Bus release DMA read DMA write Bus release ø Transfer Transfer Address bus Transfer source Transfer source destination destination DMA control Idle Read Write Idle Read Write Idle Request clearance period Request clearance period Channel...
  • Page 397 Bus release DMA read DMA write Bus release DMA read DMA write Bus release ø Transfer Transfer Address bus Transfer source Transfer source destination destination DMA control Idle Read Write Idle Read Write Idle Channel Request clearance period Request clearance period Request Request Minimum 3 cycles...
  • Page 398: Exdmac Bus Cycles (Single Address Mode)

    One block transfer One block transfer Bus release DMA read DMA write Bus release DMA read DMA write Bus release ø Transfer Transfer Address bus Transfer source Transfer source destination destination DMA control Idle Read Write Idle Read Write Idle Request clearance period Request clearance period Channel...
  • Page 399 DMA read DMA read DMA read DMA read ø Address bus Bus release Bus release Bus release Bus release Last Bus release transfer cycle Figure 8.22 Example of Single Address Mode (Byte Read) Transfer Figure 8.23 shows an example of transfer when (7(1' output is enabled, and word-size, single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device.
  • Page 400 DMA write DMA write DMA write DMA write ø Address bus Bus release Bus release Bus release Bus release Last Bus release transfer cycle Figure 8.24 Example of Single Address Mode (Byte Write) Transfer Figure 8.25 shows an example of transfer when (7(1' output is enabled, and word-size, single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space.
  • Page 401 Bus release DMA single Bus release DMA single Bus release ø Transfer source/ Transfer source/ Address bus destination destination DMA control Idle Single Idle Single Idle Request Request clearance period clearance period Channel Request Request Minimum 3 cycles Minimum 3 cycles Acceptance Acceptance resumed...
  • Page 402 Bus release DMA single Bus release DMA single Bus release ø Transfer source/ Transfer source/ Address bus destination destination DMA control Idle Single Idle Single Idle Request Request clearance period clearance period Channel Request Request Minimum 3 cycles Minimum 3 cycles Acceptance Acceptance resumed...
  • Page 403: Examples Of Operation Timing In Each Mode

    8.4.11 Examples of Operation Timing in Each Mode Auto Request/Cycle Steal Mode/Normal Transfer Mode: When the EDA bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three cycles later. There is a one- cycle bus release interval between the end of a one-transfer-unit EXDMA cycle and the start of the next transfer.
  • Page 404 ø pin 1 bus cycle Last transfer cycle EXDMA single EXDMA single EXDMA single CPU cycle CPU cycle CPU cycle CPU cycle Bus cycle transfer cycle transfer cycle transfer cycle External External space External space External space space operation Figure 8.29 Auto Request/Cycle Steal Mode/Normal Transfer Mode (CPU Cycles/Single Address Mode) ø...
  • Page 405 Figures 8.31 to 8.34 show operation timing examples for various conditions. ø pin Last transfer cycle EXDMA EXDMA EXDMA EXDMA EXDMA EXDMA Bus cycle Repeated CPU cycle CPU cycle CPU cycle read write read write read write External External External space space space...
  • Page 406 ø pin Last transfer cycle 1 bus cycle EXDMA EXDMA EXDMA EXDMA EXDMA Bus cycle CPU cycle CPU cycle CPU cycle CPU cycle CPU cycle single cycle single cycle single cycle single cycle single cycle External External External External External space space space...
  • Page 407 If a transfer request is generated for another channel, an EXDMA cycle for the other channel is generated before the next EXDMA cycle. The ('5(4 pin sensing timing is different for low level sensing and falling edge sensing. The same applies to transfer request acceptance and transfer start timing. Figures 8.35 to 8.38 show operation timing examples for various conditions.
  • Page 408 ø pin 2 bus cycles Last transfer cycle EXDMA single EXDMA single CPU cycle CPU cycle CPU cycle CPU cycle CPU cycle CPU cycle Bus cycle transfer cycle transfer cycle External External External External External External space space space space space space operation...
  • Page 409 ø pin Original channel Original channel 1 cycle 1 cycle 3 cycles Other channel EXDMA transfer EXDMA EXDMA EXDMA EXDMA Bus release Bus cycle transfer cycle cycle read write read write release release Other channel Other channel Figure 8.38 External Request/Cycle Steal Mode/Normal Transfer Mode Contention with Another Channel/Dual Address Mode/Low Level Sensing External Request/Cycle Steal Mode/Block Transfer Mode: In block transfer mode, transfer of one block is performed continuously in the same way as in burst mode.
  • Page 410 Figure 8.39 External Request/Cycle Steal Mode/Block Transfer Mode (No Contention/Dual Address Mode/Low Level Sensing/BGUP = 0) Rev. 1.0, 09/01, page 366 of 904...
  • Page 411 Figure 8.40 External Request/Cycle Steal Mode/Block Transfer Mode (No Contention/Single Address Mode/Falling Edge Sensing/BGUP = 0) Rev. 1.0, 09/01, page 367 of 904...
  • Page 412 Figure 8.41 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 0) Rev. 1.0, 09/01, page 368 of 904...
  • Page 413 Figure 8.42 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Dual Address Mode/Low Level Sensing/BGUP = 1) Rev. 1.0, 09/01, page 369 of 904...
  • Page 414 Figure 8.43 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 1) Rev. 1.0, 09/01, page 370 of 904...
  • Page 415 Figure 8.44 External Request/Cycle Steal Mode/Block Transfer Mode (Contention with Another Channel/Dual Address Mode/Low Level Sensing) Rev. 1.0, 09/01, page 371 of 904...
  • Page 416: Ending Dma Transfer

    8.4.12 Ending DMA Transfer The operation for ending DMA transfer depends on the transfer end conditions. When DMA transfer ends, the EDA bit in EDMDR changes from 1 to 0, indicating that DMA transfer has ended. Transfer End by 1 → → → → 0 Transition of EDTCR: When the value of EDTCR changes from 1 to 0, DMA transfer ends on the corresponding channel and the EDA bit in EDMDR is cleared to 0.
  • Page 417: Relationship Between Exdmac And Other Bus Masters

    When transfer is aborted, register values are retained, and as the address registers indicate the next transfer addresses, transfer can be resumed by setting the EDA bit to 1 in EDMDR. If the BEF bit is 1 in EDMDR, transfer can be resumed from midway through a block. Hardware Standby Mode and Reset Input: The EXDMAC is initialized in hardware standby mode and by a reset.
  • Page 418 Interrupt sources can be enabled or disabled by means of the EDIE bit in EDMDR for the relevant channel, and can be sent to the interrupt controller independently. The relative priority order of the channels is determined by the interrupt controller (see table 8.4). Figure 8.45 shows the transfer end interrupt logic.
  • Page 419 Transfer end interrupt exception handling routine Transfer continuation Transfer restart after end of interrupt handling routine processing Clear IRF bit to 0 Change register settings End of interrupt handling Write 1 to EDA bit routine End of interrupt handling Change register settings routine (RTE instruction execution) Write 1 to EDA bit...
  • Page 420: Usage Notes

    Usage Notes 8.6.1 EXDMAC Register Access during Operation Except for clearing the EDA bit to 0 in EDMDR, settings should not be changed for a channel in operation (including the transfer standby state). Transfer must be disabled before changing a setting for an operational channel.
  • Page 421: Enabling Interrupt Requests When Irf = 1 In Edmdr

    When the EXDMAC is activated, make sure, if necessary, that a low level does not remain at the ('5(4 pin from the previous end of transfer, etc. 8.6.5 Enabling Interrupt Requests when IRF = 1 in EDMDR When transfer is started while the IRF bit is set to 1 in EDMDR, if the EDIE bit is set to 1 in EDMDR together with the EDA bit in EDMDR, enabling interrupt requests, an interrupt will be requested since EDIE = 1 and IRF = 1.
  • Page 422 Rev. 1.0, 09/01, page 378 of 904...
  • Page 423: Section 9 Data Transfer Controller (Dtc)

    Section 9 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 9.1 shows a block diagram of the DTC. The DTC’s register information is stored in the on- chip RAM.
  • Page 424: Register Configuration

    Internal address bus On-chip Interrupt controller Interrupt request CPU interrupt Internal data bus request Legend MRA, MRB : DTC mode registers A and B CRA, CRB : DTC transfer count registers A and B : DTC source address register : DTC destination address register DTCERA to DTCERG : DTC enable registers A to G DTVECR...
  • Page 425: Dtc Mode Register A (Mra)

    9.2.1 DTC Mode Register A (MRA) MRA selects the DTC operating mode. Bit Name Initial Value Description − Undefined Source Address Mode 1 and 0 − Undefined These bits specify an SAR operation after a data transfer. 0x: SAR is fixed 10: SAR is incremented after a transfer (by +1 when Sz = 0;...
  • Page 426: Dtc Mode Register B (Mrb)

    9.2.2 DTC Mode Register B (MRB) MRB selects the DTC operating mode. Bit Name Initial Value Description − CHNE Undefined DTC Chain Transfer Enable When this bit is set to 1, a chain transfer will be performed. For details, refer to 9.5.4, Chain Transfer. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the activation source flag, and clearing of DTCER...
  • Page 427: Dtc Transfer Count Register B (Crb)

    In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00.
  • Page 428: Activation Sources

    Bit Name Initial Value Description SWDTE DTC Software Activation Enable Setting this bit to 1 activates DTC. Only 1 can be written to this bit. [Clearing conditions] • When the DISEL bit is 0 and the specified number of transfers have not ended •...
  • Page 429: Location Of Register Information And Dtc Vector Table

    Source flag cleared Clear controller Clear DTCER Clear request Select On-chip supporting module IRQ interrupt Interrupt request Interrupt controller DTVECR Interrupt mask Figure 9.2 Block Diagram of DTC Activation Source Control Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM (addresses: H'FFBC00 to H'FFBFFF). Register information should be located at the address that is multiple of four within the range.
  • Page 430 Lower addresses Start address of register information Register information Chain transfer Register information for second transfer in case of chain transfer Four bytes Figure 9.3 Correspondence between DTC Vector Address and Register Information Note: * Not available in this LSI. Rev.
  • Page 431 Table 9.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Origin of Activation Activation Source Source Vector Number Vector Address DTCE* Priority Software Write to DTVECR DTVECR H'0400 + (DTVECR — High [6:0] × 2) External pin IRQ0 H'0420 DTCEA7 IRQ1 H'0422 DTCEA6...
  • Page 432: Operation

    Origin of Activation Activation Source Source Vector Number Vector Address DTCE* Priority TMR_0 CMIA0 H'0490 DTCEE3 High CMIB0 H'0492 DTCEE2 TMR_1 CMIA1 H'0498 DTCEE1 CMIB1 H'049A DTCEE0 DMAC DMTEND0A H'04A0 DTCEF7 DMTEND0B H'04A2 DTCEF6 DMTEND1A H'04A4 DTCEF5 DMTEND1B H'04A6 DTCEF4 SCI_0 RXI0 H'04B2...
  • Page 433 Figure 9.4 shows a flowchart of DTC operation, and table 9.2 summarizes the chain transfer conditions (combinations for performing the second and third transfers are omitted). Start Read DTC vector Next transfer Read register information Data transfer Write register information CHNE = 1? CHNS = 0? Transfer counter = 0...
  • Page 434: Normal Mode

    Table 9.2 Chain Transfer Conditions 1st Transfer 2nd Transfer CHNE CHNS DISEL CHNE CHNS DISEL DTC Transfer — Not 0 — — — — Ends at 1st transfer — — — — — Ends at 1st transfer — — — —...
  • Page 435: Repeat Mode

    Transfer Figure 9.5 Memory Mapping in Normal Mode 9.5.2 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. Table 9.4 lists the register function in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers has ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated.
  • Page 436: Block Transfer Mode

    Repeat area Transfer Figure 9.6 Memory Mapping in Repeat Mode 9.5.3 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 9.5 lists the register function in block transfer mode.
  • Page 437: Chain Transfer

    First block Block area Transfer Nth block Figure 9.7 Memory Mapping in Block Transfer Mode 9.5.4 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently.
  • Page 438: Interrupts

    Source Destination Register information CHNE=1 Register information DTC vector start address address Register information CHNE=0 Source Destination Figure 9.8 Operation of Chain Transfer 9.5.5 Interrupts An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1.
  • Page 439: Operation Timing

    9.5.6 Operation Timing φ DTC activation request request Data transfer Vector read Address Read Write Transfer Transfer information read information write Figure 9.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode) φ DTC activation request request Data transfer Vector read Read Write Read Write Address...
  • Page 440: Number Of Dtc Execution States

    9.5.7 Number of DTC Execution States Table 9.6 lists execution status for a single DTC data transfer, and table 9.7 shows the number of states required for each execution status. Table 9.6 DTC Execution Status Register Information Internal Vector Read Read/Write Data Read Data Write...
  • Page 441: Procedures For Using Dtc

    Procedures for Using DTC 9.6.1 Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. 2. Set the start address of the register information in the DTC vector address. 3.
  • Page 442: Chain Transfer

    3. Set the corresponding bit in DTCER to 1. 4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts.
  • Page 443: Chain Transfer When Counter = 0

    9. Each time a TGRA compare match occurs, the next output value is transferred to NDR and the set value of the next output trigger period is transferred to TGRA. The activation source TGFA flag is cleared. 10. When the specified number of transfers are completed (the TPU transfer CRA value is 0), the TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the CPU.
  • Page 444: Software Activation

    Input circuit Input buffer First data transfer register information Chain transfer (counter = 0) Second data Upper 8 bits transfer register of DAR information Figure 9.12 Chain Transfer when Counter = 0 9.7.4 Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation.
  • Page 445: Usage Notes

    5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. 6.
  • Page 446 Therefore, when the DTC is activated by an interrupt or activation source, if a read/write of the relevant register is not included in the last chained data transfer, the interrupt or activation source will be retained. Rev. 1.0, 09/01, page 402 of 904...
  • Page 447: Section 10 I/O Ports

    Section 10 I/O Ports Table 10.1 summarizes the port functions. The pins of each port also have other functions such as input/output or external interrupt input pins of on-chip supporting modules. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, and a port register (PORT) used to read the pin states.
  • Page 448 Table 10.1 Port Functions Mode 7 Input/ Modes 1 Modes 2 Port Description Mode 4 Output and 5 and 6 EXPE = 1 EXPE = 0 Type Port General I/O port P17/PO15/TIOCB2/TCLKD/ P17/PO15/TIOCB2/ P17/PO15/TIOCB2/ Schmitt- ('5$.6 also functioning TCLKD/('5$.6 TCLKD triggered as PPG outputs, input...
  • Page 449 Mode 7 Input/ Modes 1 Modes 2 Port Description Mode 4 Output and 5 and 6 EXPE = 1 EXPE = 0 Type Port General I/O port P53/$'75*/,546 Schmitt- also functioning triggered P52/SCK2/,545 as interrupt input P51/RxD2/,544 inputs, A/D when converter inputs, used as P50/TxD2/,543...
  • Page 450 Mode 7 Input/ Modes 1 Modes 2 Port Description Mode 4 Output and 5 and 6 EXPE = 1 EXPE = 0 Type Port General I/O port PA7/A23/,54: PA7/A23/,54: PA7/,54: Only PA4 also functioning to PA7 PA6/A22/,549 PA6/A22/,549 PA6/,549 as address PA5/A21/,548 PA5/A21/,548 PA5/,548...
  • Page 451 Mode 7 Input/ Modes 1 Modes 2 Port Description Mode 4 Output and 5 and 6 EXPE = 1 EXPE = 0 Type Port General I/O port PE7/D7 PE7/D7 PE7/D7 Built-in also functioning PE6/D6 PE6/D6 PE6/D6 as data I/Os input PE5/D5 PE5/D5 PE5/D5...
  • Page 452: Port 1

    10.1 Port 1 Port 1 is an 8-bit I/O port that also has other functions. The port 1 has the following registers. • Port 1 data direction register (P1DDR) • Port 1 data register (P1DR) • Port 1 register (PORT1) 10.1.1 Port 1 Data Direction Register (P1DDR) The individual bits of P1DDR specify input or output for the pins of port 1.
  • Page 453: Port 1 Register (Port1)

    10.1.3 Port 1 Register (PORT1) PORT1 shows the pin states. PORT1 cannot be modified. Bit Name Initial Value Description If a port 1 read is performed while P1DDR bits are —* set to 1, the P1DR values are read. If a port 1 read is —* performed while P1DDR bits are cleared to 0, the pin —*...
  • Page 454 Mode 7 (EXPE = 0) EDRAKE — TPU channel 2 (1) in table (2) in table below settings below P17DDR — NDER15 — — Pin function TIOCB2 output P17 input P17 output PO15 output TIOCB2 input* TCLKD input* Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000, B000, and B'01xx and IOB3 = 1. 2.
  • Page 455 • P16/PO14/TIOCA2/('5$.5 The pin function is switched as shown below according to the combination of the TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOB3 to IOB0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bit NDER14 in NDERH, bit EDRAKE in EDMDR_2 and bit P16DDR.
  • Page 456 TPU channel 2 settings MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011 IOA3 to IOA0 B'0000 B'0001 to B'0011 B'xx00 Other than B'xx00 B'0100 B'0101 to B'0111 B'1xxx CCLR1, CCLR0 — — — — Other B'10 than B'10 Output function —...
  • Page 457 • P15/PO13/TIOCB1/TCLKC The pin function is switched as shown below according to the combination of the TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOB3 to IOB0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bits TPSC2 to TPSC0 in TCR_0, TCR_2, TCR_4, and TCR_5, bit NDER13 in NDERH, and bit P15DDR.
  • Page 458 • P14/PO12/TIOCA1 The pin function is switched as shown below according to the combination of the TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOA3 to IOA0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bit NDER12 in NDERH, and bit P14DDR. TPU channel 1 (1) in table (2) in table below...
  • Page 459 • P13/PO11/TIOCD0/TCLKB The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_2, bit NDER11 in NDERH, and bit P13DDR.
  • Page 460 • P12/PO10/TIOCC0/TCLKA The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOC3 to IOC0 in TIORL_0, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_5, bit NDER10 in NDERH, and bit P12DDR.
  • Page 461 • P11/PO9/TIOCB0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0 and bits IOB3 to IOB0 in TIORH_0), bit NDER9 in NDERH, and bit P11DDR. TPU channel 0 (1) in table (2) in table below...
  • Page 462 • P10/PO8/TIOCA0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOA3 to IOA0 in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0), bit NDER8 in NDERH, and bit P10DDR. TPU channel 0 (1) in table (2) in table below...
  • Page 463: Port 2

    10.2 Port 2 Port 2 is an 8-bit I/O port that also has other functions. The port 2 has the following registers. • Port 2 data direction register (P2DDR) • Port 2 data register (P2DR) • Port 2 register (PORT2) 10.2.1 Port 2 Data Direction Register (P2DDR) The individual bits of P2DDR specify input or output for the pins of port 2.
  • Page 464: Port 2 Register (Port2)

    10.2.3 Port 2 Register (PORT2) PORT2 shows the pin states. PORT2 cannot be modified. Bit Name Initial Value Description If a port 2 read is performed while P2DDR bits are —* set to 1, the P2DR values are read. If a port 2 read is —* performed while P2DDR bits are cleared to 0, the pin —*...
  • Page 465: Pin Functions

    10.2.4 Pin Functions Port 2 pins also function as PPG outputs, TPU I/Os, and interrupt inputs. The correspondence between the register specification and the pin functions is shown below. • P27/PO7/TIOCB5/(,548) The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR_5, bits IOB3 to IOB0 in TIOR_5, and bits CCLR1 and CCLR0 in TCR_5), bit NDER7 in NDERL, bit P27DDR, and bit ITS15 in ITSR.
  • Page 466 • P26/PO6/TIOCA5/(,5447) The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR_5, bits IOA3 to IOA0 in TIOR_5, and bits CCLR1 and CCLR0 in TCR_5), bit NDER6 in NDERL, bit P26DDR, and bit ITS14 in ITSR. TPU channel 5 (1) in table (2) in table below...
  • Page 467 • P25/PO5/TIOCB4/(,5446, The pin function is switched as shown below according to the combination of the TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bit NDER5 in NDERL, bit P25DDR, and bit ITS13 in ITSR. TPU channel 4 (1) in table (2) in table below...
  • Page 468 • P24/PO4/TIOCA4/RXD4/,5445 The pin function is switched as shown below according to the combination of the TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4 and bits IOA3 to IOA0 in TIOR_4), bit NDER4 in NDERL, bit RE in SCI_4, bit P24DDR, and bit ITS12 in ITSR. TPU channel 4 (1) in table (2) in table below...
  • Page 469 • P23/PO3/TIOCD3/TXD4/(,5444, The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER3 in NDERL, bit TE in SCR of SCI_4, bit P23DDR, and bit ITS11 in ITSR.
  • Page 470 • P22/PO2/TIOCC3/(,5443, The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOC3 to IOC0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER2 in NDERL, bit P22DDR, and bit ITS10 in ITSR. TPU channel 3 (1) in table (2) in table below...
  • Page 471 • P21/PO1/TIOCB3/(,54<, The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER1 in NDERL, bit P21DDR, and bit ITS9 in ITSR. TPU channel 3 (1) in table (2) in table below...
  • Page 472 • P20/PO0/TIOCA3/(,54;, The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOA3 to IOA0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER0 in NDERL, bit P20DDR, and bit ITS8 in ITSR. TPU channel 3 (1) in table (2) in table below...
  • Page 473: Port 3

    10.3 Port 3 Port 3 is a 6-bit I/O port that also has other functions. The port 3 has the following registers. • Port 3 data direction register (P3DDR) • Port 3 data register (P3DR) • Port 3 register (PORT3) •...
  • Page 474: Port 3 Data Register (P3Dr)

    10.3.2 Port 3 Data Register (P3DR) P3DR stores output data for the port 3 pins. Bit Name Initial Value Description — — Reserved These bits are always read as 0 and cannot be — — modified. P35DR Output data for a pin is stored when the pin function is specified to a general purpose I/O.
  • Page 475: Port 3 Open Drain Control Register (P3Odr)

    10.3.4 Port 3 Open Drain Control Register (P3ODR) P3ODR controls the output status for each port 3 pin. Bit Name Initial Value Description — — Reserved These bits are always read as 0 and cannot be — — modified. P35ODR Setting a P3ODR bit to 1 makes the corresponding port 3 pin an NMOS open-drain output pin, while P34ODR...
  • Page 476: Port Function Control Register 2 (Pfcr2)

    10.3.5 Port Function Control Register 2 (PFCR2) P3ODR controls the I/O port. Bit Name Initial Value Description — — Reserved These bits are always read as 0 and cannot be modified. $6 Output Enable ASOE Selects to enable or disable the AS output pin. 0: PF6 is designated as I/O port 1: PF6 is designated as $6 output pin /:5 Output Enable...
  • Page 477: Pin Functions

    10.3.6 Pin Functions Port 3 pins also function as the pins for SCI I/Os, I C output, and a bus control signal output. The correspondence between the register specification and the pin functions is shown below. 2(, , , , /(CKE P35/SCK1/SCL0/(2( The pin function is switched as shown below according to the combination of the ICE bit in ICCRA of I...
  • Page 478 P34/SCK0/SCK4/SDA0 The pin function is switched as shown below according to the combination of bit ICE in ICCRA of I C_0, bit C/$ in SMR, bits CKE0 and CKE1 in SCR, and bit P34DDR. CKE1 — — — CKE0 — —...
  • Page 479 P31/TxD1 The pin function is switched as shown below according to the combination of bit TE in SCR of SCI_1 and bit P31DDR. P31DDR — Pin function P31 input P31 output* TxD1 output* Note: * NMOS open-drain output when P31ODR = 1. P30/TxD0/IrTxD The pin function is switched as shown below according to the combination of bit TE in SCR of SCI_0 and bit P30DDR.
  • Page 480: Port 4

    10.4 Port 4 Port 4 is an 8-bit input-only port. Port 4 has the following register. • Port 4 register (PORT4) 10.4.1 Port 4 Register (PORT4) PORT4 is an 8-bit read-only register that shows port 4 pin states. PORT4 cannot be modified. Bit Name Initial Value Description...
  • Page 481 P45/AN5 Pin function AN5 input P44/AN4 Pin function AN4 input P43/AN3 Pin function AN3 input P42/AN2 Pin function AN2 input P41/AN1 Pin function AN1 input P40/AN0 Pin function AN0 input Rev. 1.0, 09/01, page 437 of 904...
  • Page 482: Port 5

    10.5 Port 5 Port 5 is a 4-bit I/O port. The port 5 has the following registers. • Port 5 data direction register (P5DDR) • Port 5 data register (P5DR) • Port 5 register (PORT5) 10.5.1 Port 5 Data Direction Register (P5DDR) The individual bits of P5DDR specify input or output for the pins of port 5.
  • Page 483: Port 5 Register (Port5)

    10.5.3 Port 5 Register (PORT5) PORT5 shows the pin states. PORT5 cannot be modified. Bit Name Initial Value Description — Undefined Reserved Undefined values are read from these bits. —* If bits P53 to P50 are read while P5DDR bits are set to 1, the P5DR values are read.
  • Page 484 ,545 ,545 ,545 P52/SCK2/,545 The pin function is switched as shown below according to the combination of bit C/A in SMR of SCI_2, bits CKE0 and CKE1 in SCR, bit ITS2 in ITSR, and bit P52DDR. CKE1 — CKE0 — —...
  • Page 485: Port 6

    10.6 Port 6 Port 6 is a 6-bit I/O port that also has other functions. The port 6 has the following registers. • Port 6 data direction register (P6DDR) • Port 6 data register (P6DR) • Port 6 register (PORT6) 10.6.1 Port 6 Data Direction Register (P6DDR) The individual bits of P6DDR specify input or output for the pins of port 6.
  • Page 486: Port 6 Register (Port6)

    10.6.3 Port 6 Register (PORT6) PORT6 shows the pin states. PORT6 cannot be modified. Bit Name Initial Value Description — Undefined — Reserved These bits are reserved, if read they will return an — Undefined — undefined value. —* If a port 6 read is performed while P6DDR bits are set to 1, the P6DR values are read.
  • Page 487 '$&.3/,5445 ,5445 '$&.3 '$&.3 ,5445 ,5445 P64/TMO0/'$&.3 The pin function is switched as shown below according to the combination of bit SAE0 in DMABCRH, bits OS3 to OS0 in TCSR_1 of the 8-bit timer, bit P64DDR, and bit ITS12 in ITSR. SAE1 OS3 to OS0 All 0...
  • Page 488 '5(44/,54< ,54< '5(44 '5(44 ,54< ,54< P61/TMRI1/'5(44 The pin function is switched as shown below according to the combination of bit P61DDR and bit ITS9 in ITSR. P61DDR Pin function P61 input P61 output TMRI1 input '5(44 input ,54< interrupt input* Notes: 1.
  • Page 489: Port 8

    10.7 Port 8 Port 8 is a 6-bit I/O port that also has other functions. The port 8 has the following registers. • Port 8 data direction register (P8DDR) • Port 8 data register (P8DR) • Port 8 register (PORT8) 10.7.1 Port 8 Data Direction Register (P8DDR) The individual bits of P8DDR specify input or output for the pins of port 8.
  • Page 490: Port 8 Data Register (P8Dr)

    10.7.2 Port 8 Data Register (P8DR) P8DR stores output data for the port 8 pins. Bit Name Initial Value Description — — Reserved These bits are always read as 0 and cannot be — — modified. P85DR Output data for a pin is stored when the pin function is specified to a general purpose I/O.
  • Page 491: Pin Functions

    10.7.4 Pin Functions Port 8 pins also function as interrupt inputs and EXDMAC I/Os. The correspondence between the register specification and the pin functions is shown below. ,548, , , , /('$&.6 ('$&.62 2 2 2 SC K 3 ,548 ,548 ('$&.6 ('$&.6...
  • Page 492 ('$&.5 ('$&.5 ('$&.5/(,547 ,547 ,547 ,547, , , , P84/('$&.5 The pin function is switched as shown below according to the combination of bit AMS in EDMDR_2 of the EXDMAC, bit P84DDR, and bit ITS4 in ITSR. Modes 1, 2, 4, 5, 6, 7 (EXPE = 1) P84DDR —...
  • Page 493 Mode 7 (EXPE = 0) ETENDE — P83DDR — Pin function P83 input P83 output RXD3input ,546 interrupt input* ,546 input when ITS3 = 1. Note: ,545 ,545 ,545, , , , /(7(1'5 (7(1'5 (7(1'5 (7(1'5 P82/(,545 The pin function is switched as shown below according to the combination of bit ETENDE in EDMDR_2 of the EXDMAC, bit P82DDR, and bit ITS2 in ITSR.
  • Page 494 ,544 ,544 ,544, , , , /('5(46 ('5(46 ('5(46 ('5(462 2 2 2 TX D 3 P81/(,544 The pin function is switched as shown below according to the combination of bit TE in SCR of SCI_3, bit P81DDR and bit ITS1 in ITSR. P81DDR —...
  • Page 495: Port 9

    10.8 Port 9 Port 9 is an 8-bit input-only port. Port 4 has the following register. • Port 9 register (PORT4) 10.8.1 Port 9 Register (PORT9) PORT9 is an 8-bit read-only register that shows port 4 pin states. PORT9 cannot be modified. Bit Name Initial Value Description...
  • Page 496 P95/AN13/DA3 Pin function AN13 input DA3 output P94/AN12/DA2 Pin function AN12 input DA2 output P93/AN11 Pin function AN11 input P92/AN10 Pin function AN10 input P91/AN9 Pin function AN9 input P90/AN8 Pin function AN8 input Rev. 1.0, 09/01, page 452 of 904...
  • Page 497: Port A

    10.9 Port A Port A is an 8-bit I/O port that also has other functions. The port A has the following registers. • Port A data direction register (PADDR) • Port A data register (PADR) • Port A register (PORTA) •...
  • Page 498: Port A Data Direction Register (Paddr)

    10.9.1 Port A Data Direction Register (PADDR) The individual bits of PADDR specify input or output for the pins of port A. PADDR cannot be read; if it is, an undefined value will be read. Bit Name Initial Value Description •...
  • Page 499: Port A Data Register (Padr)

    10.9.2 Port A Data Register (PADR) PADR stores output data for the port A pins. Bit Name Initial Value Description PA7DR Output data for a pin is stored when the pin function is specified to a general purpose I/O. PA6DR PA5DR PA4DR PA3DR...
  • Page 500: Port A Mos Pull-Up Control Register (Papcr)

    10.9.4 Port A MOS Pull-Up Control Register (PAPCR) PAPCR controls the MOS input pull-up function. Bits 7 to 5 are valid in modes 1, 2, 5, and 6, and all the bits are valid in modes 4 and 7. Bit Name Initial Value Description PA7PCR...
  • Page 501 Bit Name Initial Value Description A23E Address 23 Enable Enables or disables output for address output 23 (A23). 0: DR output when PA7DDR = 1 1: A23 output when PA7DDR = 1 A22E Address 22 Enable Enables or disables output for address output 22 (A22). 0: DR output when PA6DDR = 1 1: A22 output when PA6DDR = 1 A21E...
  • Page 502: Pin Functions

    10.9.7 Pin Functions Port A pins also function as the pins for address outputs and interrupt inputs. The correspondence between the register specification and the pin functions is shown below. ,54: ,54:, PA6/A22/,549 ,54: ,549 ,549, PA5/A21/,548 ,549 ,548 ,548 ,548 PA7/A23/,54: The pin function is switched as shown below according to the operating mode, bit EXPE, bits...
  • Page 503: Port A Mos Input Pull-Up States

    PA3/A19, PA2/A18, PA1/A17, PA20/A16 The pin function is switched as shown below according to the operating mode, bit EXPE, bits A19E to A16E, and bit PADDR. Operating 1, 2, 5, mode EXPE — — AxxE — — PADDR — Address Address Address function...
  • Page 504: Port B

    10.10 Port B Port B is an 8-bit I/O port that also has other functions. The port B has the following registers. • Port B data direction register (PBDDR) • Port B data register (PBDR) • Port B register (PORTB) •...
  • Page 505: Port B Data Register (Pbdr)

    10.10.2 Port B Data Register (PBDR) PBDR is stores output data for the port B pins. Bit Name Initial Value Description PB7DR An output data for a pin is stored when the pin function is specified to a general purpose I/O. PB6DR PB5DR PB4DR...
  • Page 506: Port B Mos Pull-Up Control Register (Pbpcr)

    10.10.4 Port B MOS Pull-Up Control Register (PBPCR) PBPCR controls the on/off state of MOS input pull-up of port B. PBPCR is valid in modes 4 and Bit Name Initial Value Description PB7PCR When PBDDR = 0 (input port), setting the corresponding bit to 1 turns on the MOS input pull-up PB6PCR for that pin.
  • Page 507: 10.10.6 Port B Mos Input Pull-Up States

    10.10.6 Port B MOS Input Pull-Up States Port B has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 4 and 7. MOS input pull-up can be specified as on or off on a bit-by-bit basis.
  • Page 508: Port C

    10.11 Port C Port C is an 8-bit I/O port that also has other functions. The port C has the following registers. • Port C data direction register (PCDDR) • Port C data register (PCDR) • Port C register (PORTC) •...
  • Page 509: Port C Data Register (Pcdr)

    10.11.2 Port C Data Register (PCDR) PCDR stores output data for the port C pins. Bit Name Initial Value Description PC7DR Output data for a pin is stored when the pin function is specified to a general purpose I/O. PC6DR PC5DR PC4DR PC3DR...
  • Page 510: Port C Mos Pull-Up Control Register (Pcpcr)

    10.11.4 Port C MOS Pull-Up Control Register (PCPCR) PCPCR controls the on/off state of MOS input pull-up of port C. PCPCR is valid in modes 4 and Bit Name Initial Value Description PC7PCR When PCDDR = 0 (input port), setting the corresponding bit to 1 turns on the MOS input pull-up PC6PCR for that pin.
  • Page 511: 10.11.6 Port C Mos Input Pull-Up States

    10.11.6 Port C MOS Input Pull-Up States Port C has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 4 and 7. MOS input pull-up can be specified as on or off on a bit-by-bit basis.
  • Page 512: Port D

    10.12 Port D Port D is an 8-bit I/O port that also has other functions. The port D has the following registers. • Port D data direction register (PDDDR) • Port D data register (PDDR) • Port D register (PORTD) •...
  • Page 513: Port D Register (Portd)

    10.12.3 Port D Register (PORTD) PORTD shows port D pin states. PORTD cannot be modified. Bit Name Initial Value Description If a port D read is performed while PDDDR bits are —* set to 1, the PDDR values are read. If a port D read —* is performed while PDDDR bits are cleared to 0, the —*...
  • Page 514: 10.12.6 Port D Mos Input Pull-Up States

    PD7/D15, PD6/D14, PD5/D13, PD4/D12, PD3/D11, PD2/D10, PD1/D9, PD0/D8 The pin function is switched as shown below according to the operating mode, bit EXPE, and bit PDDDR. Operating 1, 2, 4, 5, 6 mode EXPE — PDDDR — — Pin function Data I/O PD input PD output...
  • Page 515: Port E

    10.13 Port E Port E is an 8-bit I/O port that also has other functions. The port E has the following registers. • Port E data direction register (PEDDR) • Port E data register (PEDR) • Port E register (PORTE) •...
  • Page 516: Port E Data Register (Pedr)

    10.13.2 Port E Data Register (PEDR) PEDR stores output data for the port E pins. Bit Name Initial Value Description PE7DR Output data for a pin is stored when the pin function is specified to a general purpose I/O. PE6DR PE5DR PE4DR PE3DR...
  • Page 517: Port E Pull-Up Control Register (Pepcr)

    10.13.4 Port E Pull-up Control Register (PEPCR) PEPCR controls on/off states of the input pull-up MOS of port E. PEPCR is valid in 8-bit bus mode. Bit Name Initial Value Description PE7PCR When PEDDR = 0 (input port), the input pull-up MOS of the input pin is on when the corresponding bit is PE6PCR set to 1.
  • Page 518: 10.13.6 Port E Mos Input Pull-Up States

    10.13.6 Port E MOS Input Pull-Up States Port E has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in 8-bit bus mode. MOS input pull-up can be specified as on or off on a bit-by-bit basis.
  • Page 519: Port F

    10.14 Port F Port F is an 8-bit I/O port that also has other functions. The port F has the following registers. For details on the port function control register 2, refer to section 10.3.5, Port Function Control Register 2 (PFCR2). •...
  • Page 520 Bit Name Initial Value Description • PF7DDR 1/0* Modes 1, 2, 4, 5, and 6 Pin PF7 functions as the ø output pin when the PF6DDR corresponding PFDDR bit is set to 1, and as an input PF5DDR port when the bit is cleared to 0. PF4DDR Pin PF6 functions as the $6 output pin when ASOE is set to 1.
  • Page 521: Port F Data Register (Pfdr)

    10.14.2 Port F Data Register (PFDR) PFDR stores output data for the port F pins. Bit Name Initial Value Description PF7DR Output data for a pin is stored when the pin function is specified to a general purpose I/O. PF6DR PF5DR PF4DR PF3DR...
  • Page 522: 10.14.4 Pin Functions

    10.14.4 Pin Functions Port F pins also function as the pins for external interrupt inputs, bus control signal I/Os, and system clock outputs (ø). The correspondence between the register specification and the pin functions is shown below. PF7/ø The pin function is switched as shown below according to bit PF7DDR. Operating 1, 2, 4 to 7 mode...
  • Page 523 PF4/+:5 The pin function is switched as shown below according to the operating mode, bit EXPE, and bit PF4DDR. Operating 1, 2, 4, 5, 6 mode EXPE — PF4DDR — — +:5 output +:5 output Pin function PF4 input PF4 output PF3//:5 The pin function is switched as shown below according to the operating mode, bit EXPE, bit LWROE, and bit PF3DDR.
  • Page 524 /&$6 /&$6 /&$6/'40/ '40/ '40/ '40/* ,5448 ,5448 ,5448 PF2//&$6 /,5448 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR, bits ABW5 to ABW2 in ABWCR, and bit PF2DDR.
  • Page 525 8&$6 8&$6 8&$6/,5447 ,5447 ,5447/'408 ,5447 '408 '408 '408* PF1/8&$6 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR, and bit PF1DDR. Operating 1, 2, 4, 5, 6 mode EXPE —...
  • Page 526: Port G

    10.15 Port G Port G is a 7-bi