26.14.4 Dfg Noise Removal Circuit - Hitachi H8S/2199 Hardware Manual

26.14.4 DFG Noise Removal Circuit

Block Diagram: Figure 26.70 shows the block diagram of the DFG noise removal circuit.
DFG
Register Description: Table 26.24 shows the register configuration of the DFG mask circuit.
Table 26.24 Register Configuration
Name
FG control register
FG Control Register (FGCR)
Bit :
Initial value :
R/W :
FGCR selects the edge of the DFG noise removal signal (NCDFG) to be sent to the drum speed
error detector. If a read is attempted, an undetermined value is read out.
It is initialized to H'FE by a reset, or in stand-by or module stop mode.
The edge selection circuit is located in the drum speed error detector, and outputs the register
output to the drum speed error detector.
Bits 7 to 1    Reserved: Cannot be modified and are always read as 1.
Delay circuit
delay = 2φ
Figure 26.70 DFG Noise Removal Circuit
Abbrev.
FGCR
7 6 5
— — —
1 1 1
— — —
Rising edge
detection
Falling edge
detection
R/W Size
W Byte
4 3
— —
1 1
— —
S Q
R
Initial Value
H'FE
2 1
— —
1 1
— —
Rev. 1.0, 02/00, page 731 of 1141
NCDFG
Address
H'D09E
0
DRF
0
W