Hitachi H8S/2199 Hardware Manual page 130

Single-chip microcomputer
Table of Contents

Advertisement

Figure 6.4 shows a block diagram of the priority decision circuit.
Interrupt source
Figure 6.4 Block Diagram of Interrupt Priority Determination Operation
• Interrupt Acceptance Control and 3-Level Control: In interrupt control modes 0 and 1,
interrupt acceptance control and 3-level mask control is performed by means of the I and UI
bits in CCR, and ICR (control level).
Table 6.6 shows the interrupts selected in each interrupt control mode.
Table 6.6
Interrupts Selected in Each Interrupt Control Mode
Interrupt
Interrupt Mask Bit
Control
Mode
I
0
0
1
1
0
1
Notes: * Don't care
1. In this LSI, the NMI interrupt is generated by the watchdog timer.
• Default Priority Determination: If the same value is set for ICR, acceptance of multiple
interrupts is enabled, and so only the interrupt source with the highest priority according to the
preset default priorities is selected and has a vector number generated.
Interrupt sources with a lower priority than the accepted interrupt source are held pending.
Table 6.7 shows operations and control signal functions in each interrupt control mode.
Rev. 1.0, 02/00, page 112 of 1141
I C R
I
Interrupt acceptance
control and 3-level
mask control
Interrupt control modes 0 and 1
UI
*
*
*
0
1
UI
Default priority
determination
Selected Interrupts
All interrupts (control level 1 has priority)
1
NMI*
and address trap interrupts
All interrupts (control level 1 has priority)
1
NMI*
, address trap and control level 1 interrupts
1
NMI*
and address trap interrupts
Vector number

Advertisement

Table of Contents
loading

Table of Contents