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Bits 1 and 0 REF30P Division Ratio Selection Bit (DVREF1, DVREF0): Selects the division
value of REF30P. If it is read-accessed, the counter value is read out. (The selected division
value is set by the UDF of the counter.)
Bit 1
Bit 0
DVREF1
DVREF0
0
0
1
1
0
1
X-Value Data Register (XDR)
15
Bit :
—
Initial value :
1
—
R/W :
The X-value data register (XDR) is an 16-bit write-only register. No read is valid. If a read is
attempted, an undetermined value is read out. Only a word access is valid. If a byte access is
attempted, correct operation is not guaranteed.
Set an X-value correction data to XDR, except a value which is beyond the cycle of the CTL
pulse. If AT/08 = 0, TRK/; = 0 is set, CAPREF30 can be generated only by setting the XDR.
Set an X-value and TRK correction value in PB mode, and X- value in REC mode.
It is initialized to H'F000 by a reset, or in stand-by or module stop mode.
TRK-Value Data Register (TRDR)
Bit :
15
—
Initial value :
1
—
R/W :
The TRK-value data register (TRDR) is an 16-bit write-only register. No read is valid. If a read is
attempted, an undetermined value is read out. Only a word access is valid. If a byte access is
attempted, correct operation is not guaranteed.
Set an TRK-value correction data to TRDR, except a value which is beyond the cycle of the CTL
pulse. It is initialized to H'F000 by a reset, or in stand-by or module stop mode.
Rev. 1.0, 02/00, page 660 of 1141
Description
Division in 1
Division in 2
Division in 3
Division in 4
14
13
12
11
—
—
—
XD11 XD10
1
1
1
0
—
—
—
W
14
13
12
11
—
—
—
TRD11 TRD10
1
1
1
0
—
—
—
W
10
9
8
7
XD9 XD8
XD7 XD6
0
0
0
0
W
W
W
W
10
9
8
7
TRD9 TRD8
TRD7 TRD6
0
0
0
0
W
W
W
W
6
5
4
3
XD5 XD4
XD3 XD2
0
0
0
0
W
W
W
W
6
5
4
3
TRD5 TRD4
TRD3 TRD2
0
0
0
0
W
W
W
W
(Initial value)
2
1
0
XD1 XD0
0
0
0
W
W
W
2
1
0
TRD1 TRD0
0
0
0
W
W
W
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