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22.2.7
Serial Status Register 1 (SSR1)
Bit :
TDRE
Initial value :
R/W :
R/(W)*
Note: * Only 0 can be written to clear the flag.
SSR1 is an 8-bit register containing status flags that indicate the operating status of the SCI, and
multiprocessor bits.
SSR1 can be read or written to by the CPU at all times. However, 1 cannot be written to flags
TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be
read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified.
SSR1 is initialized to H'84 by a reset, and in standby mode, watch mode, subactive mode, subsleep
mode, and module stop mode.
Bit 7 Transmit Data Register Empty (TDRE): Indicates that data has been transferred from
TDR1 to TSR1 and the next serial data can be written to TDR1.
Bit 7
TDRE
Description
0
[Clearing conditions]
When 0 is written in TDRE after reading TDRE = 1
1
[Setting conditions]
1. When the TE bit in SCR is 0
2. When data is transferred from TDR1 to TSR1 and data can be written to TDR1
Bit 6 Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR1.
Bit 6
RDRF
Description
0
[Clearing conditions]
When 0 is written in RDRF after reading RDRF = 1
1
[Setting conditions]
When serial reception ends normally and receive data is transferred from RSR to
RDR
Note: RDR1 and the RDRF flag are not affected and retain their previous values when an error is
detected during reception or when the RE bit in SCR1 is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun
error will occur and the receive data will be lost.
Rev. 1.0, 02/00, page 410 of 1141
7
6
RDRF
ORER
1
0
R/(W)*
R/(W)*
5
4
FER
PER
0
0
R/(W)*
R/(W)*
3
2
TEND
MPB
0
1
R
1
0
MPBT
0
0
R
R/W
(Initial value)
(Initial value)
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