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H'FFBB: Timer Counter A TCA: TimerA
Bit :
Initial value :
R/W :
H'FFBC: Watchdog Timer Control/Status Register WTCSR: WDT
7
Bit :
OVF
0
Initial value :
R/W :
R/(W)*
Overflow flag
Note: * Only 0 can be written to clear the flag.
7
6
TCA7
TCA6
TCA5
0
0
R
R
6
5
WT/IT
TME
0
0
R/W
R/W
Timer enable bit
0
1
Timer mode select bit
0
Interval timer mode: Sends the CPU an interval timer interrupt
request (WOVI) when WTCNT overflows
1
Watchdog timer mode: Sends the CPU a reset or NMI interrupt
request when WTCNT overflows
0
[Clearing conditions]
(1) Write 0 in the TME bit
(2) Read WTCSR when OVF = 1, then write 0 in OVF
1
[Setting conditions]
When WTCNT overflows (changes from H'FF to H'00)
(When internal reset request generation is selected in watchdog timer mode,
OVF is cleared automatically by the internal reset.)
5
4
3
TCA4
TCA3
0
0
0
R
R
R
4
3
—
RST/NMI
0
0
—
R/W
Reset or NMI
0
1
WTCNT is initialized to H'00 and halted (Initial value)
WTCNT counts
2
1
TCA2
TCA1
0
0
R
R
2
1
CKS2
CKS1
CKS0
0
0
R/W
R/W
R/W
NMI interrupt request is generated
Internal reset request is generated
(Initial value)
(Initial value)
Rev. 1.0, 02/00, page 1093 of 1141
0
TCA0
0
R
0
0
(Initial value)
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