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H'D038: Drum Speed Error Detection Control Register
Bit :
7
DFCS1
0
Initial value :
R/W
R/W :
Clock source select bit
DFCS1 DFCS0
0
0
1
1
0
1
1. Only 0 can be written.
Notes:
2. When read, counter value is read.
Rev. 1.0, 02/00, page 994 of 1141
6
5
4
DFCS0
DFOVF
DFRFON DF-R/UNR
0
0
0
*1
R/W
R/(W)
R/W
Error data limit function select bit
0
Limit function OFF (Initial value)
1
Limit function ON
Counter overflow flag
0
Normal status (Initial value)
1
Counter overflows.
Description
φs (Initial value)
φs/2
φs/4
φs/8
DFVCR: Drum Speed Error Detector
3
2
DPCNT
0
0
R
R/W
Drum lock counter setting bit
DFRCS1 DFRCS0
0
1
Drum phase system filter computation auto start bit
0
Filter computation by drum lock detection is not excuted. (Initial value)
1
Filter computation of phase system is executed at the time of
drum lock detection.
Drum lock flag
0
Drum speed system is not locked. (Initial value)
1
Drum speed system is locked.
1
0
DFRCS1
DFRCS0
0
0
*2
*2
(R)/W
(R)/W
Description
0
Underflow by 1 lock detection (Initial value)
1
Underflow by 2 lock detections
0
Underflow by 3 lock detections
1
Underflow by 4 lock detections
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