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2
23.2.6
I
C Bus Status Register (ICSR)
Bit :
ESTP
Initial value :
R/W :
R/(W)*
Note: * Only 0 can be written to clear the flag.
ICSR is an 8-bit readable/writable register that performs flag confirmation and acknowledge
confirmation and control.
ICSR is initialized to H'00 by a reset.
Bit 7 Error Stop Condition Detection Flag (ESTP): Indicates that a stop condition has been
detected during frame transfer in I
Bit 7
ESTP
Description
0
No error stop condition
[Clearing condition]
1. When 0 is written in ESTP after reading ESTP = 1
2. When the IRIC flag is cleared to 0
• In I
2
1
C bus format slave mode: Error stop condition detected
[Setting condition]
When a stop condition is detected during frame transfer
• In other modes: No meaning
Rev. 1.0, 02/00, page 480 of 1141
7
6
STOP
IRTR
0
0
R/(W)*
R/(W)*
2
C bus format slave mode.
5
4
AASX
AL
0
0
R/(W)*
R/(W)*
3
2
AAS
ADZ
0
0
R/(W)*
R/(W)*
1
0
ACKB
0
0
R/W
(Initial value)
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