Hitachi H8S/2199 Hardware Manual page 631

Single-chip microcomputer

Table of Contents

Bit 2    Drum Phase System Filter Computation Automatic Start Bit (DPCNT): Enables the

filter computation of the phase system if an underflow occurred in the drum lock counter.

Bits 1 and 0    Drum Lock Counter Setting Bits (DFRCS1, DFRCS0): Sets the number of times

to detect drum locks (which means the number of times DFG is detected in the range set by the

lock range data register). The drum lock flag is set when the specified number of drum locks is

detected. If the NCDFG signal is detected outside the lock range after data is written in DFRCS1

and DFRCS0, the data will be stored in the lock counter.

Note: If DFRCS1 or DFRCS0 is read-accessed, the counter value is read out. If bit 3 (drum lock

flag) is 1 and the drum lock counter's value is 3, it indicates that the drum speed system is

locked. The drum lock counter stops until lock is released after underflow.

Disables the filter computation by detection of the drum lock.

Enables the filter computation of the phase system when drum lock is

Underflow occurs after lock was detected once.

Underflow occurs after lock was detected twice.

Underflow occurs after lock was detected three times.

Underflow occurs after lock was detected four times.

Rev. 1.0, 02/00, page 625 of 1141

(Initial value)