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H'D068 to H'D069: FIFO Output Pattern Register 2 FPDRB: HSW Timing Generator
Bit
:
Initial value
:
R/W
:
Reserved
Cannot be read or modified
:
Bit
PPGB7
:
Initial value
:
R/W
Rev. 1.0, 02/00, page 1006 of 1141
15
14
13
—
ADTRGB
STRIGB
1
*
*
—
W
W
S-TRIGB bit
Indicates a signal that generates an interrupt.
When the STRIGA is selected by the ISEL,
modifying this bit from 0 to 1 generates an interrupt.
A/D Trigger B bit
Indicates a hardware trigger signal for the A/D converter.
7
6
5
PPGB6
PPGB5
*
*
*
W
W
W
12
11
NarrowFFB
VFFB
*
*
W
W
AudioFFB bit
Controls the audio head.
VideoFFB bit
Controls the video head.
NarrowFFB bit
Controls the narrow video head.
4
3
PPGB4
PPGB3
*
*
W
W
PPG output signal B bits
Used for outputting a timing
control signal from port 7 (PPG).
10
9
8
AFFB
VpulseB
MlevelB
*
*
*
W
W
W
MlevelB bit
Used for generating an additional
V signal. For details, refer to section
26.12, Additional V Signal Generator.
VpulseB bit
Used for generating an additional
V signal. For details, refer to section
26.12, Additional V Signal Generator.
2
1
0
PPGB2
PPGB1
PPGB0
*
*
*
W
W
W
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