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CTL Detector: If the CTL detector fails to detect a CTL pulse, it sets the CTL control register
(CTCR) bit 1 to 1 indicating that the pulse has not been detected. If a CTL pulse is detected after
that, the bit is automatically cleared to 0. Duration used for determining detection or non-
detection of the pulse depends on magnitude of phase shift of the last detected pulse from the
reference phase (phase difference between REF30 and CTL signal). Typically, detection or non-
detection is determined within 3 to 4 cycles of the reference period.
If settings of the CTL gain control register are maintained in a table format, you can refer to it
when the CTL detector failed to detect CTL pulses. From the table, you can control amplifier gain
of the CTL according to state of UNCTL bit, thereby selecting an optimum CTL amplifier gain
depending on state of the pulse recorded.
Figure 26.53 illustrates concept of gain control for detecting the CTL input pulse.
*
V+TH (fixed)
V-TH (fixed)
*
Note: * CTL input sensitivity is variable depending on CTL
gain control register (CTLGR) setting.
Figure 26.53 CTL Input Pulse Gain Control
Rev. 1.0, 02/00, page 705 of 1141
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