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External Clock: The external clock signal should have the same frequency as the system clock
(φ).
Table 9.3 and figure 9.6 show the input conditions for the external clock.
Table 9.3
External Clock Input Conditions
Item
External clock input low
pulse width
External clock input high
pulse width
External clock rise time
External clock fall time
OSC1
Table 9.4 shows the external clock output settling delay time, and figure 9.7 shows the external
clock output settling delay timing. The oscillator and duty adjustment circuit have a function for
adjusting the waveform of the external clock input at the OSC1 pin. When the prescribed clock
signal is input at the OSC1 pin, internal clock signal output is fixed after the elapse of the external
clock output settling delay time (t
period, the reset signal should be driven low to maintain the reset state.
V
= 4.0 to 5.5 V
CC
Symbol
Min
t
40
EXL
t
40
EXH
t
EXr
t
EXf
t
EXH
t
EXr
Figure 9.6 External Clock Input Timing
). As the clock signal output is not fixed during the t
DEXT
Max
Unit
ns
ns
10
ns
10
ns
t
EXL
t
EXf
Rev. 1.0, 02/00, page 179 of 1141
Test Conditions
Figure 9.6
DEXT
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