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FIFO Output Pattern Register 1 (FPDRA)
Bit :
Initial value :
R/W :
Bit :
PPGA7
Initial value :
R/W :
Note : * Don't care
FPDRA is a buffer register for the FIFO1 output pattern register. The output pattern data written
in FPDRA is written at the same time to the position of the FIFO1 pointed by the buffer pointer.
Be sure to write the output pattern data in FPDRA before writing it in FTPRA.
FPDRA is an 16-bit write-only register. Only a word access is valid. If a byte access is
attempted, correct operation is not guaranteed. No read is valid. If a read is attempted, an
undetermined value is read out. It is not initialized by a reset, or in stand-by or module stop mode;
accordingly be sure to write data before use.
Bit 15 Reserved: Cannot be read or modified.
Bit 14 A/D Trigger A Bit (ADTRGA): Indicates a hardware trigger signal for the A/D
converter.
Bit 13 S-TRIGA Bit (STRIGA): Indicates a signal that generates an interrupt. When the
STRIGA is selected by the ISEL, modifying this bit from 0 to 1 generates an interrupt.
Bit 12 NarrowFFA Bit (NarrowFFA): Controls the narrow video head.
Bit 11 VideoFFA Bit (VFFA): Controls the video head.
Bit 10 AudioFFA Bit (AFFA): Controls the audio head.
Bit 9 VpulseA Bit (VpulseA): Used for generating an additional V signal. For details, refer to
section 26.12, Additional V Signal Generator.
Bit 8 MlevelA Bit (MlevelA): Used for generating an additional V signal. For details, refer to
section 26.12, Additional V Signal Generator.
Bits 7 to 0 PPG Output Signal A Bits (PPGA7 to PPGA0): Used for outputting a timing
control signal from port 7 (PPG).
Rev. 1.0, 02/00, page 600 of 1141
15
14
ADTRGA
STRIGA
—
1
*
—
W
7
6
PPGA6
PPGA5
*
*
W
W
13
12
NarrowFFA
VFFA
*
*
W
W
5
4
PPGA4
PPGA3
*
*
W
W
11
10
AFFA
VpulseA
*
*
W
W
3
2
PPGA2
PPGA1
*
*
W
W
9
8
MlevelA
*
*
W
W
1
0
PPGA0
*
*
W
W
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