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17.1.3
Register Configuration
The WDT has two registers, as described in table 17.1. These registers control clock selection,
WDT mode switching, the reset signal, etc.
Table 17.1 WDT Registers
Name
Watchdog timer
control/status register
Watchdog timer counter
System control register
Notes: 1. Lower 16 bits of the address.
2. For details of write operations, see section 17.2.4, Notes on Register Access.
3. Only 0 can be written in bit 7, to clear the flag.
Abbrev.
R/W
WTCSR
R/ (W)
WTCNT
R/W
SYSCR
R/W
Initial Value
*3
H'00
H'00
H'09
Rev. 1.0, 02/00, page 349 of 1141
*1
Address
*2
Write
Read
H'FFBC
H'FFBC
H'FFBC
H'FFBD
H'FFE8
H'FFE8
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