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Operation:
• Frequency divider
The CFG pulses output from the capstan motor are sent to internal circuitry as the CFG signal
via the zero-cross type comparator. The CFG signal, shaped into a rectangular waveform by a
reshaping circuit, is divided by the CFG frequency dividers, and used in servo control. The
rising edge or both edges of the CFG signal can be selected for the frequency divider.
The CFG frequency divider consists of a 7-bit frequency divider with a mask timer for capstan
speed control (DVCFG signal generator) and a 7-bit frequency divider for capstan phase
control (DVCFG2 signal generator).
The DVCFG signal generator consists of a 7-bit reload register (CFG frequency division
register1: CDIVR1), a 7-bit down-counter, and a 6-bit mask timer (with settable mask
interval). Frequency division is performed by setting the frequency-division value in 7-bit
CDIVR1. When the frequency-division value is written in CDIVR1, it is also written in the
down-counter. After frequency-division of a CFG signal for which the edge has been selected,
the signal is sent via the mask timer to the capstan speed error detector as the DVCFG signal.
The DVCFG2 signal generator consists of a 7-bit reload register (CFG frequency division
register 2: CDIVR2) and a 7-bit down-counter. The 7-bit frequency divider does not have a
mask timer. Frequency division is performed by setting the frequency-division value in
CDIVR2. When the frequency-division value is written in CDVIR2, it is also written in the
down-counter. After frequency division of a CFG signal for which the edge has been selected,
the signal is sent to the capstan speed error detector and timer L as the DVCFG2 signal.
Frequency division starts when the frequency-division value is written.
When DVTRG bit in CDVC register is set to 0, reloading is executed with the switch over
timing from PB (ASM) mode to REC mode. To switch from REF30 to CREF, change the
settings of bit 4 (CR/RF bit) in the capstan phase error detection control register (CPGCR). If
synchronization is necessary for phase control, this can be provided by writing the frequency-
division value in CDIVR2.
The down-counters are decremented on rising edges of the CFG signal when the CRF bit is 0
in the DVCFG control register (CDVC), and on both edges when the CRF bit is 1.
Figure 26.66 shows examples of CFG frequency division waveforms.
Rev. 1.0, 02/00, page 727 of 1141
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