Hitachi H8S/2199 Hardware Manual page 639

Drum Phase Error Data Registers (DPER1, DPER2)
DPER1
Bit :
—
Initial value :
—
R/W :
DPER2
Bit : 15
DPER15
Initial value :
R*/W
R/W :
Bit :
DPER7
Initial value :
R*/W
R/W :
Note: * Note that only detected error data can be read.
DPER1 and DPER2 constitute a 20-bit drum phase error data register. The 20 bits are weighted as
follows: bit 3 of DPER1 is the MSB, and bit 0 of DPER2 is the LSB. When the rotational phase is
correct, the data H'00000 is latched. Negative data will be latched if the drum leads the correct
phase, and positive data if it lags. Values in DPER1 and DPER 2 are transferred to the digital
filter circuit.
DPER1 and DPER are 20-bit read/write registers. When writing data to DPER 1 and DPER2,
write to DPER1 first, and then write to DPER2. Only a word access is valid. If a byte access is
attempted, correct operation is not guaranteed. DPER1 and DPER2 are initialized to H'F0 and
H'0000 by a reset, and in standby mode.
See the note on the drum phase preset data registers (DPPR1 and DPPR2).
7 6
— —
1 1
— —
14 13
DPER14 DPER13
0 0
R*/W R*/W
7 6
DPER6 DPER5
0 0
R*/W R*/W
5 4
— DPER19
1 1
—
R*/W
12 11
DPER12 DPER11
0 0
R*/W
R*/W
5 4
DPER4
DPER3
0 0
R*/W
R*/W
3 2
DPER18 DPER17
0 0
R*/W R*/W
10
DPER10 DPER9
0 0
R*/W R*/W
3 2
DPER2 DPER1
0 0
R*/W R*/W
Rev. 1.0, 02/00, page 633 of 1141
1 0
DPER16
0 0
R*/W
9 8
DPER8
0 0
R*/W
1 0
DPER0
0 0
R*/W