Hitachi H8S/2199 Hardware Manual page 1088

Single-chip microcomputer
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H'D244: Vertical Sync Signal Threshold Register VVTHR: Sync Separator
:
Bit
VVTH7
Initial value
:
R/W
:
W
Note: Refer to section 27.2.5, Vertical Sync Signal Threshold Register (VVTHR)
H'D245: Field Detection Window Register FWIDR: Sync Separator
:
Bit
Initial value
:
R/W
:
Note: Refer to section 27.2.6, Field Detection Window Register (FWIDR)
H'D246: H Complement and Mask Timing Register HCMMR: Sync Separator
15
14
:
Bit
HC8
HC7
Initial value
:
0
R/W
:
W
W
Note: Refer to section 27.2.7, H Complement and Mask Timing Register (HCMMR)
Rev. 1.0, 02/00, page 1086 of 1141
7
6
VVTH6
VVTH5
0
0
W
7
6
1
1
13
12
11
HC6
HC5
HC4
0
0
0
0
W
W
W
Complementary pulse
generation timing
5
4
VVTH4
VVTH3
0
0
W
W
Vertical sync signal threshold
5
4
FWID3
1
1
10
9
8
7
HC3
HC2
HC1
HC0 HM6
0
0
0
0
W
W
W
W
3
2
VVTH1
VVTH2
0
0
W
W
3
2
FWID2
FWID1
0
0
W
W
Field detection window timing
6
5
4
3
HM5
HM4
HM3
0
0
0
0
W
W
W
W
HHK clearing timing
1
0
VVTH0
0
0
W
W
1
0
FWID0
0
0
W
W
2
1
0
HM2
HM1
HM0
0
0
0
W
W
W

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