Hitachi H8S/2199 Hardware Manual page 787

Bits 7 and 6    Start Bit Detection Window Signal Falling Timing Setting
(SRWDE1 and SRWDE0): Specifies the falling timing (end timing) of the start bit detection
window signal.
Bit 1 Bit 0
SRWDE1 SRWDE0
0 0
1
1 0
1
Bits 5 and 4    Start Bit Detection Window Signal Rising Timing Setting
(SRWDS1 and SRWDS0): Specifies the rising timing (start timing) of the start bit detection
window signal.
Bit 1 Bit 0
SRWDS1 SRWDS0
0 0
1
1 0
1
Bits 3 and 2    Clock Run-in Detection Window Signal Falling Timing Setting
(CRWDE1 and CRWDE0): Specifies the falling timing (end timing) of the clock run-in
detection window signal.
Bit 1 Bit 0
CRWDE1 CRWDE0
0 0
1
1 0
1
Rev. 1.0, 02/00, page 782 of 1141
Description
The detection ends about 29.5 µs after the slicer start point
The detection ends about 29.0 µs after the slicer start point
The detection ends about 30.0 µs after the slicer start point
This setting must not be used
Description
The detection starts about 23.5 µs after the slicer start point
The detection starts about 23.0 µs after the slicer start point
The detection starts about 24.0 µs after the slicer start point
This setting must not be used
Description
The detection ends about 23.5 µs after the slicer start point
The detection ends about 23.0 µs after the slicer start point
The detection ends about 24.0 µs after the slicer start point
This setting must not be used
(Initial value)
(Initial value)
(Initial value)