Table of Contents
Advertisement
H'D052 to H'D053: CFG Speed Error Data Register
15
Bit
:
CFER15 CFER14 CFER13 CFER12 CFER11 CFER10 CFER9 CFER8 CFER7 CFER6 CFER5 CFER4 CFER3 CFER2 CFER1 CFER0
:
Initial value
0
R/W
*R/W
*R/W
:
Note: * Only the detected error data can be read.
H'D054 to H'D055: CFG Lock Upper Data Register
15
14
Bit
:
CFRUDR15 CFRUDR14 CFRUDR13 CFRUDR12 CFRUDR11 CFRUDR10 CFRUDR9 CFRUDR8 CFRUDR7 CFRUDR6 CFRUDR5 CFRUDR4 CFRUDR3 CFRUDR2 CFRUDR1 CFRUDR0
Initial value
:
0
W
R/W
:
H'D056 to H'D057: CFG Lock Lower Data Register
15
14
:
Bit
CFRLDR15 CFRLDR14 CFRLDR13 CFRLDR12 CFRLDR11 CFRLDR10 CFRLDR9 CFRLDR8 CFRLDR7 CFRLDR6 CFRLDR5 CFRLDR4 CFRLDR3 CFRLDR2 CFRLDR1 CFRLDR0
:
Initial value
1
W
W
R/W
:
14
13
12
11
0
0
0
0
*R/W
*R/W
*R/W
13
12
11
1
1
1
1
W
W
W
W
13
12
11
0
0
0
0
W
W
W
CFER: Capstan Speed Error Detector
10
9
8
7
0
0
0
0
*R/W
*R/W
*R/W
*R/W
CFRUDR: Capstan Speed Error Detector
10
9
8
7
1
1
1
1
W
W
W
W
CFRLDR: Capstan Speed Error Detector
10
9
8
7
0
0
0
0
W
W
W
W
6
5
4
3
0
0
0
0
*R/W
*R/W *R/W
*R/W *R/W
6
5
4
3
1
1
1
1
W
W
W
W
6
5
4
3
0
0
0
0
W
W
W
W
Rev. 1.0, 02/00, page 997 of 1141
2
1
0
0
0
0
*R/W *R/W
2
1
0
1
1
1
W
W
W
2
1
0
0
0
0
W
W
W
Advertisement
Table of Contents
