Operation - Hitachi H8S/2199 Hardware Manual

Single-chip microcomputer

Table of Contents

Bit 3    Latch Signal Selection Bit (SELCFG2): Selects the counter preset signal and the error

data latch signal data in PB (ASM) mode.

Presets CAPREF30 signal; latches DVCTL signal

Presets REF30P (CREF) signal; latches DVCFG2 signal

Bits 2 to 0    Reserved: Cannot be modified and are always read as 1.

Operation

The capstan phase error detector detects the phase error based on the reference value set in the

capstan specified phase preset data registers 1 and 2 (CPPR1 and CPPR2). The reference values

set in CPPR1 and CPPR2 are preset in the counter by REF30P (CREF) signal or CAPREF signal,

and counted up by the clock selected. The latching of the error data is performed by DVCTL or

The error data detected in the error data automatic transmission mode (CFEPS bit of DFUCR = 0)

is sent to the digital filter circuit automatically. In soft transmission mode (CFEPS bit of DFUCR

= 1), the data written in CPER1 and CPPR2 is sent to the digital filter circuit. The error data is

signed binary. It takes a positive number (+) if the phase is behind the specified phase, a negative

number (-) if in advance of the specified phase, or 0 if it had no phase error (revolving at the

specified phase). Figures 26.35 and 26.36 show examples of operation to detect a capstan phase

Capstan Phase Error Detection Counter: The capstan phase error detection counter stops

counting when an overflow or latch occurs. At the same time, it generates an interrupt request

(IRRCAP3), and sets the overflow flag (CPOVF) if overflow occurred. To clear CPOVF, write 0

after reading 1. If setting the flag and writing 0 take place simultaneously, the latter is invalid.

Interrupt Request: IRRCAP3 is generated by the DVCTL or DVCFG2 signal latch and the

overflow of the error detection counter.

Rev. 1.0, 02/00, page 654 of 1141

(Initial value)