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Table 9.4
External Clock Output Settling Delay Time
Conditions: V
= 4.0 V to 5.5 V, AV
CC
Item
External clock output settling
delay time
Note: * t
includes 20 t
DEXT
4.0 V
V
CC
OSC1
φ
(Internal)
RES
Note: * t
includes 20 t
DEXT
Figure 9.7 External Clock Output Settling Delay Timing
Rev. 1.0, 02/00, page 180 of 1141
= 4.0 V to 5.5 V, V
CC
Symbol
t
*
DEXT
of 5(6 pulse width (t
CYC
of RES pulse width (t
cyc
= AV
SS
Min
Max
500
).
RESW
t
*
DEXT
).
RESW
= 0 V
SS
Unit
Notes
µs
Figure 9.7
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