Hitachi H8S/2199 Hardware Manual page 554

Single-chip microcomputer
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2. SLEEP Instruction 2
When the trap address is the SLEEP instruction and the instruction execution cycle
immediately preceding the SLEEP instruction is that of 1 state 2 states or more and prefetch
occurs in the last state, this puts in the SLEEP mode after execution of the SLEEP instruction,
and the SLEEP mode is cancelled by the address trap interrupt and transition is made to the
exception handling. The address to be stacked is 0264.
φ
Address bus
Interrupt
request
signal
Note: * Trap setting address
The underlines address is the one to be actually stacked.
NOP
SLEEP
NOP
instruc-
instruc-
instruc-
tion
tion
tion
pre-fetch
pre-fetch
pre-fetch
0260 0262
NOP
SLEEP
execution
execution
Figure 25.17 SLEEP Instruction (2)
Start of
exception
handling
0264
SP-2 SP-4
SLEEP
mode
0260
0262
*
0264
0266
:
Rev. 1.0, 02/00, page 547 of 1141
NOP
SLEEP
NOP
NOP
:

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