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30.3.4
Serial Interface Timing of HD64F2199
Table 30.17 Serial Interface Timing of HD64F2199
(Conditions: Vcc = AVcc = 4.0 V to 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C unless otherwise
specified.)
Item
Input clock cycle
Input clock pulse
width
Input clock rise time
Input clock fall time
Transmit data delay
time (clock sync)
Receive data setup
time (clock sync)
Receive data hold
time (clock sync)
Applicable
Symbol
Pins
t
SCK1
scyc
t
SCK1
SCKW
t
SCK1
SCKr
t
SCK1
SCKf
t
SO1
TXD
t
SI1
RXS
t
SI1
RXH
V
or V
IH
OH
SCK1
V
or V
IL
OL
t
SCKr
Figure 30.15 SCK1 Clock Timing
Values
Test
Min
Conditions
Asynchroniza-
4
tion
Clock
6
synchronization
0.4
100
100
t
t
SCKW
scyc
t
SCKf
Typ
Max
Unit
t
cyc
0.6
t
scyc
1.5
t
cyc
1.5
t
cyc
100
ns
ns
ns
Rev. 1.0, 02/00, page 911 of 1141
Figure
Figure
30.15
Figure
30.16
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