Capstan Phase Error Detector; Overview; Block Diagram - Hitachi H8S/2199 Hardware Manual

Single-chip microcomputer

Table of Contents

Capstan Phase Error Detector

The capstan phase control system must start operation after the capstan motor has reached the

specified speed by the speed control system. The capstan phase control system operates as

follows in record/playback mode:

• Record mode: Controls the tape running so that it may run at a specified speed together with

the speed control system.

• Playback mode: Controls the tape running so that the recorded track may be traced correctly.

Any error deviated from the reference phase is detected by the digital counter. This phase error

data and the speed error data is processed and added by the digital filter circuit to control the

PWM output. The phase and speed of the capstan, in turn, is control this PWM output.

The control signal of the capstan phase control in the record mode differ from that in playback

mode. In record mode, the control is performed by the DVCFG2 signal which is generated by

dividing the frequencies of the reference signal (REF30P or CREF) and the CFG signal. In

playback mode, it is performed by divided rising signal (DVCTL) of the reference signal

(CAPREF30) and the playback control pulse (PB-CTL).

The reference signal in record and playback modes are as follows:

• Record mode: 1/2Vsync signal extracted from the video signal to be recorded.

• Playback mode: Signal generated by dividing the PB-CTL signal (DVCTL) at its rising edge.

Figure 26.34 shows the block diagram of the capstan phase error detector.

Rev. 1.0, 02/00, page 648 of 1141