Additional V Signal Generator; 26.12.1 Overview - Hitachi H8S/2199 Hardware Manual

Single-chip microcomputer
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26.12

Additional V Signal Generator

26.12.1 Overview

The additional V signal generator outputs an additional vertical sync signal to take the place of
Vsync in special playback. It is activated at both edges of the HSW signal output by the head-
switch timing generator. The head-switch timing generator also outputs a V pulse signal
containing the additional vertical sync pulse itself, and an M level signal that defines the width of
the additional vertical sync signal including the equalizing pulses.
The additional V signal is output at a three-level output pin (V pulse).
Figure 26.43 shows the additional V signal control circuit.
HSW timing
Csync
generator
Sync signal detector
OSCH
Additional V
pulse generator
Additional V pulse
Figure 26.43 Additional V Pulse Control Circuit
HSW Timing Generator: This circuit generates signals that are synchronized with head
switching. It should be programmed to generate the Mlevel and Vpulse signals at edges of the
HSW signal (VideoFF). For details, see section 26.4, HSW (Head-switch) Timing Generator.
Sync Signal Detector: This circuit detects pulses of the width specified by VTR or HTR from the
signal input at the Csync pin and generates an internal horizontal sync signal (OSCH). The sync
signal detector has an interpolation function, so OSCH has a regular period even if there are
horizontal sync dropouts in the signal received at the pin. For details, see section 26.15, Sync
Signal Detector.
Rev. 1.0, 02/00, page 678 of 1141

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