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Horizontal Sync Signal Threshold Register (HTR)
Bit :
Initial value :
R/W :
HTR is an 8-bit write-only register that sets the threshold for the horizontal sync signal when the
signal is detected from the composite sync signal. The threshold is set by bits 3 to 0 (HTR3 to
HTR0). Bits 7 and 4 are reserved. If a read is attempted, an undetermined value is read out. It is
initialized to H'F0 by a reset, or in stand-by or module stop mode.
Figure 26.73 shows the threshold values and separated sync signals.
Hpuls
Csync
Counter value
H'00
SEPH
SEPV
[Legend]
TH
: Period of the horizontal sync signal (NTSC: 63.6, PAL: 64 [µs])
Hpuls
: Pulse width of the horizontal sync signal (NTSC, PAL: 4.7 [µs])
VVTH
: Value set as the threshold of the vertical sync signal
HVTH
: Value set as the threshold of the horizontal sync signal
SEPV
: Detected vertical sync signal
SEPH
: Detected horizontal sync signal (before complement)
Figure 26.73 Threshold Values and Separated Sync Signals
7
6
—
—
1
1
—
—
T H
VVTH
HVTH
5
4
HTR3
—
—
1
1
—
—
1/2 Hpuls
3
2
HTR2
HTR1
0
0
W
W
Hpuls
T H
VD interrupt
Rev. 1.0, 02/00, page 737 of 1141
1
0
HTR0
0
0
W
W
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