Register Configuration; Data Slicer Use Conditions - Hitachi H8S/2199 Hardware Manual

Single-chip microcomputer

Table of Contents

Register Configuration

Table 28.2 shows the data slicer registers.

Table 28.2 Register Configuration

Slice even-field mode register

Slice odd-field mode register

Slice line setting register 1

Slice line setting register 2

Slice line setting register 3

Slice line setting register 4

Slice detection register 1

Slice detection register 2

Slice detection register 3

Slice detection register 4

Slice data register 1

Slice data register 2

Slice data register 3

Slice data register 4

Notes: 1. Only 0 can be written to clear the flag (bit 14).

2. Bits 7 to 0 are cleared when 1 is written to bit 7 of the corresponding slice line setting

3. Lower 16 bits of the address.

Table 28.3 indicates the conditions of use of the data slicer.

Table 28.3 Data Slicer Use Conditions

Sync Signal Input for Sync Separation

Sync separation signal input from CVin2

Sync separation signal input from Csync

Hsync or Vsync separation signals

Rev. 1.0, 02/00, page 802 of 1141

Initial Value