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17.2
Register Descriptions
17.2.1
Watchdog Timer Counter (WTCNT)
Bit :
Initial value :
R/W :
TCNT is an 8-bit readable/writable* up-counter.
When the TME bit is set to 1 in WTCSR, WTCNT starts counting pulses generated from the
internal clock source selected by bits CKS2 to CKS0 in WTCSR. When the count overflows
(changes from H'FF to H'00), the OVF flag in WTCSR is set to 1.
WTCNT is initialized to H'00 by a reset, or when the TME bit is cleared to 0.
Note: * WTCNT is write-protected by a password to prevent accidental overwriting. For
details see section 17.2.4, Notes on Register Access.
17.2.2
Watchdog Timer Control/Status Register (WTCSR)
Bit :
OVF
Initial value :
R/W :
R/(W)*
Note: * Only 0 can be written to clear the flag.
WTCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to
be input to WTCNT, and the timer mode.
WTCSR is initialized to H'00 by a reset.
Note: * WTCSR is write-protected by a password to prevent accidental overwriting. For
details see section 17.2.4, Notes on Register Access.
Rev. 1.0, 02/00, page 350 of 1141
7
6
0
0
R/W
R/W
7
6
WT/
TME
0
0
R/W
5
4
0
0
R/W
R/W
5
4
—
RST/
0
0
R/W
—
3
2
0
0
R/W
R/W
3
2
CKS2
CKS1
0
0
R/W
R/W
1
0
0
0
R/W
R/W
1
0
CKS0
0
0
R/W
R/W
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