Hitachi H8S/2199 Hardware Manual page 844

All of the row registers 1 to 12 have the same specifiable format.
When the OSD display update timing control bit (DTMV) is 1, the OSD display is updated to the
row register settings in synchronous with the Vsync signal (OSDV).
Bit 7    Button Pattern Specification Bit (BPTNn n=1 to 12): Sets the button pattern for the nth
row. For button specification, refer to section 29.3.7, Display Data RAM (OSDRAM).
Bit 7
BPTNn
Description
0 Pattern causing buttons in the nth row to appear to be raised
1 Pattern causing buttons in the nth row to appear to be lowered
Bit 6    Character Size Specification Bit (SZn, n =1 to 12): Sets the size of characters. The
border width and button width also change according to the character size. These settings are
common to superimposed and text display modes and to C.Video output and digital outputs.
Bit 6
SZn
Description
Character display size: single height × single width
0
Character display size: double height × double width
1
Rev. 1.0, 02/00, page 841 of 1141
AA
(Initial value)
AA
(Initial value)