Hitachi H8/500 Series Hardware Manual

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Page 1 H8/532 Hardware Manual Downloaded from Elcodis.com electronic components distributor...
Page 2 This manual gives a hardware description of the H8/532. For details of the instruction set, refer to the H8/500 Series Programming Manual, which applies to all chips in the H8/500 Series. * ZTAT (Zero Turn-Around Time) is a registered trademark of Hitachi, Ltd.
Page 3: Table Of Contents
Contents Section 1 Overview Features ··································································································································1 Block Diagram ·······················································································································4 Pin Arrangements and Functions ···························································································5 1.3.1 Pin Arrangement ·········································································································5 1.3.2 Pin Functions ··············································································································8 Section 2 MCU Operating Modes and Address Space Overview ······························································································································23 Mode Descriptions ···············································································································24 Address Space Map ··············································································································25 2.3.1 Page Segmentation ····································································································25 2.3.2 Page 0 Address Allocations ······················································································27 Mode Control Register (MDCR) ·························································································29 Section 3 CPU...
Page 4 3.5.8 System Control Instructions ······················································································59 3.5.9 Short-Format Instructions ·························································································62 Operating Modes ··················································································································62 3.6.1 Minimum Mode ········································································································62 3.6.2 Maximum Mode ········································································································63 Basic Operational Timing ····································································································63 3.7.1 Overview ···················································································································63 3.7.2 On-Chip Memory Access Cycle ···············································································64 3.7.3 Pin States during On-Chip Memory Access ·····························································65 3.7.4 Register Field Access Cycle (Addresses H'FF80 to H'FFFF) ···································66 3.7.5 Pin States during Register Field Access (Addresses H'FF80 to H'FFFF) ·················67 3.7.6 External Access Cycle ·······························································································68...
Page 5 4.8.1 Instructions that Disable Interrupts ···········································································92 4.8.2 Disabling of Exceptions Immediately after a Reset ··················································93 4.8.3 Disabling of Interrupts after a Data Transfer Cycle ··················································93 Stack Status after Completion of Exception Handling ························································94 4.9.1 PC Value Pushed on Stack for Trace, Interrupts, Trap Instructions, and Zero Divide Exceptions ·······································96 4.9.2 PC Value Pushed on Stack for Address Error and Invalid Instruction Exceptions ······························································································96...
Page 6 6.3.1 Data Transfer Cycle ································································································118 6.3.2 DTC Vector Table ···································································································120 6.3.3 Location of Register Information in Memory ·························································122 6.3.4 Length of Data Transfer Cycle ················································································122 Procedure for Using the DTC ····························································································124 Example ·····························································································································125 Section 7 Wait-State Controller Overview ····························································································································127 7.1.1 Features ···················································································································127 7.1.2 Block Diagram ········································································································128 7.1.3 Register Configuration ····························································································128 Wait-State Control Register ·······························································································129...
Page 7 9.5.3 Pin Functions in Each Mode ···················································································156 Port 5 ··································································································································157 9.6.1 Overview ·················································································································157 9.6.2 Port 5 Registers ·······································································································158 9.6.3 Pin Functions in Each Mode ···················································································159 9.6.4 Built-in MOS Pull-Up ·····························································································161 Port 6 ··································································································································163 9.7.1 Overview ·················································································································163 9.7.2 Port 6 Registers ·······································································································164 9.7.3 Pin Functions in Each Mode ···················································································165 9.7.4 Built-in MOS Pull-Up ·····························································································167 Port 7 ··································································································································167...
Page 8 10.4.4 Setting of FRC Overflow Flag (OVF) ·····································································195 10.5 CPU Interrupts and DTC Interrupts ···················································································195 10.6 Synchronization of Free-Running Timers 1 to 3 ································································196 10.6.1 Synchronization after a Reset ·················································································196 10.6.2 Synchronization by Writing to FRCs ······································································196 10.7 Sample Application ············································································································200 10.8 Application Notes ··············································································································200 Section 11 8-Bit Timer 11.1 Overview ····························································································································207...
Page 9 Section 13 Watchdog Timer 13.1 Overview ····························································································································235 13.1.1 Features ···················································································································235 13.1.2 Block Diagram ········································································································236 13.1.3 Register Configuration ····························································································236 13.2 Register Descriptions ·········································································································237 13.2.1 Timer Counter TCNT - H'FFED ·············································································237 13.2.2 Timer Control/Status Register (TCSR) - H'FFEC (Read), H'FFED (Write) ··········237 13.2.3 Notes on Register Access ························································································239 13.3 Operation ····························································································································240 13.3.1 Watchdog Timer Mode ···························································································240...
Page 10 15.1.1 Features ···················································································································273 15.1.2 Block Diagram ········································································································274 15.1.3 Input Pins ················································································································275 15.1.4 Register Configuration ····························································································275 15.2 Register Descriptions ·········································································································276 15.2.1 A/D Data Registers (ADDR) - H'FFE0 to H'FFE7 ·················································276 15.2.2 A/D Control/Status Register (ADCSR) - H'FFE8 ··················································277 15.3 CPU Interface ·····················································································································279 15.4 Operation ····························································································································280 15.4.1 Single Mode ············································································································281 15.4.2 Scan Mode ··············································································································284...
Page 11 18.3 Software Standby Mode ·····································································································308 18.3.1 Transition to Software Standby Mode ····································································308 18.3.2 Software Standby Control Register (SBYCR) ························································309 18.3.3 Exit from Software Standby Mode ·········································································310 18.3.4 Sample Application of Software Standby Mode ····················································310 18.3.5 Application Notes ···································································································311 18.4 Hardware Standby Mode ····································································································312 18.4.1 Transition to Hardware Standby Mode ···································································312 18.4.2 Recovery from Hardware Standby Mode ·······························································312 18.4.3 Timing Sequence of Hardware Standby Mode ·······················································313...
Page 12 Appendix C I/O Port Schematic Diagrams Schematic Diagram of Port 1 ·····························································································407 Schematic Diagram of Port 2 ·····························································································413 Schematic Diagram of Port 3 ·····························································································414 Schematic Diagram of Port 4 ·····························································································415 Schematic Diagram of Port 5 ·····························································································416 Schematic Diagram of Port 6 ·····························································································417 Schematic Diagram of Port 7 ·····························································································418 Schematic Diagram of Port 8 ·····························································································423 Schematic Diagram of Port 9 ·····························································································424...
Page 13 Figures Block Diagram ···················································································································4 Pin Arrangement (CP-84, Top View) ·················································································5 Pin Arrangement (CG-84, Top View) ················································································6 Pin Arrangement (FP-80A, Top View) ··············································································7 Address Space in Each Mode ··························································································26 Map of Page 0 ··················································································································28 CPU Operating Modes ·····································································································32 Registers in the CPU ········································································································33 Stack Pointer ····················································································································34 Combinations of Page Registers with Other Registers ····················································38 Short Absolute Addressing Mode and Base Register ······················································39...
Page 14 Programmable Wait Mode ·····························································································131 Pin Wait Mode ···············································································································132 Pin Auto-Wait Mode ······································································································133 Block Diagram of Clock Pulse Generator ·····································································135 Connection of Crystal Oscillator (Example) ·································································136 Crystal Oscillator Equivalent Circuit ·············································································136 Notes on Board Design around External Crystal ···························································137 External Clock Input (Example) ····················································································137 Phase Relationship of ø...
Page 15 10-11 Square-Wave Output (Example) ····················································································200 10-12 FRC Write-Clear Contention ·························································································201 10-13 FRC Write-Increment Contention ·················································································202 10-14 Contention between OCR Write and Compare-Match ··················································203 11-1 Block Diagram of 8-Bit Timer ·······················································································208 11-2 Count Timing for External Clock Input ·········································································215 11-3 Setting of Compare-Match Flags ···················································································216 11-4 Timing of Timer Output ·································································································216 11-5...
Page 16 18-2 Hardware Standby Sequence ·························································································313 19-1 Execution Cycle of Instruction Synchronized with E Clock in Expanded Modes (Maximum Synchronization Delay) ··············································································316 19-2 Execution Cycle of Instruction Synchronized with E Clock in Expanded Modes (Minimum Synchronization Delay) ···············································································317 20-1 Example of Circuit for Driving a Darlington Transistor Pair ········································322 20-2 Example of Circuit for Driving an LED ········································································322 20-3...
Page 17 C-7 (d) Schematic Diagram of Port 7, Pins P7 , P7 and P7 ····················································421 C-7 (e) Schematic Diagram of Port 7, Pin P7 ··········································································422 Schematic Diagram of Port 8 ·························································································423 C-9 (a) Schematic Diagram of Port 9, Pins P9 and P9 ···························································424 C-9 (b) Schematic Diagram of Port 9, Pins P9 , P9...
Page 18 3-13 Shift Instructions ··············································································································55 3-14 Bit-Manipulation Instructions ··························································································56 3-15 Branching Instructions ·····································································································57 3-16 System Control Instructions ····························································································59 3-17 Short-Format Instructions and Equivalent General Formats ···········································62 4-1 (a) Exceptions and Their Priority ··························································································81 4-1 (b) Instruction Exceptions ······································································································81 Exception Vector Table ····································································································84 Stack after Exception Handling Sequence ·······································································94 Interrupt Controller Registers ··························································································99 Interrupts, Vectors, and Priorities ··················································································102...
Page 19 10-3 Free-Running Timer Interrupts ······················································································195 10-4 Synchronization by Writing to FRCs ············································································196 10-5 Effect of Changing Internal Clock Sources ···································································204 11-1 Input and Output Pins of 8-Bit Timer ············································································209 11-2 8-Bit Timer Registers ·····································································································209 11-3 8-Bit Timer Interrupts ····································································································218 11-4 Priority Order of Timer Output ······················································································223 11-5 Effect of Changing Internal Clock Sources ···································································223...
Page 20 18-1 Power-Down State ·········································································································307 18-2 Software Standby Control Register ···············································································309 20-1 Absolute Maximum Ratings ··························································································319 20-2 DC Characteristics ·········································································································320 20-3 Allowable Output Current Sink Values ·········································································321 20-4 Bus Timing ····················································································································322 20-5 Control Signal Timing ···································································································324 20-6 Timing Conditions of On-Chip Supporting Modules ····················································325 20-7 A/D Converter Characteristics ·······················································································326 A-1 (a) Machine Language Coding [General Format] ·······························································346...
Page 21 C-7 (c) Port 7 Port Read (Pin P7 ) ·····························································································420 C-7 (d) Port 7 Port Read (Pins P7 –P7 ) ····················································································421 C-7 (e) Port 7 Port Read (Pin P7 ) ·····························································································422 C-9 (a) Port 9 Port Read (Pins P9 , P9 ) ····················································································424 C-9 (b) Port 9 Port Read (Pins P9 –P9...
Page 22: Section 1 Overview
Section 1 Overview 1.1 Features The H8/532 is an original Hitachi CMOS microcomputer unit (MCU) comprising a high- performance CPU core plus a full range of supporting functions—an entire system integrated onto a single chip. The CPU features a highly orthogonal instruction set that permits addressing modes and data sizes to be specified independently in each instruction.
Page 23: Addressing Modes
Table 1-1 Features Feature Description General-register machine • Eight 16-bit general registers • Five 8-bit and two 16-bit control registers High speed • Maximum clock rate: 10MHz (oscillator frequency: 20MHz) Expanded operating modes supporting external memory • Minimum mode: up to 64K-byte address space •...
Page 24 Table 1-1 Features (cont) Feature Description Serial com- • Asynchronous or synchronous mode (selectable) munication • Full duplex: can send and receive simultaneously interface (SCI) • Built-in baud rate generator A/D converter • 10-Bit resolution • 8 channels, controllable in single mode or scan mode (selectable) •...
Page 25: Block Diagram
1.2 Block Diagram Figure 1-1 shows a block diagram of the H8/532 chip. Port 1 Port 2 Port 3 EXTAL Clock Gener- XTAL P4 /A ator P4 /A P4 /A P4 /A Wait- P4 /A PROM/Mask State STBY P4 /A ROM 32 kByte 1 kByte Controller...
Page 26: Pin Arrangements And Functions
1.3 Pin Arrangements and Functions 1.3.1 Pin Arrangement Figure 1-2 shows the pin arrangement of the CP-84 package. Figure 1-3 shows the pin arrangement of the CG-84 package. Figure 1-4 shows the pin arrangement of the FP-80A package. 11 10 9 1 84 83 82 81 80 79 78 77 76 75 P2 /R/W P8 /AN...
Page 27 11 10 9 1 84 83 82 81 80 79 78 77 76 75 P2 /R/W P8 /AN P2 /DS P8 /AN P2 /RD P8 /AN P2 /WR P8 /AN P8 /AN P8 /AN P8 /AN P8 /AN STBY LCC-84 P7 /FTOA P7 /FTOB /FTCI P7 /FTOB /FTCI...
Page 28 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P2 /R/W P8 /AN P2 /DS P8 /AN P2 /RD P2 /WR P8 /AN P8 /AN P8 /AN P8 /AN P8 /AN P8 /AN STBY...
Page 29 1.3.2 Pin Functions Pin Arrangements in Each Operating Mode: Table 1-2 lists the arrangements of the pins of the CP-84 and CG-84 packages in each operating mode. Table 1-3 lists the arrangements for the FP- 80A package. Table 1-2 Pin Arrangements in Each Operating Mode (CP-84, CG-84) Pin Name Expanded Minimum Expanded Maximum...
Page 30 Table 1-2 Pin Arrangements in Each Operating Mode (CP-84, CG-84) (cont) Pin Name Expanded Minimum Expanded Maximum Single-Chip PROM Modes Modes Mode Mode 1 Mode 2 Mode 3 Mode 4 Mode 7 Mode STBY STBY STBY STBY STBY Notes: 1. For the PROM mode, see section 17, “ROM.” 2.
Page 31 Table 1-2 Pin Arrangements in Each Operating Mode (CP-84, CG-84) (cont) Pin Name Expanded Minimum Expanded Maximum Single-Chip PROM Modes Modes Mode Mode 1 Mode 2 Mode 3 Mode 4 Mode 7 Mode / TMCI / TMCI / TMCI / TMCI / TMCI / FTI / FTI...
Page 32 Table 1-2 Pin Arrangements in Each Operating Mode (CP-84, CG-84) (cont) Pin Name Expanded Minimum Expanded Maximum Single-Chip PROM Modes Modes Mode Mode 1 Mode 2 Mode 3 Mode 4 Mode 7 Mode / FTOB / FTOB / P7 / FTOB / P7 / FTOB / P7...
Page 33 Table 1-3 Pin Arrangements in Each Operating Mode (FP-80A) Pin Name Expanded Minimum Expanded Maximum Single-Chip PROM Modes Modes Mode Mode 1 Mode 2 Mode 3 Mode 4 Mode 7 Mode STBY STBY STBY STBY STBY Notes: 1. For the PROM mode, see section 17, “ROM.” 2.
Page 34 Table 1-3 Pin Arrangements in Each Operating Mode (FP-80A) (cont) Pin Name Expanded Minimum Expanded Maximum Single-Chip PROM Modes Modes Mode Mode 1 Mode 2 Mode 3 Mode 4 Mode 7 Mode Notes: 1. For the PROM mode, see section 17, “ROM.” 2.
Page 35 Table 1-3 Pin Arrangements in Each Operating Mode (FP-80A) (cont) Pin Name Expanded Minimum Expanded Maximum Single-Chip PROM Modes Modes Mode Mode 1 Mode 2 Mode 3 Mode 4 Mode 7 Mode / TMCI / TMCI / TMCI / TMCI / TMCI / FTI / FTI...
Page 36 Table 1-3 Pin Arrangements in Each Operating Mode (FP-80A) (cont) Pin Name Expanded Minimum Expanded Maximum Single-Chip PROM Modes Modes Mode Mode 1 Mode 2 Mode 3 Mode 4 Mode 7 Mode / FTOA / FTOA / FTOA / FTOA / FTOA / FTOA / FTOA...
Page 37 Pin Functions: Table 1-4 gives a concise description of the function of each pin. Table 1-4 Pin Functions Pin No. CP-84, Type Symbol CG-84 FP-80A I/O Name and Function Power 16, 55 5, 42 Power: Connected to the power supply (+5V). Connect both V pins to the system power supply (+5V).
Page 38 Table 1-4 Pin Functions (cont) Pin No. CP-84, Type Symbol CG-84 FP-80A I/O Name and Function System BREQ Bus Request: Sent by an external device to the control H8/532 chip to request the bus right. STBY Standby: A transition to the hardware standby mode (a power-down state) occurs when a Low input is received at the STBY pin.
Page 39 Table 1-4 Pin Functions (cont) Pin No. CP-84, Type Symbol CG-84 FP-80A I/O Name and Function Interrupt NonMaskable Interrupt: Highest-signals priority interrupt request. The port 1 control register (P1CR) determines whether the interrupt is requested on the rising or falling edge of the NMI input. Interrupt Request 0 and 1: Maskable interrupt request pins.
Page 40 Table 1-4 Pin Functions (cont) Pin No. CP-84, Type Symbol CG-84 FP-80A I/O Name and Function 16-Bit free- FTOA FRT Output Compare A (channels 1, 2, and 3): running FTOA Output pins for the output compare A function timer (FRT) FTOA of the free-running timer channels 1, 2, and 3.
Page 41 Table 1-4 Pin Functions (cont) Pin No. CP-84, Type Symbol CG-84 FP-80A I/O Name and Function Serial com- TXD Transmit Data: Data output pins for the munication serial communication interface. interface signals Receive Data: Data input pins for the serial communication interface. I/O Serial Clock: Input/output pin for the serial interface clock.
Page 42 Table 1-4 Pin Functions (cont) Pin No. CP-84, Type Symbol CG-84 FP-80A I/O Name and Function Parallel – P5 50 – 43 37 – 30 I/O Port 5: An 8-bit input/output port. The direction of each bit is determined by the port 5 data direction register (P5DDR).
Page 43: Section 2 Mcu Operating Modes And Address Space
Section 2 MCU Operating Modes and Address Space 2.1 Overview The H8/532 microcomputer unit (MCU) operates in five modes numbered 1, 2, 3, 4, and 7. The mode is selected by the inputs at the mode pins (MD to MD ) at the instant when the chip comes out of a reset.
Page 44: Mode Descriptions
2.2 Mode Descriptions The five MCU modes are described below. For further information on the I/O pin functions in each mode, see section 9, “I/O Ports.” Mode 1 (Expanded Minimum Mode): Mode 1 supports a maximum 64K-byte address space which does not include any on-chip ROM. Ports 1 to 5 are used for bus lines and bus control signals as follows: Control signals: Ports 1* and 2 Data bus:...
Page 45: Address Space Map
Mode 4 (Expanded Maximum Mode): Mode 4 supports a maximum 1M-byte address space of which the first 32K bytes are in on-chip ROM. Ports 1 to 6 are used for bus lines and bus control signals as follows: Control signals: Ports 1* and 2 Data bus: Port 3 Address bus:...
Page 46: Address Space In Each Mode
Expanded minimum modes Expanded maximum modes Single-chip mode Address Mode 1 Mode 2 Mode 3 Mode 4 Mode 7 H'00000 Page 0 H'0FFFF H'10000 Page 1 H'1FFFF H'F0000 Page 15 H'FFFFF On-chip On- or off-chip (selectable) Off-chip Figure 2-1 Address Space in Each Mode Downloaded from Elcodis.com electronic components distributor...
Page 47: Address Allocations
2.3.2 Page 0 Address Allocations The high and low address areas in page 0 are reserved for registers and vector tables. Vector Tables: The low address area contains the exception vector table and DTC vector table. The CPU accesses the exception vector table to obtain the addresses of user-coded exception- handling routines.
Page 48 Figure 2-2 is a map of page 0 of the address space. H'0000 Exception vector table DTC vector table On-chip ROM (modes 2, 4, and 7) or external memory (modes 1 and 3) H'7FFF H'8000 H'FB80 On-chip RAM (when enabled) H'FF80 On-chip register field H'FFFF...
Page 49: Mode Control Register (Mdcr)
2.4 Mode Control Register (MDCR) Another control register in the register field in page 0 is the mode control register (MDCR). The inputs at the mode pins are latched in this register on the rising edge of the signal. The mode control register can be read by the CPU, but not written.
Page 50: Section 3 Cpu
The H8/532 chip has the H8/500 Family CPU: a high-speed central processing unit designed for realtime control of a wide range of medium-scale office and industrial equipment. Its Hitachi- original architecture features eight 16-bit general registers, internal 16-bit data paths, and an optimized instruction set.
Page 51: Address Space
3.1.2 Address Space The address space size depends on the operating mode. The H8/532 MCU has five operating modes, which are selected by the input to the mode pins to MD ) when the chip comes out of a reset. The CPU, however, has only two operating modes.
Page 52: Register Configuration
3.1.3 Register Configuration Figure 3-2 shows the register structure of the CPU. There are two groups of registers: the general registers (Rn) and control registers (CR). General registers (Rn) (FP) FP: Frame Pointer (SP) SP: Stack Pointer Control registers (CR) PC: Program Counter C C R SR: Status Register...
Page 53: Cpu Register Descriptions
3.2 CPU Register Descriptions 3.2.1 General Registers All eight of the 16-bit general registers are functionally alike; there is no distinction between data registers and address registers. When these registers are accessed as data registers, either byte or word size can be selected. R6 and R7, in addition to functioning as general registers, have special assignments.
Page 54: Control Registers
3.2.2 Control Registers The CPU control registers (CR) include a 16-bit program counter (PC), a 16-bit status register (SR), four 8-bit page registers, and one 8-bit base register (BR). Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU will execute.
Page 55: Interrupt Mask Levels
Table 3-1 Interrupt Mask Levels Mask Mask Bits Priority Level Interrupts Accepted High Level 7 and NMI Levels 6 to 7 and NMI Levels 5 to 7 and NMI Levels 4 to 7 and NMI Levels 3 to 7 and NMI Levels 2 to 7 and NMI Levels 1 to 7 and NMI Table 3-2 Interrupt Mask Bits after an Interrupt is Accepted...
Page 56 The specific changes that occur in the condition code bits when each instruction is executed are listed in appendix A.1 “Instruction Tables.” See the H8/500 Series Programming Manual for further details. Page Registers: The code page register (CP), data page register (DP), extended page register (EP), and stack page register (TP) are 8-bit registers that are used only in the maximum mode.
Page 57: Combinations Of Page Registers With Other Registers
Page register PC or general register 8 Bits 16 Bits @ aa : 16 24 Bits (effective address) Figure 3-4 Combinations of Page Registers with Other Registers Code Page Register (CP): The code page register and the program counter combine to generate a 24-bit program code address.
Page 58: Short Absolute Addressing Mode And Base Register
are saved and restored in exception handling. Data Page Register (DP): The data page register combines with general registers R0 to R3 to generate a 24-bit effective address. The data page register contains the upper 8 bits of the address. It is used to calculate effective addresses in the register indirect addressing mode using R0 to R3, and in the 16-bit absolute addressing mode (@aa:16).
Page 59: Initial Register Values
3.2.3 Initial Register Values When the CPU is reset, its internal registers are initialized as shown in table 3-3. Note that the stack pointer (R7) and base register (BR) are not initialized to fixed values. Also, of the page registers used in maximum mode, only the code page register (CP) is initialized; the other three page registers come out of the reset state with undetermined values.
Page 60: Data Formats
Table 3-3 Initial Values of Registers Initial Value Register Minimum Mode Maximum Mode General registers Undetermined Undetermined R7 – R0 Control registers Loaded from vector table Loaded from vector table H'070x H'070x T– – – – I2I1I0 – – – – NZVC (x: undetermined) (x: undetermined) Undetermined...
Page 61: Data Formats In Memory
Bit data locations are specified by bit number. Bit 15 is the most significant bit. Bit 0 is the least significant bit. BCD and byte data are stored in the lower 8 bits of a general register. Word data use all 16 bits of a general register. Longword data use two general registers: the upper 16 bits are stored in Rn (n must be an even number);...
Page 62: Data Formats In Memory
Table 3-5 Data Formats in Memory Data Type Data Format 1-Bit (in byte operand data) Address n 1-Bit (in word operand data) Even address Odd address Byte Address n Word Even address Upper 8 bits Odd address Lower 8 bits When the stack is accessed in exception processing (to save or restore the program counter, code page register, or status register), word access is always performed, regardless of the actual data size.
Page 63: Instructions
Table 3-6 Data Formats on the Stack Data Type Data Format Byte data on stack Even address Don’t-care Odd address Word data on stack Even address Upper 8 bits Odd address Lower 8 bits 3.4 Instructions 3.4.1 Basic Instruction Formats There are two basic CPU instruction formats: the general format and the special format.
Page 64: Addressing Modes
• (Example of prefix code in DADD instruction) Effective address Prefix code Operation code 10100rrr 00000000 10100rrr Special Format: In this format the operation code comes first, followed by the effective address field and effective address extension. This format is used in branching instructions, system control instructions, and other instructions that can be executed faster if the operation is specified before the operand.
Page 65 Table 3-7 Addressing Modes Addressing Mode Mnemonic EA Field EA Extension Register direct 1 0 1 0 Sz r r r None Register indirect 1 1 0 1 Sz r r r None Register indirect @(d:8,Rn) 1 1 1 0 Sz r r r Displacement (1 byte) with displacement @(d:16,Rn)
Page 66: Effective Address Calculation
3.4.3 Effective Address Calculation Table 3-8 explains how the effective address is calculated in each addressing mode. Table 3-8 Effective Address Calculation Addressing Mode Effective Address Calculation Effective Address Register direct — Operand is contents of 1010Sz Register indirect — 1101Sz Or TP or EP Register indirect...
Page 67 Table 3-8 Effective Address Calculation (cont) Addressing Mode Effective Address Calculation Effective Address Absolute address — @aa:8 H'00 0000Sz101 EA extension data @aa:16 — 0001Sz101 EA extension data Immediate — Operand is 1-byte EA #xx:8 extension data. 00000100 #xx:16 — Operand is 2-byte EA 00001100 extension data.
Page 68 Old SP-2 (upper byte) Old SP-2 (lower byte) MOV.W SP, @–SP MOV.W @SP+.SP Downloaded from Elcodis.com electronic components distributor...
Page 69: Instruction Set
Tables 3-10 to 3-16 give a concise summary of the instructions in each functional category. The MOV, ADD, and CMP instructions have special short formats, which are listed in table 3-17. For detailed descriptions of the instructions, refer to the H8/500 Series Programming Manual. The notation used in tables 3-10 to 3-17 is defined below.
Page 70 Operation Notation General register (destination) General register (source) General register (EAd) Destination operand (EAs) Source operand Condition code register N (negative) bit of CCR Z (zero) bit of CCR V (overflow) bit of CCR C (carry) bit of CCR Control register Program counter Code page register Stack pointer...
Page 71: Data Transfer Instructions
3.5.2 Data Transfer Instructions Table 3-10 describes the seven data transfer instructions. Table 3-10 Data Transfer Instructions Instruction Size* Function (EAs) → (EAd), #IMM → (EAd) Data transfer Moves data between two general registers, or between MOV:G a general register and memory, or moves immediate data MOV:E to a general register or memory.
Page 72: Arithmetic Instructions
3.5.3 Arithmetic Instructions Table 3-11 describes the 17 arithmetic instructions. Table 3-11 Arithmetic Instructions Instruction Size Function Rd ± (EAs) → Rd, (EAd) ± #IMM → (EAd) Arithmetic operations Performs addition or subtraction on data in a general ADD:G register and data in another general register or memory, or ADD:Q on immediate data and data in a general register or memory.
Page 73: Logic Operations
Table 3-11 Arithmetic Instructions (cont) Instruction Size Function (<bit 7> of <Rd>) → (<bits 15 to 8> of <Rd>) Arithmetic EXTS operations Converts byte data in a general register to word data by extending the sign bit. 0 → (<bits 15 to 8> of <Rd>) EXTU Converts byte data in a general register to word data by padding with zero bits.
Page 74: Shift Operations
3.5.5 Shift Operations Table 3-13 lists the eight shift instructions. Table 3-13 Shift Instructions Instruction Size Function (EAd) shift → (EAd) Shift SHAL operations Performs an arithmetic shift operation on general register SHAR or memory contents. (EAd) shift → (EAd) SHLL Performs a logical shift operation on general register or SHLR...
Page 75: Bit Manipulations
3.5.6 Bit Manipulations Table 3-14 describes the four bit-manipulation instructions. Table 3-14 Bit-Manipulation Instructions Instruction Size Function ¬ (<bit-No.> of <EAd>) → Z, BSET 1 → (<bit-No.> of <EAd>) manipu- lations Tests a specified bit in a general register or memory, then sets the bit to “1.”...
Page 76: Branching Instructions
3.5.7 Branching Instructions Table 3-15 describes the 11 branching instructions. Table 3-15 Branching Instructions Instruction Size Function Branch — Branches if condition cc is true. Mnemonic Description Condition Always (true) True BRA (BT) Never (false) False BRN (BF) C ∨ Z = 0 High C ∨...
Page 77 Table 3-15 Branching Instructions (cont) Instruction Size Function Branch — Returns from a subroutine in a different page. PRTS — Returns from a subroutine in the same page and adjusts the stack pointer. — Returns from a subroutine in a different page and adjusts PRTD the stack pointer.
Page 78: System Control Instructions
3.5.8 System Control Instructions Table 3-16 describes the 12 system control instructions. Table 3-16 System Control Instructions Instruction Size Function System — Generates a trap exception with a specified vector number. TRAPA control — Generates a trap exception if the V bit is set to “1” when TRAP/VS the instruction is executed.
Page 79 Specifically, the LDC.B and STC.B instructions are executed as follows. The following applies only to the stack-pointer addressing modes. In addressing modes that do not use the stack pointer, byte data access is performed as specified by the assembler mnemonic. STC.B EP, @–SP When word data access is applied to EP, both EP and DP are accessed.
Page 80 LDC.B @SP+, CCR When word data access is applied to CCR, only CCR is accessed. This instruction loads CCR from address SP (old) +1. Note that the value in address SP (old) is not loaded. Old SP New SP – 2 Old SP + 1 New SP –...
Page 81: Operating Modes
3.5.9 Short-Format Instructions The ADD, CMP, and MOV instructions have special short formats. Table 3-17 lists these short formats together with the equivalent general formats. The short formats are a byte shorter than the corresponding general formats, and most of them execute one state faster.
Page 82: Maximum Mode
3.6.2 Maximum Mode In the maximum mode the page registers are valid, expanding the maximum address space to 1M byte. The address space is divided into 64k-byte pages. The pages are separate; it is not possible to move continuously across a page boundary. It is possible to move from one page to another with branching instructions (PJMP, PJSR, PRTS, PRTD).
Page 83: On-Chip Memory Access Cycle
Access to External Devices: The access cycle consists of three states. The data bus is 8 bits wide. Figure 3-10 (a) and (b) shows the external access cycle. Additional wait states (Tw) can be inserted by the wait-state controller (WSC). 3.7.2 On-Chip Memory Access Cycle Memory cycle T state...
Page 84: Pin States During On-Chip Memory Access
3.7.3 Pin States during On-Chip Memory Access T state T state ø to A R/W (read access) R/W (write access) “High” AS, DS, RD, WR High-impedance D to D Figure 3-7 Pin States during Access to On-Chip Memory Downloaded from Elcodis.com electronic components distributor...
Page 85: Register Field Access Cycle (Addresses H'ff80 To H'ffff)
3.7.4 Register Field Access Cycle (Addresses H'FF80 to H'FFFF) Memory cycle T state T state T state ø Internal address bus Address Internal Read signal Internal data bus Read data (read access) Internal Write signal Internal data bus Write data (write access) Figure 3-8 Register Field Access Timing Downloaded from...
Page 86: Pin States During Register Field Access (Addresses H'ff80 To H'ffff)
3.7.5 Pin States during Register Field Access (Addresses H'FF80 to H'FFFF) T state T state T state ø to A R/W (read access) R/W (write access) “High” AS, DS, RD, WR High-impedance D to D Figure 3-9 Pin States during Register Field Access Downloaded from Elcodis.com electronic components distributor...
Page 87: External Access Cycle
3.7.6 External Access Cycle Read cycle T state T state T state ø –A Address “High” D –D Read data Figure 3-10 (a) External Access Cycle (Read Access) Downloaded from Elcodis.com electronic components distributor...
Page 88: Cpu States
Write cycle T state T state T state ø –A Address “High” D –D Write data Figure 3-10 (b) External Access Cycle (Write Access) 3.8 CPU States 3.8.1 Overview The CPU has five states: the program execution state, exception-handling state, bus-released state, reset state, and power-down state.
Page 89: Operating States
State Program execution state The CPU executes program instructions in sequence. Exception-handling state A transient state in which the CPU executes a hardware sequence (saving the program counter and status register, fetching a vector from the vector table, etc.) triggered by a reset, interrupt, or other exception.
Page 90: Program Execution State
BREQ = “1” BREQ = “0” Program execution state SLEEP BREQ = “0” SLEEP instruction BREQ = “1” instruction End of with standby exception flag set Sleep mode handling Bus-released state Request for exception handling Interrupt request Exception-handling Software standby mode state STBY = “1”, RES = “0”...
Page 91: Bus-Released State
In the hardware exception-handling sequence the CPU does the following: 1. Saves the program counter and status register (in minimum mode) or program counter, code page register, and status register (in maximum mode) to the stack. 2. Clears the T bit in the status register to “0.” 3.
Page 92: Bus-Right Release Cycle (During On-Chip Memory Access Cycle)
Timing Charts: Timing charts of the operation by which the bus is released are shown in figure 3-13 for the case of bus release during an on-chip memory read cycle, in figure 3-14 for bus release during an external memory read cycle, and in figure 3-15 for bus release while the CPU is performing an internal operation.
Page 93: Bus-Right Release Cycle (During External Access Cycle)
External access cycle Bus-right release cycle CPU cycle ø –A D –D RD, WR R/W, DS BREQ BACK (1) The BREQ pin is sampled at the start of the T state and the Low level is detected. (2) At the end of the external access cycle, the BACK pin goes Low and the CPU releases the bus. (3) The BREQ pin is sampled at the T state and a High level is detected.
Page 94: Bus-Right Release Cycle (During Internal Cpu Operation)
External access cycle Bus-right release cycle CPU cycle ø –A D –D RD, WR R/W, DS BREQ BACK (1) The BREQ pin is sampled at the start of a T state and the Low level is detected. (2) At the end of the internal operation cycle, the BACK pin goes Low and the CPU releases the bus. (3) The BREQ pin is sampled at the T state and a High level is detected.
Page 95 Notes: The BREQ signal must be held Low until BACK goes Low. If BREQ returns to the High level before BACK goes Low, the bus release operation may be executed incorrectly. To leave the bus-released state, the High level at the BREQ pin must be sampled two times. If the BREQ returns to Low before it is sampled two times, the bus released cycle will not end.
Page 96: Reset State
3.8.5 Reset State In the reset state, the CPU and all on-chip supporting modules are initialized and placed in the stopped state. The CPU enters the reset state whenever the RES pin goes Low, unless the CPU is currently in the hardware standby mode. It remains in the reset state until the RES pin goes High. See section 4.2, “Reset,”...
Page 97: Programming Notes
3.9 Programming Notes 3.9.1 Restriction on Address Location The following restriction applies when instructions are located in on-chip RAM. • Restriction Instruction execution cannot proceed continuously from an external address to on-chip RAM in the ZTAT versions. This restriction does not apply to versions with masked ROM. •...
Page 98: Note On Mulxu Instruction
3.9.2 Note on MULXU Instruction Note that in the case described below, the H8/532 multiply instruction does not give correct results. Problem The result of a squaring operation such as MULXU.B Rn, Rn is indeterminate. This problem occurs when the same register is specified for the source and destination of a byte multiplication operation.
Page 99 A one-byte variable (char or unsigned char) is declared as a register variable. The variable declared as in is squared by compound substitution Example: register char a; a * = a; • Solution The problem can be avoided as follows: In the example above, do not declare the variable (a) as a register variable.
Page 100: Section 4 Exception Handling
Section 4 Exception Handling 4.1 Overview 4.1.1 Types of Exception Handling and Their Priority As indicated in table 4-1 (a) and (b), exception handling can be initiated by a reset, address error, trace, interrupt, or instruction. An instruction initiates exception handling if the instruction is an invalid instruction, a trap instruction, or a DIVXU instruction with zero divisor.
Page 101: Hardware Exception-Handling Sequence
4.1.2 Hardware Exception-Handling Sequence The hardware exception-handling sequence varies depending on the type of exception. When exception handling is initiated by a factor other than a reset, the CPU: 1. Saves the program counter and status register (in minimum mode) or program counter, code page register, and status register (in maximum mode) to the stack.
Page 102: Types Of Factors Causing Exception Handling
• Reset External interrupt • Interrupt Internal Internal interrupt requested by interrupt on-chip module Exception • Address error • Trace Invalid instruction Zero divide • Instruction TRAPA instruction TRAP/VS instruction Figure 4-1 Types of Factors Causing Exception Handling Downloaded from Elcodis.com electronic components distributor...
Page 103: Exception Vector Table
Table 4-2 Exception Vector Table Vector Address Type of Exception Minimum Mode Maximum Mode Reset (initialize PC) H'0000 to H'0001 H'0000 to H'0003 — (Reserved for system) H'0002 to H'0003 H'0004 to H'0007 Invalid instruction H'0004 to H'0005 H'0008 to H'000B DIVXU instruction (zero divide) H'0006 to H'0007 H'000C to H'000F...
Page 104: Reset
4.2 Reset 4.2.1 Overview A reset has the highest exception-handling priority. When the RES pin goes Low, all current processing is halted and the H8/532 chip enters the reset state. A reset initializes the internal status of the CPU and the registers of the on-chip supporting modules and I/O ports.
Page 105: Stack Pointer Initialization
Maximum Mode: Two words are read from addresses H'0000 to H'0003 in the vector table. The byte in address H'0000 is ignored. The byte in address H'0001 is copied to the code page register (CP). The contents of addresses H'0002 and H'0003 are copied to the program counter. Program execution starts from the address indicated by the code page register and program counter.
Page 106: Reset Sequence (Minimum Mode, On-Chip Memory)
Fig. 4-3 Figure 4-3 Reset Sequence (Minimum Mode, On-Chip Memory) Downloaded from Elcodis.com electronic components distributor...
Page 107: Reset Sequence (Maximum Mode, External Memory)
Figure 4-4 Reset Sequence (Maximum Mode, External Memory) Downloaded from Elcodis.com electronic components distributor...
Page 108: Address Error
4.3 Address Error There are three causes of address errors: • Illegal instruction prefetch • Word data access at odd address • Off-chip access in single-chip mode An address error initiates the address error exception-handling sequence. This sequence clears the T bit of the status register to “0”...
Page 109: Trace
Access to Disabled RAM Area: The on-chip RAM area (H'FB80 to H'FF7F) can be disabled by clearing the RAME bit in the RAM control register (RAMCR). If RAM access is attempted in this state in the single-chip mode, an address error occurs. 4.4 Trace When the T bit of the status register is set to “1,”...
Page 110: Interrupt Sources (And Number Of Interrupt Types)
When it accepts an interrupt, the interrupt controller also decides whether to interrupt the CPU or start the on-chip data transfer controller (DTC). This decision is controlled by bits set in four data transfer enable registers (DTE A to D) in the register field. The DTC is started if the corresponding DTE bit is set to “1;”...
Page 111: Invalid Instruction
4.6 Invalid Instruction An invalid instruction exception occurs if an attempt is made to execute an instruction with an undefined operation code or illegal addressing mode specification. The program counter value pushed on the stack is the value of the program counter when the invalid instruction code was detected.
Page 112: Disabling Of Exceptions Immediately After A Reset
currently executing one of the five instructions listed above. After executing this instruction the CPU always proceeds to the next instruction. (And if the next instruction is one of these five, the CPU also proceeds to the next instruction after that.) The exception-handling sequence starts after the next instruction that is not one of these five has been executed.
Page 113: Stack Status After Completion Of Exception Handling
(Example) Program flow ← DTC interrupt request ADD.W R2,R0 ← NMI interrupt request Data transfer cycle MOV.W R0,@H'FF00 After data transfer cycle, CPU executes next instruction before MOV.W #H'FF02,R0 branching to exception handling To NMI exception-handling sequence 4.9 Stack Status after Completion of Exception Handling The status of the stack after an exception-handling sequence is described below.
Page 114 Table 4-3 Stack after Exception Handling Sequence (cont) Exception Factor Minimum Mode Maximum Mode Invalid SR (upper byte) TP:SP SR (upper byte) instruction SR (lower byte) SR (lower byte) PC when error occurred (upper byte) Don’t-care PC when error occurred (lower byte) CP when error occurred (8 bits) PC when error occurred (upper byte) PC when error occurred (lower byte)
Page 115: Pc Value Pushed On Stack For Trace
4.9.1 PC Value Pushed on Stack for Trace, Interrupts, Trap Instructions, and Zero Divide Exceptions The program counter value pushed on the stack for a trace, interrupt, trap, or zero divide exception is the address of the next instruction at the time when the interrupt was accepted. The RTE instruction accordingly returns to the next instruction after the instruction executed before the exception-handling sequence.
Page 116: Section 5 Interrupt Controller
Section 5 Interrupt Controller 5.1 Overview The interrupt controller decides which interrupts to accept, and how to deal with multiple interrupts. It also decides whether an interrupt should be served by the CPU or by the data transfer controller (DTC). This section explains the features of the interrupt controller, describes its internal structure and control registers, and details the handling of interrupts.
Page 117: Block Diagram
5.1.2 Block Diagram Figure 5-1 shows the block configuration of the interrupt controller. Interrupt controller request IRQ0 IRQ1 FRT1 FRT2 Interrupt request FRT3 Interrupt signals request 8 bits timer from modules A/D converter request SR (CPU) FRT: 16 Bits Free Running Timer SCI: Serial Communication Interface Status Register...
Page 118: Register Configuration
5.1.3 Register Configuration The four interrupt priority registers (IPRA to IPRD) and four data transfer enable registers (DTEA to DTED) are 8-bit registers located at addresses H'FFF0 to H'FFF7 in the register field in page 0 of the address space. Table 5-1 lists their attributes. Table 5-1 Interrupt Controller Registers Name Abbreviation...
Page 119 Coding Examples: To select the rising edge of the NMI input: BSET.B #4, @H'FFFC To select the falling edge of the NMI input: BCLR.B #4, @H'FFFC (Interrupt Request 0): An IRQ interrupt can be requested by a Low input to the IRQ and/or a watchdog timer overflow.
Page 120: Internal Interrupts
In the CPU interrupt-handling sequence for IRQ , the T bit of the CPU status register is cleared to “0,” and the interrupt mask level is set to the value in the lower four bits of IPRA. Coding Examples: To enable IRQ to be requested by IRQ input: BSET.B #6, @H'FFFC...
Page 121: Interrupts, Vectors, And Priorities
Table 5-2 Interrupts, Vectors, and Priorities Assignable Priority Priority Vector Table among Levels Priority Entry Address Interrupts (Initial within Minimum Maximum on Same Interrupt Level) Bits Module Mode Mode Level* — — H'16 - H'17 H'2C - H'2F High 7 to 0 IPRA —...
Page 122: Register Descriptions
5.3 Register Descriptions 5.3.1 Interrupt Priority Registers A to D (IPRA to IPRD) , IRQ , and the on-chip supporting modules are each assigned three bits in one of the four interrupt priority registers (IPRA to IPRD). These bits specify a priority level from 7 (high) to 0 (low) for interrupts from the corresponding source.
Page 123: Timing Of Priority Setting
When the interrupt controller receives one or more interrupt requests, it selects the request with the highest priority and compares its priority level with the interrupt mask level set in bits I2 to I0 in the CPU status register. If the priority level is higher than the mask level, the interrupt controller passes the interrupt request to the CPU (or starts the data transfer controller).
Page 124 If the data transfer enable bit is cleared to “0” (or is nonexistent), the sequence proceeds as follows. For the case in which the data transfer controller is started, see section 6, “Data Transfer Controller.” 5. After the CPU has finished executing the current instruction, the program counter and status register (in minimum mode) or program counter, code page register, and status register (in maximum mode) are saved to the stack, leaving the stack in the condition shown in figure 5-3 (a) or (b).
Page 125: Interrupt Handling Flowchart
Program execution state Interrupt requested? Address error? Trace? NMI? Level-7 interrupt? Level-6 interrupt? Level-1 interrupt? Mask level Mask level Mask level ≤ ≤ in SR in SR in SR = 0? Interrupt remains pending Data transfer enabled? Start DTC Read DTC vector Exception-handling Read transfer mode sequence...
Page 126: Stack Status After Interrupt Handling Sequence
5.4.2 Stack Status after Interrupt Handling Sequence Figure 5-3 (a) and (b) show the stack before and after the interrupt exception-handling sequence. Address Address 2m – 4 2m – 4 Upper 8 bits of SR 2m – 3 2m – 3 Lower 8 bits of SR 2m –...
Page 127: Timing Of Interrupt Exception-Handling Sequence
Address Address 2m – 6 2m – 6 Upper 8 bits of SR 2m – 5 2m – 5 Lower 8 bits of SR 2m – 4 2m – 4 Don’t care 2m – 3 2m – 3 2m – 2 2m –...
Page 128: Interrupt Sequence (Minimum Mode, On-Chip Memory)
Figure 5-4 Interrupt Sequence (Minimum Mode, On-Chip Memory) Downloaded from Elcodis.com electronic components distributor...
Page 129: Interrupt Sequence (Maximum Mode, External Memory)
Figure 5-5 Interrupt Sequence (Maximum Mode, External Memory) Downloaded from Elcodis.com electronic components distributor...
Page 130: Interrupt Response Time
5.6 Interrupt Response Time Table 5-4 indicates the number of states that may elapse between the generation of an interrupt request and the execution of the first instruction of the interrupt-handling routine, assuming that the interrupt is not masked and not preempted by a higher-priority interrupt. Since word access is performed to on-chip memory areas, fastest interrupt service can be obtained by placing the program in on-chip ROM and the stack in on-chip RAM.
Page 131: Section 6 Data Transfer Controller
Section 6 Data Transfer Controller 6.1 Overview The H8/532 chip includes a data transfer controller (DTC) that can be started by designated interrupts to transfer data from a source address to a destination address located in page 0. These addresses include in particular the registers of the on-chip supporting modules and I/O ports. Typical uses of the DTC are to change the setting of a control register of an on-chip supporting module in response to an interrupt from that module, or to transfer data from memory to an I/O port or the serial communication interface.
Page 132: Register Configuration
Internal data bus DTC request Register Interrupt controller information table Register information table DTEA DTMR DTEB DTSR DTEC DTDR DTED DTCR DTMR: DT Mode Register DTSR: DT Source Address Register DTDR: DT Destination Address Register DTCR: DT Count Register DTEA to DTED: DT Enable Register A to D Figure 6-1 Block Diagram of Data Transfer Controller 6.1.3 Register Configuration...
Page 133: Data Transfer Enable Registers
Starting of the DTC is controlled by the four data transfer enable registers, which are located in high addresses in page 0. Table 6-2 lists these registers. Table 6-2 Data Transfer Enable Registers Name Abbreviation Read/Write Address Initial Value Data transfer DTEA H'FFF4 H'00...
Page 134: Data Transfer Source Address Register (Dtsr)
Bit 13—DI (Destination Increment): This bit specifies whether to increment to destination address. Bit 13 Description Destination address is not incremented. 1) If Sz = 0: Destination address is incremented by +1 after each data transfer. 2) If Sz = 1: Destination address is incremented by +2 after each data transfer. Bits 12 to 0—Reserved Bits: These bits are reserved.
Page 135: Data Transfer Enable Registers A To D (Dtea To Dted)
The data transfer count register is a 16-bit register that counts the number of bytes or words of data remaining to be transferred. The initial count can be set from 1 to 65,536. A register value of 0 designates an initial count of 65,536. The data transfer count register is decremented automatically after each byte or word is transferred.
Page 136: Data Transfer Operation
• Note on Timing of DTE Modifications: The interrupt controller requires two system clock (ø) periods to determine the priority level of an interrupt. Accordingly, when an instruction modifies a data transfer enable register, the new setting does not take effect until the third state after that instruction has been executed.
Page 137: Flowchart Of Data Transfer Cycle
Interrupt DTC interrupt? Save PC and SR Read DTC vector Read vector Read transfer mode Read address from Read source address vector table Read data Start executing interrupt-handling Source address routine at that increment mode? address. Increment source address (+1 or +2) Write source address Read destination address Write data...
Page 138: Dtc Vector Table
6.3.2 DTC Vector Table The DTC vector table is located immediately following the exception vector table at the beginning of page 0 in memory. For each interrupt that can request DTC service, the DTC vector table provides a pointer to an address in memory where the table of DTC control register information for that interrupt is stored.
Page 139: Dtc Vector Table Entry
DTC vector table DTC vector table Address Address Register Address (H) Don’t care information m + 1 Address (L) Don’t care 2 m + 1* Address (H) 2 m + 2 Address (L) 2 m + 3 (1) Minimum mode (2) Maximum mode * Address 2m and 2m + 1 are not accessed at vector read.
Page 140: Location Of Register Information In Memory
Table 6-4 Addresses of DTC Vectors (cont) Address of DTC Vector Interrupt Minimum Mode Maximum Mode 8-Bit CMIA H'00A0 - H'00A1 H'0140 - H'0143 timer CMIB H'00A2 - H'00A3 H'0144 - H'0147 — — Serial — — communication H'00AA - H'00AB H'0154 - H'0157 interface H'00AC - H'00AD...
Page 141: Number Of States Per Data Transfer
Table 6-5 Number of States per Data Transfer On-Chip RAM ↔Module or I/O External RAM ↔ Module or I/O Increment Mode Source Destina- Register Register (SI) tion (DI) Byte Transfer Word Transfer Byte Transfer Word Transfer Note: Numbers in the table are the number of states. The values in table 6-5 are calculated from the formula: N = 26 + 2 ×...
Page 142: Procedure For Using The Dtc
Table 6-6 Number of States before Interrupt Service Number of States No. Reason for Wait Minimum Mode Maximum Mode Interrupt priority decision and comparison with 2 states mask level in CPU status register Maximum number of Instruction is in on-chip states to completion memory (LDM instruction specifying all registers)
Page 143: Example
6.5 Example Purpose: To receive 128 bytes of serial data via the serial communication interface. Conditions: • Operating mode: Minimum mode • Received data are to be stored in consecutive addresses starting at H'FC00. • DTC control register information for the RXI interrupt is stored at addresses H'FB80 to H'FB87. •...
Page 144: Use Of Dtc To Receive Data Via Serial Communication Interface
6. When 128 bytes have been transferred (DTCR = 0), the DTC generates a CPU interrupt. The interrupt type is RXI. 7. The user-coded RXI interrupt-handling routine processes the received data and disables further data transfer (by clearing the RIE bit, for example). Figure 6-6 shows the DTC vector table and data in RAM for this example.
Page 145: Section 7 Wait-State Controller
Section 7 Wait-State Controller 7.1 Overview To simplify interfacing to low-speed external devices, the H8/532 has an on-chip wait-state controller (WSC) that can insert wait states (T ) to prolong bus cycles. The wait-state function can be used in CPU and DTC access cycles to external addresses. It is not used in access to on-chip supporting modules.
Page 146: Block Diagram
7.1.2 Block Diagram Figure 7-1 shows a block diagram of the wait-state controller. Internal data bus — — — — WMS1 WMS0 Wait counter WAIT request Control logic WAIT input WCR: Wait-state Control Register WMS1, 0: Wait Mode Select 1, 0 WC1, 0: Wait Count 1, 0 Figure 7-1 Block Diagram of Wait-State Controller...
Page 147: Wait-State Control Register
7.2 Wait-State Control Register The wait-state control register (WCR) is an 8-bit register that specifies the wait mode and the number of wait states to be inserted. A reset initializes the WCR to specify the programmable wait mode with three wait states. The WCR is not initialized in the software standby mode. —...
Page 148: Operation In Each Wait Mode
7.3 Operation in Each Wait Mode Table 7-2 summarizes the operation of the three wait modes. Table 7-2 Wait Modes WAIT Insertion Number of Wait Mode Pin Function Conditions States Inserted Programmable Disabled Inserted on access to 1 to 3 wait states are inserted, as wait mode an off-chip address specified by bits WC0 and WC1.
Page 149: Pin Wait Mode
Figure 7-2 shows the timing of the operation in this mode when the wait count is 1 (WC1 = “0,” WC0 = “1”). state or T ø –A Off-chip address RD, AS, DS (Read) Read data Read data D –D WR, DS (Write) Write data...
Page 150: Pin Wait Mode
Figure 7-3 shows the timing of the operation in this mode when the wait count is 1 (WC1 = “0,” WC0 = “1”) and the WAIT pin is held Low to insert one additional wait state. Wait WAIT count ø WAIT pin –A Off-chip address...
Page 151: Pin Auto-Wait Mode
7.3.3 Pin Auto-Wait Mode The pin auto-wait mode is selected when WMS1 = “1” and WMS0 = “1.” In this mode the WAIT function of the P1 /WAIT pin is used automatically. In this mode, the number of wait states indicated by bits WC1 and WC0 are inserted, but only if there is a Low input at the WAIT pin.
Page 152: Section 8 Clock Pulse Generator
Section 8 Clock Pulse Generator 8.1 Overview The H8/532 chip has a built-in clock pulse generator (CPG) consisting of an oscillator circuit, a system (ø) clock divider, an E clock divider, and a group of prescalers. The prescalers generate clock signals for the on-chip supporting modules. 8.1.1 Block Diagram Prescaler Divider...
Page 153: Connection Of Crystal Oscillator (Example)
EXTAL XTAL =10 to 22pF Figure 8-2 Connection of Crystal Oscillator (Example) (2) Crystal Oscillator: The external crystal should have the characteristics listed in table 8-1. XTAL EXTAL AT-cut parallel resonating crystal Figure 8-3 Crystal Oscillator Equivalent Circuit Table 8-1 External Crystal Parameters Frequency (MHz) Rs max (Ω) (pF)
Page 154: Notes On Board Design Around External Crystal
Not allowed Signal A Signal B H8/532 XTAL EXTAL Figure 8-4 Notes on Board Design around External Crystal Input of External Clock Signal (1) Circuit Configuration: An external clock signal can be input at the EXTAL and XTAL pins as shown in the example in figure 8-5. EXTAL External clock input 74HC04...
Page 155: System Clock Divider
(2) External Clock Input Frequency Double the system clock (ø) frequency Duty factor 45% to 55% 8.3 System Clock Divider The system clock divider divides the crystal oscillator or external clock frequency (fosc) by 2 to create the ø clock. An E clock signal is created by dividing the ø...
Page 156: Section 9 I/O Ports
Section 9 I/O Ports 9.1 Overview The H8/532 has nine ports. Ports 1, 3, 4, 5, 7, and 9 are eight-bit input/output ports. Port 2 is a five-bit input/output port. Port 6 is a four-bit input/output port. Port 8 is an eight-bit input-only port.
Page 157: Input/Output Port Summary
Table 9-1 Input/Output Port Summary Expanded Modes Single-Chip Mode Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 (Mode 7) Port 1 8-Bit input/output P1 / TMO These input/output pins double as and / IRQ inputs and as IRQ and IRQ input and / IRQ...
Page 158 Table 9-1 Input/Output Port Summary (cont) Expanded Modes Single-Chip Mode Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 (Mode 7) Port 7 8-Bit input/output P7 / FTOA Input/output for free-running timers 1, port / FTOB / 2 and 3 (FTI to FTI , FTCI to FTCI...
Page 159: Port 1
9.2 Port 1 9.2.1 Overview Port 1 is an 8-bit input/output port with the pin configuration shown in figure 9-1. All pins have dual functions, except that in the single-chip mode pins 4, 3, and 2 do not have the WAIT, BREQ, and BACK functions.
Page 160: And P1
1. Port 1 Data Direction Register (P1DDR)—H'FF80 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 Initial value Read/Write P1DDR is an 8-bit register that selects the direction of each pin in port 1. A pin functions as an output pin if the corresponding bit in P1DDR is set to “1,”...
Page 161 P1CR selects the functions of four of the port 1 pins. It also selects the input edge of the NMI pin. At a reset and in the hardware standby mode, P1CR is initialized to H'87. It is not initialized in the software standby mode.
Page 162: Pin Functions In Each Mode
Bit 3 BRLE Description and P1 function as input/output pins. (Initial value) functions as the input pin. P1 functions as the output pin. Bits 2 to 0—Reserved: These bits cannot be modified and are always read as “1.” 9.2.3 Pin Functions in Each Mode Port 1 operates differently in the expanded modes (modes 1, 2, 3, and 4) and the single-chip mode (mode 7).
Page 163 Table 9-3 Port 1 Pin Functions in Expanded Modes (cont) Functions and How they are Selected / WAIT The function depends on the wait mode select 1 bit (WMS1) of the wait-state control register (WCR) and the P1 DDR bit as follows: WMS1 Pin function input...
Page 164: Port 1 Pin Functions In Single-Chip Modes
Table 9-4 Port 1 Pin Functions in Single-Chip Modes Selection of Pin Functions / TMO The function depends on output select bits 3 to 0 (OS3 to OS0) of the 8-bit timer control/status register (TCSR) and on the P1 DDR bit as follows: OS3 to OS0 All four bits are “0”...
Page 165 Table 9-4 Port 1 Pin Functions in Single-Chip Modes (cont) Selection of Pin Functions Pin function Input Output Pin function Input E clock output / ø Pin function Input ø clock output 9.3 Port 2 9.3.1 Overview Port 2 is a five-bit input/output port with the pin configuration shown in figure 9-2. It functions as an input/output port only in the single-chip mode.
Page 166: Port 2
9.3.2 Port 2 Registers Register Configuration: Table 9-5 lists the registers of port 2. Table 9-5 Port 2 Registers Name Abbreviation Read/Write Initial Value Address Port 2 data direction register P2DDR H'E0 H'FF81 Port 2 data register P2DR H'E0 H'FF83 1.
Page 167: Pin Functions In Each Mode
2. Port 2 Data Register (P2DR)—H'FF83 — — — Initial value Read/Write — — — P2DR is an 8-bit register containing the data for pins P2 to P2 Bits 7 to 5 are reserved. They cannot be modified and are always read as “1.” When the CPU reads P2DR, for output pins it reads the value in the P2DR latch, but for input pins, it obtains the pin status directly.
Page 168: Port 3
Pin Functions in Single-Chip Mode: In the single-chip mode (mode 7), each of the port 2 pins can be designated as an input pin or an output pin, as indicated in figure 9-4, by setting the corresponding bit in P2DDR to “1” for output or clearing it to “0” for input. (input/output) Port (input/output)
Page 169: Port 3 Registers
9.4.2 Port 3 Registers Register Configuration: Table 9-6 lists the registers of port 3. Table 9-6 Port 3 Registers Name Abbreviation Read/Write Initial Value Address Port 3 data direction register P3DDR H'00 H'FF84 Port 3 data register P3DR H'00 H'FF86 1.
Page 170: Pin Functions In Each Mode
2. Port 3 Data Register (P3DR)—H'FF86 Initial value Read/Write P3DR is an 8-bit register containing the data for pins P3 to P3 At a reset and in the hardware standby mode, P3DR is initialized to H'00. When the CPU reads P3DR, for output pins it reads the value in the P3DR latch, but for input pins, it obtains the pin status directly.
Page 171: Port 3 Pin Functions In Single-Chip Mode
Pin Functions in Single-Chip Mode: In the single-chip mode (mode 7), each of the port 3 pins can be designated as an input pin or an output pin, as indicated in figure 9-7, by setting the corresponding bit in P3DDR to “1” for output or clearing it to “0” for input. (input/output) (input/output) (input/output)
Page 172: Port 4
9.5.2 Port 4 Registers Register Configuration: Table 9-7 lists the registers of port 4. Table 9-7 Port 4 Registers Name Abbreviation Read/Write Initial Value Address Port 4 data direction register P4DDR H'00 H'FF85 Port 4 data register P4DR H'00 H'FF87 1.
Page 173: Pin Functions In Each Mode
2. Port 4 Data Register (P4DR)—H'FF87 Initial value Read/Write P4DR is an 8-bit register containing the data for pins P4 to P4 At a reset and in the hardware standby mode, P4DR is initialized to H'00. When the CPU reads P4DR, for output pins it reads the value in the P4DR latch, but for input pins, it obtains the pin status directly.
Page 174: Overview
(input/output) (input/output) (input/output) Port (input/output) (input/output) (input/output) (input/output) (input/output) Figure 9-10 Port 4 Pin Functions in Single-Chip Mode 9.6 Port 5 9.6.1 Overview Port 5 is an 8-bit input/output port with the pin configuration shown in figure 9-11. In the expanded modes that use the on-chip ROM (modes 2 and 4), the pins of port 5 function either as general-purpose input pins or as bits A –...
Page 175: Port 5 Registers
9.6.2 Port 5 Registers Register Configuration: Table 9-8 lists the registers of port 5. Table 9-8 Port 5 Registers Name Abbreviation Read/Write Initial Value Address Port 5 data direction register P5DDR H'00 H'FF88 Port 5 data register P5DR H'00 H'FF8A 1.
Page 176: Pin Functions In Each Mode
Port 5 Data Register (P5DR)—H'FF8A Initial value Read/Write P5DR is an 8-bit register containing the data for pins P5 to P5 At a reset and in the hardware standby mode, P5DR is initialized to H'00. When the CPU reads P5DR, for output pins it reads the value in the P5DR latch, but for input pins, it obtains the pin status directly.
Page 177: Port 5 Pin Functions In Single-Chip Mode
Pin Functions in Modes 2 and 4: In modes 2 and 4, (expanded modes in which the on-chip ROM is used), software can select whether to use port 5 for general-purpose input, or for output of bits A – A of the address bus.
Page 178: Built-In Mos Pull
9.6.4 Built-In MOS Pull-Up The MOS input pull-ups of port 5 are turned on by clearing the corresponding bit in P5DDR to “0” and writing a “1” in P5DR. These pull-ups are turned off at a reset and in the hardware standby mode.
Page 179 A: Before Execution of BSET Instruction Input/output Input Input Output Output Output Output Output Output Pin state High Pull-up B: Execution of BSET Instruction ;set bit 0 in data register BSET.B @PORT5 C: After Execution of BSET Instruction Input/output Input Input Output Output...
Page 180: Overview
A: Before Execution of BSET Instruction ;write data (H'80) for data register MOV.B #80, R0 ;write to work area (RAM0) MOV.B @RAM0 ;write to P5DR MOV.B @PORT5 Input/output Input Input Output Output Output Output Output Output Pin state High Pull-up RAM0 B: Execution of BSET Instruction ;set bit 0 in work area (RAM0)
Page 181: Port 6 Registers
Mode 3 Mode 4 Mode 1 and 2 and Single-Chip Mode (output) (input) / A (output) (input/output) Port (output) (input) / A (output) (input/output) (output) (input) / A (output) (input/output) (output) (input) / A (output) (input/output) Figure 9-15 Pin Functions of Port 6 9.7.2 Port 6 Registers Register Configuration: Table 9-10 lists the registers of port 6.
Page 182 Bits 7 to 4 are reserved. They cannot be modified and are always read as “1.” At a reset and in the hardware standby mode, P6DDR is initialized to H'F0, making all four pins input pins. P6DDR is not initialized in the software standby mode, so in the single-chip mode, or expanded minimum mode, if a P6DDR bit is set to “1”...
Page 183 (output) Port (output) (output) (output) Figure 9-16 Port 6 Pin Functions in Mode 3 Pin Functions in Mode 4: In mode 4, (the expanded maximum mode in which the on-chip ROM is used), software can select whether to use port 6 for general-purpose input, or for output of the page address bits.
Page 184: Port 7
(input/output) Port (input/output) (input/output) (input/output) Figure 9-18 Port 6 Pin Functions in Modes 7, 2, and 1 9.7.4 Built-in MOS Pull-Up Port 6 has programmable MOS input pull-ups which are turned on by clearing the corresponding bit in P6DDR to “0” and writing a “1” in P6DR. These pull-ups are turned off at a reset and in the hardware standby mode.
Page 185: Port 7 Registers
Port 7 has Schmitt inputs. Outputs from port 7 can drive one TTL load and a 30pF capacitive load. They can also drive a Darlington transistor pair. (input/output) / FTOA (output) (input/output) / FTOB (output) / FTCI (input) (input/output) / FTOB (output) / FTCI (input) Port...
Page 186: Pin Functions
A transition to the software standby mode initializes the on-chip supporting modules, so any pins of port 7 that were being used by an on-chip timer when the transition occurs revert to general- purpose input or output, controlled by P7DDR and P7DR. 2.
Page 187: Port 7 Pin Functions
and P7 can be used for timer reset input (TMRI) and timer clock input (TMCI) for the 8-bit timer, as well as for general-purpose input and output. Table 9-13 shows how the functions of the pins of port 7 are selected. Table 9-13 Port 7 Pin Functions Selection of Pin Functions The function depends on the output enable A bit (OEA) of the FRT1 timer control...
Page 188 Table 9-13 Port 7 Pin Functions (cont) Selection of Pin Functions / FTI The function depends on the counter clear bits 1 and 0 (CCLR1 and CCLR0) in the TMRI timer control register (TCR) of the 8-bit timer, and on the P7 DDR bit as follows: CCLR1, CCLR0: At least one bit is “0.”...
Page 189: Port 8
9.9 Port 8 9.9.1 Overview Port 8 is an 8-bit input port that also receives inputs for the on-chip A/D converter. The pin functions are the same in all MCU operating modes, as shown in figure 9-20. (input) / AN (input) (input) / AN (input)
Page 190: Port 9
9.10 Port 9 9.10.1 Overview Port 9 is an 8-bit input/output port with the pin configuration shown in figure 9-21. In addition to general-purpose input and output, its pins are used for the output compare A signals from free- running timers 2 and 3, for PWM timer output, and for input and output by the on-chip serial communication interface 9 (SCI).
Page 191 1. Port 9 Data Direction Register (P9DDR)—H'FFFE DDR P9 DDR P9 DDR P9 DDR P9 DDR P9 DDR P9 DDR P9 Initial value Read/Write P9DDR is an 8-bit register that selects the direction of each pin in port 9. A pin functions as an output pin if the corresponding bit in P9DDR is set to “1,”...
Page 192: Port 9 Pin Functions
Table 9-16 shows how the functions of the pins of port 9 are selected. Table 9-16 Port 9 Pin Functions Selection of Pin Functions The function depends on the communication mode bit (C/A) and the clock enable 1 and 2 bits (CKE1 and CKE0) of the serial control register (SCR) of the serial communication interface as follows: CKE1 CKE0...
Page 193: Pin Functions
Table 9-16 Port 9 Pin Functions (cont) Selection of Pin Functions / PW The function depends on the output enable bit (OE) of the timer control register of PWM timer channel 3 and on the P9 DDR bit as follows: Pin function input output...
Page 194: Section 10 16-Bit Free-Running Timers
Section 10 16-Bit Free-Running Timers 10.1 Overview The H8/532 has an on-chip 16-bit free-running timer (FRT) module with three independent channels (FRT1, FRT2, and FRT3). All three channels are functionally identical. Each channel has a 16-bit free-running counter that it uses as a time base. Applications of the FRT module include rectangular-wave output (up to two independent waveforms per channel), input pulse width measurement, and measurement of external clock periods.
Page 195: Block Diagram
10.1.2. Block Diagram Figure 10-1 shows a block diagram of one free-running timer channel. External clock Internal clock ø/4 ø/8 FTCI ø/32 Clock Clock select OCRA Compare-match A Comparator A FTOA Internal Overflow data bus FTOB Clear Compare-match B Comparator B Module Control data...
Page 196: Input And Output Pins
10.1.3 Input and Output Pins Table 10-1 lists the input and output pins of the free-running timer module. Table 10-1 Input and Output Pins of Free-Running Timer Module Channel Name Abbreviation I/O Function Output compare A FTOA Output Output controlled by comparator A of FRT1 Output compare B or FTOB Output / Output controlled by comparator B of FRT1, counter clock input...
Page 197: Register Configuration
10.1.4 Register Configuration Table 10-2 lists the registers of each free-running timer channel. Table 10-2 Register Configuration Initial Channel Name Abbreviation Value Address Timer control register H'00 H'FF90 Timer control/status register TCSR R/(W)* H'00 H'FF91 Free-running counter (High) FRC (H) H'00 H'FF92 Free-running counter (Low)
Page 198: Register Descriptions
Table 10-2 Register Configuration (cont) Initial Channel Name Abbreviation Value Address Timer control register H'00 H'FFB0 Timer control/status register TCSR R/(W)* H'00 H'FFB1 Free-running counter (High) FRC (H) H'00 H'FFB2 Free-running counter (Low) FRC (L) H'00 H'FFB3 Output compare register A (High) OCRA (H) H'FF H'FFB4...
Page 199: Input Capture Register (Icr)-H'ff98, H'ffa8, H'ffb8
10.2.2 Output Compare Registers A and B (OCRA and OCRB)—H'FF94 and H'FF96, H'FFA4 and H'FFA6, H'FFB4 and H'FFB6 Initial value 1 Read/WriteR/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCRA and OCRB are 16-bit readable/writable registers, the contents of which are continually compared with the value in the FRC.
Page 200: Timer Control Register (Tcr)
To ensure input capture, the pulse width of the input capture signal should be at least 1.5 system clock periods (1.5·ø). ø Minimum FTI Pulse Width The ICR is initialized to H'0000 at a reset and in the standby modes. Note: When input capture is detected, the FRC value is transferred to the ICR even if the input capture flag (ICF) is already set.
Page 201 Bit 6 OCIEB Description Output compare interrupt request B (OCIB) is disabled. (Initial value) Output compare interrupt request B (OCIB) is enabled. Bit 5—Output Compare Interrupt Enable A (OCIEA): This bit selects whether to request output compare interrupt A (OCIA) when output compare flag A (OCFA) in the timer status/control register (TCSR) is set to “1.”...
Page 202: Timer Control/Status Register (Tcsr)
Bit 2 Description Output compare A output is disabled. (Initial value) Output compare A output is enabled. Bits 1 and 0—Clock Select (CKS1 and CKS0): These bits select external clock input or one of three internal clock sources for the FRC. External clock pulses are counted on the rising edge. Bit 1 Bit 0 CKS1...
Page 203 Bit 7 Description This bit is cleared from 1 to 0 when: (Initial value) 1. The CPU reads the ICF bit, then writes a “0” in this bit. 2. The data transfer controller (DTC) serves an input capture interrupt. This bit is set to 1 when an input capture signal causes the FRC value to be copied to the ICR. Bit 6—Output Compare Flag B (OCFB): This status flag is set to “1”...
Page 204 Bit 3 OLVLB Description A “0” logic level (Low) is output for compare-match B. (Initial value) A “1” logic level (High) is output for compare-match B. Bit 2—Output Level A (OLVLA): This bit selects the logic level to be output at the FTOA pin when the FRC and OCRA values match.
Page 205: Cpu Interface
10.3 CPU Interface The FRC, OCRA, OCRB, and ICR are 16-bit registers, but they are connected to an 8-bit data bus. When the CPU accesses these four registers, to ensure that both bytes are written or read simultaneously, the access is performed using an 8-bit temporary register (TEMP). These registers are written and read as follows.
Page 206 < Upper byte write > Module data bus CPU wites Bus interface data H’AA TEMP [H’AA] FRCH FRCL < Lower byte write > Module data bus CPU wites Bus interface data H’55 TEMP [H’AA] FRCH FRCL [H’AA] [H’55] Figure 10-2 (a) Write Access to FRC (When CPU Writes H'AA55) Downloaded from Elcodis.com electronic components distributor...
Page 207: Operation
< Upper byte read > Module data bus CPU wites Bus interface data H’AA TEMP [H’55] FRCH FRCL [H’AA] [H’55] < Lower byte read > Module data bus CPU wites Bus interface data H’55 TEMP [H’55] FRCH FRCL Figure 10-2 (b) Read Access to FRC (When FRC Contains H'AA55) 10.4 Operation 10.4.1 FRC Incrementation Timing The FRC increments on a pulse generated once for each period of the selected (internal or...
Page 208: Output Compare Timing
The pulse width of the external clock signal must be at least 1.5·ø clock periods. The counter will not increment correctly if the pulse width is shorter than 1.5·ø clock periods. ø FTCI Minimum FTCI Pulse Width ø External clock source FRC clock pulse N + 1...
Page 209: Setting Of Output Compare Flags
ø Ø N + 1 Internal compare- match signal Figure 10-4 Setting of Output Compare Flags Output Timing: When a compare-match occurs, the logic level selected by the output level bit (OLVLA or OLVLB) in the TCSR is output at the output compare pin (FTOA or FTOB). Figure 10-5 shows the timing of this operation for compare-match A.
Page 210: Input Capture Timing
FRC Clear Timing: If the CCLRA bit is set to “1,” the FRC is cleared when compare-match A occurs. Figure 10-6 shows the timing of this operation. ø Internal compare- match A signal H’0000 Figure 10-6 Clearing of FRC by Compare-Match A 10.4.3 Input Capture Timing 1.
Page 211: Input Capture Timing (1-State Delay)
Read cycle: CPU reads upper byte of ICR ø Input at FTI pin Internal input capture signal Figure 10-8 Input Capture Timing (1-State Delay) Timing of Input Capture Flag (ICF) Setting: The input capture flag (ICF) is set to “1” by the internal input capture signal.
Page 212: Setting Of Frc Overflow Flag (Ovf)
10.4.4 Setting of FRC Overflow Flag (OVF) The FRC overflow flag (OVF) is set to “1” when the FRC overflows (changes from H'FFFF to H'0000). Figure 10-10 shows the timing of this operation. ø H’FFFF H’0000 Internal overflow signal Figure 10-10 Setting of Overflow Flag (OVF) 10.5 CPU Interrupts and DTC Interrupts Each free-running timer channel can request four types of interrupts: input capture (ICI), output compare A and B (OCIA and OCIB), and overflow (FOVI).
Page 213: Synchronization Of Free-Running Timers 1
10.6 Synchronization of Free-Running Timers 1 to 3 10.6.1 Synchronization after a Reset The three free-running timer channels are synchronized at a reset and remained synchronized until: • the clock source is changed; • FRC contents are rewritten; or • an FRC is cleared. After a reset, each free-running counter operates on the ø/4 internal clock source.
Page 214 Example a: ø/4 clock source, 12-state write interval (n = 3), on-chip memory ; Initialize base register for short-format instruction (MOV:S) LDC.B #H'FF,BR ; Raise interrupt mask level to 7 LDC.W #H'0700,SR ; Data for free-running timer 1 MOV.W #m,R1 ;...
Page 215 Example c: ø/32 clock source, 32-state write interval (n = 1), on-chip memory LDC.B #H'FF,BR LDC.W #H'0700,SR MOV.W #m,R1 MOV.W #m+1,R2 MOV.W #m+2,R3 SET32 ; Align on even address .ALIGN 2 ; 2 Bytes, 9 states SET32: MOV:S.W R1,@H'92:8 ; 2 Bytes, 9 states BSR WAIT:8 MOV:S.W R2,@H'A2:8 Total 32 states...
Page 216 Example e: ø/8 clock source, 24-state write interval (n = 3), external memory LDC.B #H'FF,BR LDC.W #H'0700,SR CLR.B @H'F8"8 MOV.W #m,R1 MOV.W #m+3,R2 MOV.W #m+6,R3 ; 13 States MOV:S.W R1,@H'92:8 ; 2 Bytes, 7 states Total 24 states LE:8 ; 1 Byte, 4 states MOV:S.W R2,@H'A2:8 LE:8...
Page 217: Sample Application
Synchronization on External Clock Source: When the external clock source is selected, the free-running timers can be synchronized by halting their external clock inputs, then writing identical values in their free-running counters. 10.7 Sample Application In the example below, one free-running timer channel is used to generate two square-wave outputs with a 50% duty factor and arbitrary phase relationship.
Page 218 Figure 10-12 shows this type of contention. Write cycle: CPU write to lower byte of FRC ø Internal address bus FRC address Internal write signal FRC clear signal H’0000 Figure 10-12 FRC Write-Clear Contention Contention between FRC Write and Increment: If an FRC increment pulse is generated during the T state of a write cycle to the lower byte of a free-running counter, the write takes priority and the FRC is not incremented.
Page 219 Figure 10-13 shows this type of contention. Write cycle: CPU write to lower byte of FRC ø Internal address bus FRC address Internal write signal FRC clock pulse Write data Figure 10-13 FRC Write-Increment Contention Downloaded from Elcodis.com electronic components distributor...
Page 220: Contention Between Ocr Write And Compare-Match
Contention between OCR Write and Compare-Match: If a compare-match occurs during the T3 state of a write cycle to the lower byte of OCRA or OCRB, the write takes precedence and the compare-match signal is inhibited. Figure 10-14 shows this type of contention. Write cycle: CPU write to lower byte of OCRA or OCRB ø...
Page 221: Effect Of Changing Internal Clock Sources
Table 10-5 Effect of Changing Internal Clock Sources Description Timing Chart Low → Low: Old clock source CKS1 and CKS0 are rewritten while both clock sources are Low. New clock source FRC clock pulse N + 1 CKS rewrite Low → High: CKS1 and CKS0 are Old clock rewritten while old...
Page 222: Effect Of Changing Internal Clock Sources
Table 10-5 Effect of Changing Internal Clock Sources (cont) Description Timing Chart High → High: Old clock CKS1 and CKS0 are source rewritten while both clock sources are High. New clock source FRC clock pulse N + 1 N + 2 CKS rewrite Downloaded from Elcodis.com...
Page 223: Section 11 8-Bit Timer
Section 11 8-Bit Timer 11.1 Overview The H8/532 chip includes a single 8-bit timer based on an 8-bit counter (TCNT). The timer has two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to detect compare-match events. One application of the 8-bit timer is to generate a rectangular-wave output with an arbitrary duty factor.
Page 224: Block Diagram
11.1.2 Block Diagram Figure 11-1 shows a block diagram of 8-bit timer. External clocks Internal clocks ø/8 ø/64 TMCI ø/1024 Clock Clock select TCORA Compare-match A Comparator A Internal Overflow data bus TMRI TCNT Clear Comparator B Control Compare-match B logic Module data...
Page 225: Input And Output Pins
11.1.3 Input and Output Pins Table 11-1 lists the input and output pins of the 8-bit timer. Table 11-1 Input and Output Pins of 8-Bit Timer Name Abbreviation Function Timer output Output Output controlled by compare-match Timer clock input TMCI Input External clock source for the counter Timer reset input...
Page 226: Time Constant Registers A And B
The timer counter can be cleared by an external reset input or by an internal compare-match signal generated at a compare-match event. Clock clear bits 1 and 0 (CCLR1 and CCLR0) of the timer control register select the method of clearing. When the timer counter overflows from H'FF to H'00, the overflow flag (OVF) in the timer control/status register (TCSR) is set to “1.”...
Page 227 Bit 7—Compare-match Interrupt Enable B (CMIEB): This bit selects whether to request compare-match interrupt B (CMIB) when compare-match flag B (CMFB) in the timer status/control register (TCSR) is set to “1.” Bit 7 CMIEB Description Compare-match interrupt request B (CMIB) is disabled. (Initial value) Compare-match interrupt request B (CMIB) is enabled.
Page 228: Timer Control/Status Register (Tcsr)
Bits 2, 1, and 0—Clock Select (CKS2, CKS1, and CKS0): These bits select the internal or external clock source for the timer counter. For the external clock source they select whether to increment the count on the rising or falling edge of the clock input, or on both edges. Bit 2 Bit 1 Bit 0...
Page 229 Bit 7 CMFB Description This bit is cleared from 1 to 0 when: (Initial value) 1. The CPU reads the CMFB bit, then writes a “0” in this bit. 2. Compare-match interrupt B is served by the data transfer controller (DTC). This bit is set to 1 when TCNT = TCORB.
Page 230: Operation
Bit 1 Bit 0 Description No change when compare-match A occurs. (Initial value) Output changes to “0” when compare-match A occurs. Output changes to “1” when compare-match A occurs. Output inverts (toggles) when compare-match A occurs. 11.3 Operation 11.3.1 TCNT Incrementation Timing The timer counter increments on a pulse generated once for each period of the selected (internal or external) clock source.
Page 231: Compare Match Timing
ø Ø External clock External clock source source TCNT clock TCNT clock pulse pulse TCNT TCNT N – 1 N + 1 Figure 11-2 Count Timing for External Clock Input 11.3.2 Compare Match Timing Setting of Compare-Match Flags A and B (CMFA and CMFB): The compare-match flags are set to “1”...
Page 232: Setting Of Compare-Match Flags
ø Ø TCNT N + 1 TCOR Internal compare-match signal Figure 11-3 Setting of Compare-Match Flags Output Timing: When a compare-match event occurs, the timer output (TMO) changes as specified by the output select bits (OS3 to OS0) in the TCSR. Depending on these bits, the output can remain the same, change to “0,”...
Page 233: External Reset Of Tcnt
Timing of Compare-Match Clear Depending on the CCLR1 and CCLR0 bits in the TCR, the timer counter can be cleared when compare-match A or B occurs. Figure 11-5 shows the timing of this operation. ø Internal compare-match signal H’00 TCNT Figure 11-5 Timing of Compare-Match Clear 11.3.3 External Reset of TCNT When the CCLR1 and CCLR0 bits in the TCR are both set to “1,”...
Page 234: Setting Of Tcnt Overflow Flag
11.3.4 Setting of TCNT Overflow Flag The overflow flag (OVF) is set to “1” when the timer count overflows (changes from H'FF to H'00). Figure 11-7 shows the timing of this operation. Ø ø TCNT H’FF H’00 Internal overflow signal Figure 11-7 Setting of Overflow Flag (OVF) 11.4 CPU Interrupts and DTC Interrupts The 8-bit timer can generate three types of interrupts: compare-match A and B (CMIA and...
Page 235: Sample Application
11.5 Sample Application In the example below, the 8-bit timer is used to generate a pulse output with a selected duty factor. The control bits are set as follows: 1. In the TCR, CCLR1 is cleared to “0” and CCLR0 is set to “1” so that the timer counter is cleared when its value matches the constant in TCORA.
Page 236: Application Notes
11.6 Application Notes Application programmers should note that the following types of contention can occur in the 8-bit timer. Contention between TCNT Write and Clear: If an internal counter clear signal is generated during the T state of a write cycle to the timer counter, the clear signal takes priority and the write is not performed.
Page 237: Tcnt Write-Increment Contention
Contention between TCNT Write and Increment: If a timer counter increment pulse is generated during the T state of a write cycle to the timer counter, the write takes priority and the timer counter is not incremented. Figure 11-10 shows this type of contention. Write cycle: CPU writes to TCNT ø...
Page 238: Contention Between Tcor Write And Compare-Match
Contention between TCOR Write and Compare-Match: If a compare-match occurs during the state of a write cycle to TCORA or TCORB, the write takes precedence and the compare- match signal is inhibited. Figure 11-11 shows this type of contention. Write cycle: CPU writes to TCORA or TCORB ø...
Page 239: Priority Order Of Timer Output
Table 11-4 Priority Order of Timer Output Output Selection Priority Toggle High “1” Output “0” Output No change Incrementation Caused by Changing of Internal Clock Source: When an internal clock source is changed, the changeover may cause the timer counter to increment. This depends on the time at which the clock select bits (CKS2 to CKS0) are rewritten, as shown in table 11-5.
Page 240 Table 11-5 Effect of Changing Internal Clock Sources (cont) Description Timing Chart Low → High Old clock CKS1 and CKS0 are source rewritten while old clock source is Low and New clock new clock source is High. source TCNT clock pulse TCNT N + 1...
Page 241 Table 11-5 Effect of Changing Internal Clock Sources (cont) Description Timing Chart High → High: CKS1 and CKS0 are Old clock source rewritten while both clock sources are High. New clock source TCNT clock pulse TCNT N + 1 N + 2 CKS rewrite Downloaded from Elcodis.com...
Page 242: Section 12 Pwm Timer
Section 12 PWM Timer 12.1 Overview The H8/532 has an on-chip pulse-width modulation (PWM) timer module with three independent channels (PWM1, PWM2, and PWM3). All three channels are functionally identical. Using an 8-bit timer counter, each PWM channel generates a rectangular output pulse with a duty factor of 0 to 100%.
Page 243: Input And Output Pins
Compare- Output match Internal Comparator control data bus TCNT Module data bus Internal clock source ø/2 ø/8 ø/32 ø/128 Clock Clock select ø/256 ø/1024 DTR: Duty Register ø/2048 TCNT: Timer Counter ø/4096 TCR: Timer Control Register Figure 12-1 Block Diagram of PWM Timer 12.1.3 Input and Output Pins Table 12-1 lists the output pins of the PWM timer module.
Page 244: Register Configuration
12.1.4 Register Configuration The PWM timer module has three registers for each channel as listed in table12-2. Table 12-2 PWM Timer Registers Initial Channel Name Abbreviation Value Address Timer control register H'38 H'FFC0 Duty register H'FF H'FFC1 Timer counter TCNT R/(W)* H'00 H'FFC2...
Page 245: Duty Register (Dtr)-H'ffc1, H'ffc5, H'ffc9
The PWM timer counters are initialized to H'00 at a reset and in the standby modes, and when the OE bit is cleared to 0. 12.2.2 Duty Register (DTR)—H'FFC1, H'FFC5, H'FFC9 Initial value Read/Write The duty registers (DTR) specify the duty factor of the output pulse. Any duty factor from 0 to 100% can be selected, with a resolution of 1/250.
Page 246 Bit 7—Output Enable (OE): This bit enables the timer counter and the PWM output. Bit 7 Description PWM output is disabled. TCNT is cleared to H'00 and stopped. (Initial value) PWM output is enabled. TCNT runs. Bit 6—Output Select (OS): This bit selects positive or negative logic for the PWM output. Bit 6 Description Positive logic;...
Page 247: Operation
Table 12-3 PWM Timer Parameters for 10MHz System Clock Internal Clock Frequency Resolution PWM Period PWM Frequency ø/2 200ns 50µs 20kHz ø/8 800ns 200µs 5kHz ø/32 3.2µs 800µs 1.25kHz ø/128 12.8µs 3.2ms 312.5Hz ø/256 25.6µs 6.4ms 156.3Hz ø/1024 102.4µs 25.6ms 39.1Hz ø/2048 204.8µs...
Page 248: Pwm Timing
Figure 12-2 PWM Timing Downloaded from Elcodis.com electronic components distributor...
Page 249: Application Notes
12.4 Application Notes Two notes on the use of the PWM timer module are given below. 1. Any necessary changes to the clock select bits (CKS2 to CKS0) and output select bit (OS) should be made before the output enable bit (OE) is set to 1. 2.
Page 250: Section 13 Watchdog Timer
Section 13 Watchdog Timer 13.1 Overview The H8/532 has an on-chip watchdog timer (WDT) module. This module can monitor system operation by requesting a nonmaskable interrupt if a system crash allows the timer count to overflow. When this watchdog function is not needed, the WDT module can be used as an interval timer. In the interval timer mode, an IRQ interrupt is requested at each counter overflow.
Page 251: Block Diagram
13.1.2 Block Diagram Figure 13-1 is a block diagram of the watchdog timer. (Watchdog timer mode) Overflow TCNT Internal data bus Interrupt Read/ signals Interrupt write control control (Interval timer mode) TCSR Internal clock source ø/2 Ø/2 ø/32 Ø/32 Ø/64 ø/64 Ø/128 ø/128...
Page 252: Register Descriptions
13.2 Register Descriptions 13.2.1 Timer Counter TCNT—H'FFED Initial value Read/Write The watchdog timer counter (TCNT) is a readable/writable* 8-bit up-counter. When the timer enable bit (TME) in the timer control/status register (TCSR) is set to 1, the timer counter starts counting pulses of an internal clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) in the TCSR.
Page 253 Bit 7—Overflow Flag (OVF): This bit indicates that the watchdog timer count has overflowed. Bit 7 Description This bit is cleared to from 1 to 0 when the CPU reads (Initial value) the OVF bit, then writes a 0 in this bit. This bit is set to 1 when TCNT changes from H'FF to H'00.
Page 254: Notes On Register Access
Bit 2 Bit 1 Bit 0 Description CKS2 CKS1 CKS0 Clock Source Overflow Interval (ø = 10MHz) ø/2 51.2µs (Initial value) ø/32 819.2µs ø/64 1.6ms ø/128 3.3ms ø/256 6.6ms ø/512 13.1ms ø/2048 52.4ms ø/4096 104.9ms 13.2.3 Notes on Register Access The watchdog timer’s TCNT and TCSR registers differ from other registers in being more difficult to write.
Page 255: Operation
Coding Examples: To clear TCNT to 00: MOV.W #H'5A00, @H'FFEC To write H'4F in TCSR: MOV.W #H'A54F, @H'FFEC 2. Reading TCNT and TCSR: The read addresses are H'FFEC for TCSR and H'FFED for TCNT, as indicated in table 13-2. These two registers are read like other registers. Byte access instructions can be used. Table 13-2 Read Addresses of TCNT and TCSR Read Address Register...
Page 256: Interval Timer Mode
H’FF TCNT count Time t H’00 WT/IT = 1 H'00 written OVF = 1 TIME = 1 to TCNT NMI requested Figure 13-3 Operation in Watchdog Timer Mode 13.3.2 Interval Timer Mode Interval timer operation begins when the WT/IT bit is cleared to 0 and the TME bit is set to 1. In the interval timer mode, an IRQ request is generated each time the timer count overflows.
Page 257: Operation In Software Standby Mode
H’FF TCNT count Time t H’00 WT/IT = 0 TME = 1 request request request request request Figure 13-4 Operation in Interval Timer Mode 13.3.3 Operation in Software Standby Mode The watchdog timer has a special function in the software standby mode. Specific watchdog timer settings are required when the software standby mode is used.
Page 258: Setting Of Overflow Flag
13.3.4 Setting of Overflow Flag The OVF bit is set to 1 when the timer count overflows. Simultaneously, the WDT module requests an NMI or IRQ interrupt. The timing is shown in figure 13-5. ø TCNT H'FF H'00 Internal overflow signal Figure 13-5 Setting of OVF Bit 13.4 Application Notes...
Page 259: Tcnt Write-Increment Contention
Write cycle: CPU writes to TCNT ø Internal address bus TCNT address Internal write signal TCNT clock pulse TCNT Counter write data Figure 13-6 TCNT Write-Increment Contention 2. Changing the Clock Select Bits (CKS2 to CKS0): Software should stop the watchdog timer (by clearing the TME bit to 0) before changing the value of the clock select bits.
Page 260: Section 14 Serial Communication Interface
Section 14 Serial Communication Interface 14.1 Overview The H8/532 chip includes a single-channel serial communication interface (SCI) for transferring serial data to and from other chips. The SCI supports both synchronous and asynchronous data transfer. Communication control functions are provided by eight internal registers. 14.1.1 Features The features of the on-chip serial communication interface are: •...
Page 261: Block Diagram
14.1.2 Block Diagram Figure 14-1 shows a block diagram of serial communication interface. Internal Module data bus data bus Internal clock source ø Baud-rate ø/4 generator ø/16 Communication control ø/64 Parity generator Parity check Clock External clock RDR: Receive Data Register RSR: Receive Shift Register TDR:...
Page 262: Input And Output Pins
14.1.3 Input and Output Pins Table 14-1 lists the input and output pins used by the SCI module. Table 14-1 SCI Input/Output Pins Name Abbreviation Function Serial clock Input/output Serial clock input and output. Receive data Input Receive data input. Transmit data Output Transmit data output.
Page 263: Receive Data Register (Rdr)-H'ffdd
14.2.2 Receive Data Register (RDR)—H'FFDD Initial value Read/Write The RDR stores received data. As each character is received, it is transferred from the RSR to the RDR, enabling the RSR to receive the next character. This double-buffering allows the SCI to receive data continuously.
Page 264: Serial Mode Register (Smr)-H'ffd8
14.2.5 Serial Mode Register (SMR)—H'FFD8 STOP — CKS1 CKS0 Initial value Read/Write — The SMR is an 8-bit readable/writable register that controls the communication format and selects the clock rate for the internal clock source. It is initialized to H'04 at a reset and in the standby modes.
Page 265 Bit 4—Parity Mode (O/E): In asynchronous mode, when parity is enabled (PE = 1), this bit selects even or odd parity. Even parity means that a parity bit is added to the data bits for each character to make the total number of 1’s even.
Page 266: Serial Control Register (Scr)-H'ffda
14.2.6 Serial Control Register (SCR)—H'FFDA — — CKE1 CKE0 Initial value Read/Write — — The SCR is an 8-bit readable/writable register that enables or disables various SCI functions. It is initialized to H'0C at a reset and in the standby modes. Bit 7—Transmit Interrupt Enable (TIE): This bit enables or disables the transmit-end interrupt (TXI) requested when the transmit data register empty (TDRE) bit in the serial status register (SSR) is set to 1.
Page 267 Bit 4—Receive Enable (RE): This bit enables or disables the receive function. When the receive function is enabled, the RXD pin is automatically used for input. When the receive function is disabled, the RXD pin is available as a general-purpose I/O port. Bit 4 Description The receive function is disabled.
Page 268: Serial Status Register (Ssr)-H'ffdc
14.2.7 Serial Status Register (SSR)—H'FFDC TDRE RDRF ORER — — — Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* — — — * Software can write a 0 to clear the flags, but cannot write a 1 in these bits. The SSR is an 8-bit register that indicates transmit and receive status.
Page 269 Bit 5—Overrun Error (ORER): This bit indicates an overrun error during reception. Bit 5 ORER Description This bit is cleared from 1 to 0 when: (Initial value) 1. The CPU reads the ORER bit, then writes a 0 in this bit. 2.
Page 270: Bit Rate Register (Brr)-H'ffd9
14.2.8 Bit Rate Register (BRR)—H'FFD9 Initial value Read/Write The BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in the SMR, determines the bit rate output by the baud rate generator. The BRR is initialized to H'FF (the slowest rate) at a reset and in the standby modes. Tables 14-3 and 14-4 show examples of BRR (N) and CKS (n) settings for commonly used bit rates.
Page 271 Table 14-3 Examples of BRR Settings in Asynchronous Mode (2) XTAL Frequency (MHz) 4.9152 7.3728 Error Error Error Error Rate –0.26 +0.50 +0.70 +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 1200 +0.16 +0.16 2400 +0.16 +0.16 4800 –2.34 +0.16 9600 —...
Page 272 Table 14-3 Examples of BRR Settings in Asynchronous Mode (4) XTAL Frequency (MHz) 14.7456 19.6608 Error Error Error Error Rate –0.07 +0.03 –0.26 +0.88 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 1200 +0.16 +0.16 2400 +0.16 +0.16 4800 +0.16 +0.16 9600 +0.16 –1.36 19200...
Page 273: Examples Of Brr Settings In Synchronous Mode
Table 14-4 Examples of BRR Settings in Synchronous Mode XTAL Frequency (MHz) Rate — — — — — — — — — — — — — — — — — — — — — — — — 2.5M 100K — —...
Page 274: Operation
14.3 Operation 14.3.1 Overview The SCI supports serial data transfer in both asynchronous and synchronous modes. The communication format depends on settings in the SMR as indicated in table 14-5. The clock source and usage of the SCK pin depend on settings in the SMR and SCR as indicated in table 14-6. Table 14-5 Communication Formats Used by SCI Stop Bit STOP...
Page 275: Asynchronous Mode
14.3.2 Asynchronous Mode In asynchronous mode, each character is individually synchronized by framing it with a start bit and stop bit. Full duplex data transfer is possible because the SCI has independent transmit and receive sections. Double buffering in both sections enables the SCI to be programmed for continuous data transfer.
Page 276: Phase Relationship Between Clock Output And Transmit Data
Table 14-7 Data Formats in Asynchronous Mode SMR Bits STOP Data Format START 8-Bit data STOP START 8-Bit data STOP STOP START 8-Bit data STOP START 8-Bit data STOP STOP START 7-Bit data STOP START 7-Bit data STOP STOP START 7-Bit data STOP START...
Page 277 3. Data Transmission and Reception • SCI Initialization: Before data can be transmitted or received, the SCI must be initialized by software. To initialize the SCI, software must clear the TE and RE bits to 0, then execute the following procedure. (1) Set the desired communication format in the SMR.
Page 278 (4) The first byte of transmit data is transferred from the TDR to the TSR and sent in the designated format as follows. Start bit (one 0 bit) ii) Transmit data (seven or eight bits, starting from bit 0) iii) Parity bit (odd or even parity bit, or no parity bit) iv) Stop bit (one or two consecutive 1 bits) (5) Transfer of the transmit data from the TDR to the TSR makes the TDR empty, so the TDRE bit is set to 1.
Page 279: Synchronous Mode
When a framing or parity error occurs, the RSR contents are transferred to the RDR. If an overrun error occurs, however, the RSR contents are not transferred to the RDR. If multiple receive errors occur simultaneously, all the corresponding error flags are set to 1. To clear a receive-error flag (ORER, FER, or PER), software must read the SSR, then write a 0 in the flag bit.
Page 280: Data Format In Synchronous Mode
Transmission direction Serial clock Data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don’t-care Don’t-care Figure 14-4 Data Format in Synchronous Mode 2. Clock: Either the internal serial clock created by the on-chip baud rate generator or an external clock input at the SCK pin can be selected in the synchronous mode.
Page 281 When clearing the TDRE bit during data transmission, to assure correct data transfer, do not clear the TDRE bit until after writing data in the TDR. Similarly, in receiving data, do not clear the RDRF bit until after reading data from the RDR. •...
Page 282 (2) Set the RE bit in the SCR to 1. The RXD pin will automatically be switched to input and the SCI is ready to receive data. (3) Incoming data bits are latched in the RSR on eight clock pulses. When 8 bits of data have been received, the SCI sets the RDRF bit in the SSR to 1.
Page 283: Cpu Interrupts And Dtc Interrupts
(5) First, the transmit data are transferred from the TDR to the TSR. This makes the TDR empty, so the TDRE bit is set to 1. If the TIE bit is set to 1, a transmit-end interrupt (TXI) is requested. If continuous data transmission is desired, the CPU must read the TDRE bit in the SSR, write the next transmit data in the TDR, then clear the TDRE bit to 0.
Page 284: Application Notes
Table 14-9 SCI Interrupts DTC Service Interrupt Description Available? Priority Receive-error interrupt, requested when High ORER, FER, or PER is set. Receive-end interrupt, requested when RDRF is set. Transmit-end interrupt, requested when TDRE is set. The TXI and RXI interrupts can be served by the data transfer controller (DTC) to have a data transfer performed.
Page 285: Ssr Bit States And Data Transfer When Multiple Receive Errors Occur
Table 14-10 SSR Bit States and Data Transfer When Multiple Receive Errors Occur SSR Bits Receive Error RDRF ORER RSR to RDR Overrun error Framing error Parity error Overrun + framing errors Overrun + parity errors Framing + parity errors Overrun + framing + parity errors *1 Set to 1 before the overrun error occurs.
Page 286: Sampling Timing (Asynchronous Mode)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 Basic clock –7.5 pulses +7.5 pulses Receive data...
Page 287: Section 15 A/D Converter
Section 15 A/D Converter 15.1 Overview The H8/532 chip includes an analog-to-digital converter module which can be programmed for input of analog signal on up to eight channels. A/D conversion is performed by the successive approximations method with 10-bit resolution. 15.1.1 Features The features of the on-chip A/D module are: •...
Page 288: Block Diagram
15.1.2 Block Diagram Figure 15-1 shows a block diagram of A/D converter. Internal data bus Module data bus 10-Bit D/A ø/8 – Control circuit ø/16 Sample & hold circuit Interrupt signal ADDRA: A/D Data Register A ADDRB: A/D Data Register B ADDRC: A/D Data Register C ADDRD:...
Page 289: Input Pins
15.1.3 Input Pins Table 15-1 lists the input pins used by the A/D converter module. The eight analog input pins are divided into two groups, consisting of analog inputs 0 to 3 (AN ) and analog inputs 4 to 7 (AN to AN ), respectively.
Page 290: Assignment Of Data Registers To Analog Input Channels
15.2 Register Descriptions 15.2.1 A/D Data Registers (ADDR)—H'FFE0 to H'FFE7 ADDRn H Initial value Read/Write (n = A to D) ADDRn H — — — — — — Initial value Read/Write (n = A to D) The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion.
Page 291: A/D Control/Status Register (Adcsr)-H'ffe8
15.2.2 A/D Control/Status Register (ADCSR)—H'FFE8 ADIE ADST SCAN Initial value Read/Write R/(W)* * Software can write a 0 in bit 7 to clear the flag, but cannot write a 1 in this bit. The A/D control/status register (ADCSR) is an 8-bit readable/writable register that controls the operation of the A/D converter module.
Page 292 Bit 5—A/D Start (ADST): The A/D converter operates while this bit is set to 1. In the single mode, this bit is automatically cleared to 0 at the end of each A/D conversion. Bit 5 ADST Description A/D conversion is halted. (Initial value) 1.
Page 293: Cpu Interface
Group Select Channel Select Selected Channels Single Mode Scan Mode and AN to AN to AN and AN to AN to AN 15.3 CPU Interface The A/D data registers (ADDRA to ADDRD) are 16-bit registers. The upper byte of each register can be read directly, but the lower byte is accessed through an 8-bit temporary register (TEMP).
Page 294: Operation
< Upper byte read > Module data bus Bus interface receives data H’AA TEMP [H’40] ADDRn H ADDRn L [H’AA] [H’40] (n = A to D) < Lower byte read > Module data bus Bus interface receives data H’40 TEMP [H’40] ADDRn H ADDRn L...
Page 295: Single Mode
15.4.1 Single Mode The single mode is suitable for obtaining a single data value from a single channel. A/D conversion starts when the ADST bit is set to 1. During the conversion process the ADST bit remains set to 1. When conversion is completed, the ADST bit is automatically cleared to 0. When the conversion is completed, the ADF bit is set to 1.
Page 296 Steps 2 to 7 can now be repeated by setting the ADST bit to 1 again. If the data transfer enable (DTE) bit is set to 1, the interrupt is served by the data transfer controller (DTC). Steps 4 to 7 then change as follows. 4’.
Page 297: A/D Operation In Single Mode (When Channel 1 Is Selected)
Figure 15-3 A/D Operation in Single Mode (When Channel 1 is Selected) Downloaded from Elcodis.com electronic components distributor...
Page 298: Scan Mode
15.4.2 Scan Mode The scan mode can be used to monitor analog inputs on one or more channels. When the ADST bit is set to 1, A/D conversion starts from the first channel selected by the CH bits. When CH2 = 0 the first channel is AN .
Page 299 Note on Scan Mode: If the ADST bit is cleared to 0 while two or more channels are being converted in scan mode, incorrect values may be set in the A/D data registers. This problem is limited to ZTAT versions. It does not occur in versions with masked ROM. Solution: Read the A/D data registers only when the ADST bit is set to 1.
Page 300: A/D Operation In Scan Mode (When Channels 0 To 2 Are Selected)
Figure 15-4 A/D Operation in Scan Mode (When Channels 0 to 2 are Selected) Downloaded from Elcodis.com electronic components distributor...
Page 301: Input Sampling Time And A/D Conversion Time
15.5 Input Sampling Time and A/D Conversion Time The A/D converter includes a built-in sample-and-hold circuit. Sampling of the input starts at a time t after the ADST bit is set to 1. The sampling process lasts for a time t .
Page 302: A/D Conversion Timing
ø Internal address Write signal Input sampling timing CONV : ADCSR write cycle : ADCSR address : Synchronization delay : Input sampling time : Total A/D conversion time CONV Figure 15-5 A/D Conversion Timing Table 15-4 A/D Conversion Time (Single Mode) CKS = “0”...
Page 303: Interrupts And The Data Transfer Controller
15.6 Interrupts and the Data Transfer Controller The ADI interrupt request is enabled or disabled by the ADIE bit in the ADCSR. When the ADI bit in data transfer enable register DTED (bit 0 at address H'FFF7) is set to 1, the ADI interrupt is served by the data transfer controller.
Page 304: Section 16 Ram
Section 16 RAM 16.1 Overview The H8/532 includes 1K byte of on-chip static RAM, connected to the CPU by a 16-bit data bus. Both byte and word access to the on-chip RAM are performed in two states, enabling rapid data transfer and instruction execution.
Page 305: Register Configuration
16.1.2 Register Configuration The on-chip RAM is controlled by the register described in table 16-1. Table 16-1 RAM Control Register Name Abbreviation Initial Value Address RAM control register RAMCR H'FF H'FFF9 16.2 RAM Control Register (RAMCR) RAME — — — —...
Page 306: Single-Chip Mode (Mode 7)
16.3.2 Single-Chip Mode (Mode 7) If the RAME bit is set to 1, accesses to addresses H'FB80 to H'FF7F are directed to the on-chip RAM. If the RAME bit is cleared to 0, access of any type (instruction fetch or data read or write) to addresses H'FB80 to H'FF7F causes an address error and initiates the CPU’s exception-handling sequence.
Page 307: Section 17 Rom
Section 17 ROM 17.1 Overview The H8/532 includes 32K bytes of high-speed, on-chip ROM. The on-chip ROM is connected to the CPU via a 16-bit data bus and is accessed in two states. Users wishing to program the chip themselves can request electrically programmable ROM (PROM).
Page 308: Prom Modes
Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) Addresses H'0000 H'0002 On-chip ROM H'7FFF Even addresses Odd addresses Figure 17-1 Block Diagram of On-Chip ROM 17.2 PROM Mode 17.2.1 PROM Mode Setup The PROM version of the H8/532 has a PROM mode in which the usual microcomputer functions are halted to allow the on-chip PROM to be programmed.
Page 309: Socket Adapter Pin Arrangements And Memory Map
17.2.2 Socket Adapter Pin Arrangements and Memory Map The H8/532 can be programmed with a general-purpose PROM writer by attaching a socket adapter as listed in table 17-3. The socket adapter depends on the type of package. Figure 17-2 shows the socket adapter pin arrangements by giving the correspondence between H8/532 pins and HN27C256 pin functions.
Page 310: Socket Adapter Pin Arrangements
H8/532 EPROM socket FP-80A CG-84, CP-84 HN27C256 (28 pins) • • • • • • • • STBY Programming power (12.5V) • to E Data input/output • to EA : Address input • Output enable • Chip enable • — •...
Page 311: Programming
Address in MCU mode Address in PROM mode H'0000 H'0000 On-chip ROM H'7FFF H'7FFF Figure 17-3 Memory Map in PROM Mode 17.3 Programming The write, verify, and inhibited sub-modes of the PROM mode are selected as shown in table 17-4. Table 17-4 Selection of Sub-Modes in PROM Mode Pins Mode...
Page 312: High-Speed Programming Flowchart
Figure 17-4 shows the basic high-speed programming flowchart. Tables 17-5 and 17-6 list the electrical characteristics of the chip in the PROM mode. Figure 17-5 shows a write/verify timing chart. START SET program mode Vcc = 6.0V ±0.25V, Vpp = 12.5V ±0.3V Address = 0 n = 0 →...
Page 313: Cc = 6.0V ±0.25V, V Pp = 12.5V ±0.3V, V Ss = 0V
Table 17-5 DC Characteristics (When V = 6.0V ±0.25V, V = 12.5V ±0.3V, V = 0V, Ta = 25˚C ±5˚C) Sym- Measurement Item Min Typ Max Unit Conditions Input High voltage O to O to A , OE, CE V —...
Page 314: Notes On Writing
Caution: Applied voltages in excess of the specified values can permanently destroy to the chip. Be particularly careful about the PROM writer’s overshoot characteristics. If the PROM writer is set to Intel specifications or Hitachi HN27256 or HN27C256 specifications, Vpp will be 12.5V.
Page 315: Reliability Of Written Data
PROM writer and socket adapter for defects, using a microcomputer with a windowed package and on-chip EPROM. Please inform Hitachi of any abnormal conditions noted during programming or in screening of program data after high-temperature baking. Downloaded from Elcodis.com...
Page 316: Erasing Of Data
17.3.4 Erasing of Data The windowed package enables data to be erased by illuminating the window with ultraviolet light. Table 17-7 lists the erasing conditions. Table 17-7 Erasing Conditions Item Value Ultraviolet wavelength 253.7nm Minimum illumination 15W·s/cm The conditions in table 17-7 can be satisfied by placing a 12000µW/cm ultraviolet lamp 2 or 3 centimeters directly above the chip and leaving it on for about 20 minutes.
Page 317: Socket For 84-Pin Lcc Package
In addition, exposure to any type of intense light can induce photoelectric effects that may lead to chip malfunction. It is recommended that after programming the chip, you cover the erasing window with a light-proof label (such as an ultraviolet-shield label). 3.
Page 318: Section 18 Power-Down State
Section 18 Power-Down State 18.1 Overview The H8/532 has a power-down state that greatly reduces power consumption by stopping the CPU functions. The power-down state includes three modes: 1. Sleep mode— a software-triggered mode in which the CPU halts but the rest of the chip remains active 2.
Page 319: Sleep Mode
18.2 Sleep Mode 18.2.1 Transition to Sleep Mode Execution of the SLEEP instruction causes a transition from the program execution state to the sleep mode. After executing the SLEEP instruction, the CPU halts, but the contents of its internal registers remain unchanged. The functions of the on-chip supporting modules do not stop in the sleep mode.
Page 320: Software Standby Control Register (Sbycr)
Table 18-2 Software Standby Control Register Name Abbreviation Initial Value Address Software standby control register SBYCR H'7F H'FFFB In the software standby mode, the CPU, clock, and the on-chip supporting module functions all stop, reducing power consumption to an extremely low level. The on-chip supporting modules and their registers are reset to their initial state, but as long as a minimum necessary voltage supply is maintained (at least 2V), the contents of the CPU registers and on-chip RAM remain unchanged.
Page 321: Exit From Software Standby Mode
18.3.3 Exit from Software Standby Mode The chip can be brought out of the software standby mode by an input at one of three pins: the NMI pin, RES pin, or STBY pin. 1. Recovery by NMI Pin: When an NMI request signal is received, the clock oscillator begins operating but clock pulses are supplied only to the watchdog timer (WDT).
Page 322: Application Notes
Oscillator ø NMEG SSBY Clock setting time NMI interrupt handling Software standby mode NMI interrupt handling WDT interval (t OSC2 NMIEG = 1 (Power-down state) SSBY = 1 SLEEP instruction Clock start-up time WDT overflow Figure 18-1 NMI Timing of Software Standby Mode (Application Example) 18.3.5 Application Notes (1) The I/O ports retain their current states in the software standby mode.
Page 323: Hardware Standby Mode
• Store program code only in on-chip ROM. • Use the hardware standby mode. There is never any additional current in hardware standby mode. 18.4 Hardware Standby Mode 18.4.1 Transition to Hardware Standby Mode Regardless of its current state, the chip enters the hardware standby mode whenever the STBY pin goes Low.
Page 324: Timing Sequence Of Hardware Standby Mode
18.4.3 Timing Sequence of Hardware Standby Mode Figure 18-2 shows the usual sequence for entering and leaving the hardware standby mode. First the RES pin goes Low, placing the chip in the reset state. Then the STBY pin goes Low, placing the chip in the hardware standby mode and stopping the clock.
Page 325: Section 19 E Clock Interface
Section 19 E Clock Interface 19.1 Overview For interfacing to E clock based peripheral devices, the H8/532 can generate an E clock output. Special instructions (MOVTPE, MOVFPE) perform data transfers synchronized with the E clock. The E clock is created by dividing the system clock (ø) by 8. The E clock is output at the P1 when the P1 DDR bit in the port 1 data direction register (P1DDR) is set to 1.
Page 326: Execution Cycle Of Instruction Synchronized With E Clock In Expanded Modes
Figure 19-1 Execution Cycle of Instruction Synchronized with E Clock in Figure 19-1 Execution Cycle of Instruction Synchronized with E Clock in Expanded Modes (Maximum Synchronization Delay) Expanded Modes (Maximum Synchronization Delay) Downloaded from Elcodis.com electronic components distributor...
Page 327: Execution Cycle Of Instruction Synchronized With E Clock In Expanded Modes
Last state ø to A DS (Read access), DS (Write access), D to D (Read access) D to D (Write access) Figure 19-2 Execution Cycle of Instruction Synchronized with E Clock in Expanded Modes (Minimum Synchronization Delay) Downloaded from Elcodis.com electronic components distributor...
Page 328: Section 20 Electrical Specifications
Section 20 Electrical Specifications 20.1 Absolute Maximum Ratings Table 20-1 lists the absolute maximum ratings. Table 20-1 Absolute Maximum Ratings Item Symbol Rating Unit Supply voltage –0.3 to +7.0 Programming voltage –0.3 to +13.5 Input voltage (except Port 8) –0.3 to V + 0.3 (Port 8) –0.3 to AV...
Page 329: Dc Characteristics
Table 20-2 DC Characteristics Conditions: V = 5.0V ±10% , AV = 5.0V ±10%, = AV = 0V, = –20 to +75˚C (Regular Specifications) = –40 to +85˚C (Wide-Range Specifications) Sym- Measurement Item Unit Conditions Input High voltage RES, STBY, –...
Page 330: Allowable Output Current Sink Values
Table 20-2 DC Characteristics (cont) Sym- Measurement Item Unit Conditions Current dissipation Normal operation – f = 6 MHz – f = 8 MHz – f = 10 MHz Sleep mode – f = 6 MHz – f = 8 MHz –...
Page 331: Ac Characteristics
H8/532 H8/532 - - - - - - - - - - - - - 2 kΩ Port 600 Ω - - - - - - - - - - - - - Darlington pair Port 4 Figure 20-1 Example of Circuit for Driving a Figure 20-2 Example of Circuit for Driving Darlington Transistor Pair an LED...
Page 332 Table 20-4 Bus Timing (cont) 6MHz 8MHz 10MHz Measurement Item Symbol Min Max Min Max Unit Conditions Address setup time 2 – – – See figure 20-4 Read data setup time – – – Read data hold time – – –...
Page 333: Control Signal Timing
Table 20-5 Control Signal Timing Conditions: V = 5.0V ±10%, AV = 5.0V ±10%, ø = 0.5 to 10MHz, V = 0V = –20 to +75˚C (Regular Specifications) = –40 to +85˚C (Wide-Range Specifications) 6MHz 8MHz 10MHz Measurement Item Symbol Min Max Min Max Unit Conditions RES setup time –...
Page 334: Output Load Circuit
Table 20-6 Timing Conditions of On-Chip Supporting Modules Conditions: V = 5.0V ±10%, AV = 5.0V ±10%, ø = 0.5 to 10MHz, V = 0V = –20 to +75˚C (Regular Specifications) = –40 to +85˚C (Wide-Range Specifications) 6MHz 8MHz 10MHz Measurement Item Symbol Min Max...
Page 335: A/D Converter Characteristics
20.2.3 A/D Converter Characteristics Table 20-7 lists the characteristics of the on-chip A/D converter. Table 20-7 A/D Converter Characteristics Conditions: V = 5.0V ±10%, AV = 5.0V ±10%, V = AV = 0V, = –20 to +75˚C (Regular Specifications) = –40 to +85˚C (Wide-Range Specifications) 6MHz 8MHz 10MHz...
Page 336: Basic Bus Cycle (Without Wait States) In Expanded Modes
20.3.1 Bus Timing 1. Basic Bus Cycle (without Wait States) in Expanded Modes ø to A DSD1 DSD3 DS (Read), D to D (Read) DSD2 DSD3 DSWW DS (Write), D to D (Write) Figure 20-4 Basic Bus Cycle (without Wait States) in Expanded Modes Downloaded from Elcodis.com electronic components distributor...
Page 337: Basic Bus Cycle (With 1 Wait State) In Expanded Modes
2. Basic Bus Cycle (with 1 Wait State) in Expanded Modes ø to A DS (Read), D to D (Read) DS (Write), D to D (Write) WAIT Figure 20-5 Basic Bus Cycle (with 1 Wait State) in Expanded Modes Downloaded from Elcodis.com electronic components distributor...
Page 338: Bus Cycle Synchronized With E Clock
3. Bus Cycle Synchronized with E Clock ø to A DSD3 DS (Read), RDHE D to D (Read) DSD3 DS (Write), WDHE D to D (Write) Figure 20-6 Bus Cycle Synchronized with E Clock Downloaded from Elcodis.com electronic components distributor...
Page 339: Reset Input Timing
20.3.2 Control Signal Timing 1. Reset Input Timing ø RESS RESS RESW MD to MD Figure 20-7 Reset Input Timing 2. Interrupt Input Timing ø NMIS NMIH IRQ1S IRQ1H IRQ0S Figure 20-8 Interrupt Input Timing 3. NMI Pulse Width NMIW Figure 20-9 NMI Pulse Width (for Recovery from Software Standby Mode) Downloaded from Elcodis.com...
Page 340: Clock Timing
4. Bus Release State Timing ø BRQS BRQS BREQ (Input) BACD1 BACD2 BACK (Output) to A , R/W, DS, RD, WR, Figure 20-10 Bus Release State Timing 20.3.3 Clock Timing 1. E Clock Timing ø Figure 20-11 E Clock Timing Downloaded from Elcodis.com electronic components distributor...
Page 341: Clock Oscillator Stabilization Timing
2. Clock Oscillator Stabilization Timing Figure 20-12 Clock Oscillator Stabilization Timing Downloaded from Elcodis.com electronic components distributor...
Page 342: I/O Port Timing
20.3.4 I/O Port Timing Port read/write cycle ø Port 1 (Input) port 9 Port 1* (Output) port 9 * Except P1 , P1 , and P8 to P8 Figure 20-13 I/O Port Input/Output Timing Downloaded from Elcodis.com electronic components distributor...
Page 343: 16-Bit Free-Running Timer Timing
20.3.5 16-Bit Free-Running Timer Timing 1. Free-Running Timer Input/Output Timing ø Free-running Compare-match timer counter FTOD FTOA , FTOB , FTOA , FTOB , FTOA , FTOB FTIS FTI , FTI , FTI Figure 20-14 Free-Running Timer Input/Output Timing 2. External Clock Input Timing for Free-Running Timers ø...
Page 344: 8-Bit Timer Timing
20.3.6 8-Bit Timer Timing 1. 8-Bit Timer Output Timing ø Timer Compare-match counter TMOD Figure 20-16 8-Bit Timer Output Timing 2. 8-Bit Timer Clock Input Timing ø TMCS TMCS TMCI TMCWL TMCWH Figure 20-17 8-Bit Timer Clock Input Timing 3. 8-Bit Timer Reset Input Timing ø...
Page 345: Pulse Width Modulation Timer Timing
20.3.7 Pulse Width Modulation Timer Timing ø Timer Compare-match counter PWOD PW , PW , Figure 20-19 PWM Timer Output Timing 20.3.8 Serial Communication Interface Timing SCKW Scyc Figure 20-20 SCI Input Clock Timing Scyc Serial clock Transmit data Receive data Figure 20-21 SCI Input/Output Timing (Synchronous Mode) Downloaded from...
Page 346: Appendix A Instructions
Appendix A Instructions A.1 Instruction Set Operation Notation General register (destination operand) Frame pointer General register (source operand) #IMM Immediate data General register disp Displacement (EAd) Destination operand (EAs) Source operand – Subtract × Condition code register Multiply ÷ N (Negative) flag in CCR Divide ∧...
Page 347 Size CCR Bit Mnemonic Operation (EAs) → Rd Data MOV: G — → (EAd) transfer #IMM → (EAd) #IMM → Rd MOV: E (short format) — @ (d: 8, FP) → Rd MOV: F — → @ (d: 8, FP)(short format) #IMM →...
Page 348 Size CCR Bit Mnemonic Operation Arith- EXTS (< Bit 7 > of < Rd >) → (< Bit 15 to 8 > of < Rd >) metic 0 → (<Bit 15 to 8 > of < Rd >) opera- EXTU tions (EAd) –...
Page 349 Size CCR Bit Mnemonic Operation Branch- Bcc If condition is true then — — — — — PC + disp  → PC instruc- else next; tions Mnemonic Description Condition (BT) Always (True) True (BF) Never (False) False C ∨ Z = 0 HIgh C ∨...
Page 350 Size CCR Bit Mnemonic Operation PC  → @ – SP System TRAPA — — — — — (If MAX MODE CP → @ – SP) control SR  → @ – SP (If MAX MODE < vector >  → CP) <...
Page 351: Instruction Codes
A.2 Instruction Codes Table A-1 shows the machine-language coding of each instruction. • How to read table A-1 (a) to (d) The general operand format consists of an effective address (EA) field and operation-code (OP) field specified in the following order. EA field Op field Bytes 2, 3, 5, 6 are not present in all instructions.
Page 352 Operation code (OP) Instruction MOV:G.B <EA >, R 2 2 3 4 2 2 3 4 3 1 0 0 0 0 r r r d d d MOV:G.W <EA >, R 2 2 3 4 2 2 3 4 1 0 0 0 0 r r r d d d MOV:G.B R , <EA >...
Page 353 • rrr : General register number field Sz = 0 (Byte) Sz = 1 (Word) Not used Not used Not used Not used Not used Not used Not used Not used • ccc : Control register number field Sz = 0 (Byte) Sz = 1 (Word) (Not allowed*) (Not allowed)
Page 354 • register list: A byte in which bits indicate general registers as follows • #VEC: Four bits designating a vector number from 0 to 15. The vector numbers correspond to addresses of entries in the exception vector table as follows: Vector Address Vector Address #VEC Minimum Mode...
Page 355 Table A-1 (a) Machine Language Coding [General Format] Operation code (OP) Instruction MOV:G.B <EA >, R 2 2 3 4 2 2 3 4 3 1 0 0 0 0 MOV:G.W <EA >, R 2 2 3 4 2 2 3 4 1 0 0 0 0 MOV:G.B R , <EA >...
Page 356 Table A-1 (a) Machine Language Coding [General Format] (cont) Operation code (OP) Instruction DADD.B R ,R 0 0 0 0 0 0 0 0 1 0 1 0 0 SUB.B <EA >, R 2 2 3 4 2 2 3 4 0 0 1 1 0 SUB.W <EA >, R 2 3 4 2 2 3 4...
Page 357 Table A-1 (a) Machine Language Coding [General Format] (cont) Operation code (OP) Instruction SHAL.B <EA > 2 2 3 4 2 2 3 4 0 0 0 1 1 0 0 0 SHAL.W <EA > 2 2 3 4 2 2 3 4 0 0 0 1 1 0 0 0 SHAR.B <EA >...
Page 358 Table A-1 (a) Machine Language Coding [General Format] (cont) Operation code (OP) Instruction BSET.B #xx, <EA > 2 2 3 4 2 2 3 4 1 1 0 0 (data) BSET.W #xx, <EA > 2 2 3 4 2 2 3 4 1 1 0 0 (data) BSET.B R , <EA >...
Page 359 Table A-1 (b) Machine Language Coding [Special Format: Short Format] Operation code Instruction Byte MOV:E,B #xx:8,Rd 01010r data MOV:I.W #xx:16,Rd 01011r data (H) data (L) MOV:L.B @aa:8,Rd 01100r address (L) MOV:L.W @aa:8,Rd 01101r address (L) MOV:S.B Rs,@aa:8 01110r address (L) MOV:S.W Rs,@aa:8 01111r address (L)
Page 360: Operation Code Map
Table A-1 (c) Machine Language Coding [Special Format: Branch Instruction] Operation code Instruction Byte Bcc d:8 BRA (BT) 00100000 disp BRN (BF) 00100001 disp 00100010 disp 00100011 disp BCC (BHS) 00100100 disp BCS (BLO) 00100101 disp 00100110 disp 00100111 disp 00101000 disp 00101001...
Page 361 Table A-1 (c) Machine Language Coding [Special Format: Branch Instruction] Operation code Instruction Byte JMP @(d:8,Rn) 00010001 11100rrr disp JMP @(d:16,Rn) 00010001 11110rrr disp (H) disp (L) BSR d:8 00001110 disp BSR d:16 00011110 disp (H) disp (L) JSR @Rn 00010001 11011rrr JSR @aa:16...
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Page 367: Instruction Execution Cycles
A.4 Instruction Execution Cycles Tables A-7 (1) through (6) list the number of cycles required by the CPU to execute each instruction in each addressing mode. The meaning of the symbols in the tables is explained below. The values of I, J, and K are used to calculate the number of execution cycles when off-chip memory is accessed for an instruction fetch or operand read/write.
Page 368: Tables Of Instruction Execution Cycles
A.4.2 Tables of Instruction Execution Cycles Tables A-7 (1) through (6) should be read as shown below: J + K: Number of instruction fetch cycles. Addressing mode I: Total number of bytes written and read when operand is in memory. Instruction ADD.B ADD.W...
Page 369 • Examples of Calculation of Number of States Required for Execution (Example 1) Instruction fetch from on-chip memory Operand Start Assembler Notation Table A-7 + Number Read/Write Addr. Address Code Mnemonic Table A-8 of States On-chip memory Even H'0100 H'D821 ADD @R0, R1 5 + 1 or general register...
Page 370 Table A-7 Instruction Execution Cycles (1) Addressing mode Instruction ADD:G.B ADD:G.W ADD:Q.B ADD:Q.W ADDS.B ADDS.W ADDX.B ADDX.W AND.B AND.W ANDC BCLR.B BCLR.W BNOT.B BNOT.W BSET.B BSET.W BTST.B BTST.W CLR.B CLR.W CMP:G.B CMP:G.W CMP:G.B #XX:8, <EA> CMP:G.B #XX:16, <EA> Downloaded from Elcodis.com electronic components distributor...
Page 371 Table A-7 Instruction Execution Cycles (2) Addressing mode Addressing mode Instruction CMP:E #xx:8, R Instruction CMP:I #xx:16, R CMP:E #xx:8,Rd DADD CMP:I #xx:16,Rd DIVXU.B 23 24 DADD DIVXU.W 29 30 DIVXU.B 24 23 24 DSUB DIVXU.W 30 29 30 EXTS DSUB EXTU EXTS...
Page 372 Table A-7 Instruction Execution Cycles (3) Addressing mode Instruction MOVFPE MOVTPE MULXU.B 19 20 MULXU.W 25 26 NEG.B NEG.W NOT.B NOT.W OR.B OR.W ROTL.B ROTL.W ROTR.B ROTR.W ROTXL.B ROTXL.W ROTXR.B ROTXR.W SHAL.B SHAL.W SHAR.B SHAR.W SHLL.B SHLL.W MOVFPE and MOVTPE are executed synchronous with the E-clock, so the number of execution states will change depending on timing of the execution.
Page 373 Table A-7 Instruction Execution Cycles (4) Addressing mode Instruction SHLR.B SHLR.W STC.B STC.W SUB.B SUB.W SUBS.B SUBS.W SUBX.B SUBX.W SWAP TST.B TST.W XOR.B XOR.W XORC DIVXU.B Zero divide, minimum mode 23 24 DIVXU.B Zero divide, maximum mode 28 29 DIVXU.W Zero divide, minimum mode 23 24 DIVXU.W...
Page 374 Table A-7 Instruction Execution Cycles (5) Instruction (Condition) Execution Cycles J + K Bcc d:8 Condition false, branch not taken Condition true, branch taken Bcc d:16 Condition false, branch not taken Condition true, branch taken d:16 @aa:16 @(d:8, Rn) @(d:16, Rn) @aa:16 @(d:8, Rn) @(d:16, Rn)
Page 375 Table A-7 Instruction Execution Cycles (6) Instruction (Condition) Execution Cycles J + K TRAPA Minimum mode Maximum mode TRAP/VS V = 0, trap not taken V = 1, trap taken, minimum mode V = 1, trap taken, maximum mode UNLK PJMP @aa:24 PJSR...
Page 376: Appendix B Register Field
Appendix B Register Field B.1 Register Addresses and Bit Names Addr. (last Register Bit Names byte) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'80 P1DDR DDR P1 DDR P1 DDR P1 DDR P1 DDR P1...
Page 377 (Continued from preceding page) Addr. (last Register Bit Names byte) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'A0 ICIE OCIEB OCIEA OVIE CKS1 CKS0 H'A1 TCSR OCFB OCFA OLVLB OLVLA IEDG CCLRA...
Page 378 (Continued from preceding page) Addr. (last Register Bit Names byte) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'C0 — — — CKS2 CKS1 CKS0 H'C1 PWM1 H'C2 TCNT H'C3 —...
Page 379 (Continued from preceding page) Addr. (last Register Bit Names byte) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'E0 ADDRA (H) AD ADDRA (L) AD H'E1 — — — — —...
Page 380 (Continued from preceding page) Addr. (last Register Bit Names byte) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'F0 IPRA — — H'F1 IPRB — — H'F2 IPRC — — 8 Bit Timer H'F3 IPRD...
Page 381: Register Descriptions
B.2 Register Descriptions Register name Address to which the Name of the on-chip register is mapped supporting module Acronym of the register SYSCR1—System Control Register 1 H'FEFC Port 1 numbers Names of the — NMIEG BRLE — — — bits. Initial bit Initial value Dashes (—)
Page 382 P1DDR—Port 1 Data Direction Register H'FF80 Port 1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 Initial value Read/Write Port 1 Input/Output Selection 0 Input port 1 Output port P1DR—Port 1 Data Register H'FF82 Port 1 Initial value —...
Page 383 P1CR—Port 1 Control Register H'FFFC Port 1 — NMIEG BRLE — — — Initial value Read/Write — — — — Bus Release Enable 0 P1 and P1 are I/O ports. 1 P1 is the output pin and is the input pin. Nonmaskable Interrupt Edge 0 An NMI request is generated on the falling edge of the NMI pin input.
Page 384 P2DR—Port 2 Data Register H'FF83 Port 2 — — — Initial value Read/Write — — — P3DDR—Port 3 Data Direction Register H'FF84 Port 3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 Initial value Read/Write Port 3 Input/Output Selection 0 Input port...
Page 385 P4DR—Port 4 Data Register H'FF87 Port 4 Initial value Read/Write P5DDR—Port 5 Data Direction Register H'FF88 Port 5 DDR P5 DDR P5 DDR P5 DDR P5 DDR P5 DDR P5 DDR P5 Initial value Read/Write Port 5 Input/Output Selection 0 Input port 1 Output port P5DR—Port 5 Data Register H'FF8A...
Page 386 P6DR—Port 6 Data Register H'FF8B Port 6 — — — — Initial value Read/Write — — — — P7DDR—Port 7 Data Direction Register H'FF8C Port 7 DDR P7 DDR P7 DDR P7 DDR P7 DDR P7 DDR P7 DDR P7 Initial value Read/Write Port 7 Input/Output Selection...
Page 387 P9DDR—Port 9 Data Direction Register H'FFFE Port 9 DDR P9 DDR P9 DDR P9 DDR P9 DDR P9 DDR P9 DDR P9 Initial value Read/Write Port 9 Input/Output Selection 0 Input port 1 Output port P9DR—Port 9 Data Register H'FFFF Port 9 Initial value Read/Write...
Page 388 TCR—Timer Control Register H'FF90 FRT1 ICIE OCIEB OCIEA OVIE CKS1 CKS0 Initial value Read/Write Clock Select 00 Internal clock source: ø4 01 Internal clock source: ø8 10 Internal clock source: ø32 11 External clock source: counted on rising edge Output Enable A 0 Compare-A output is disabled.
Page 389 TCSR—Timer Control/Status Register H'FF91 FRT1 OCFB OCFA OLVLB OLVLA IEDG CCLRA Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* Counter Clear A FRC count is not cleared. FRC count is cleared by compare- match A. Input Edge Select Count is captured on falling edge of input capture signal (FTI).
Page 390 FRC (H and L)—Free-Running Counter H'FF92, H'FF93 FRT 1 Initial value Read/Write Count value OCRA (H and L)—Output Compare Register A H'FF94, H'FF95 FRT 1 Initial value Read/Write Continually compared with FRC. OCFA is set to 1 when OCRA = FRC. OCRB (H and L)—Output Compare Register B H'FF96, H'FF97 FRT 1...
Page 391 TCR—Timer Control Register H'FFA0 FRT 2 ICIE OCIEB OCIEA OVIE CKS1 CKS0 Initial value Read/Write Note: Bit functions are the same as for FRT1. TCSR—Timer Control/Status Register H'FFA1 FRT 2 OCFB OCFA OLVLB OLVLA IEDG CCLRA Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)*...
Page 392 OCRA (H and L)—Output Compare Register A H'FFA4, H'FFA5 FRT 2 Initial value Read/Write Note: Bit functions are the same as for FRT1. OCRB (H and L)—Output Compare Register B H'FFA6, H'FFA7 FRT 2 Initial value Read/Write Note: Bit functions are the same as for FRT1. ICR (H and L)—Input Capture Register H'FFA8, H'FFA9 FRT 2...
Page 393 TCSR—Timer Control/Status Register H'FFB1 FRT 3 OCFB OCFA OLVLB OLVLA IEDG CCLRA Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* Note: Bit functions are the same as for FRT1. * Only writing of 0 to clear the flag is enabled. FRC (H and L)—Free-Running Counter H'FFB2, H'FFB3 FRT 3 Initial value...
Page 394 OCRB (H and L)—Output Compare Register B H'FFB6, H'FFB7 FRT 3 Initial value Read/Write Note: Bit functions are the same as for FRT1. ICR (H and L)—Input Capture Register H'FFB8, H'FFB9 FRT 3 Initial value Read/Write Note: Bit functions are the same as for FRT1. Downloaded from Elcodis.com electronic components distributor...
Page 395 TCR—Timer Control Register H'FFC0 PWM1 — — — CKS2 CKS1 CKS0 Initial value Read/Write — — — Clock Select (Values When ø = 10MHz) Internal Reso- Clock Freq. lution Period Frequency 000 ø/2 200ns 50µs 20kHz 001 ø/8 800ns 200µs 5kHz 010 ø/32 3.2µs...
Page 396 TCNT—Timer Counter H'FFC2 PWM1 Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Count value (runs from H'00 to H'F9, then repeats from H'00) * Write function is for test purposes only. Writing to this register during normal operation may have unpredictable effects TCR—Timer Control Register H'FFC4...
Page 397 TCNT—Timer Counter H'FFC6 PWM2 Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: Bit functions are the same as for PWM1. * Write function is for test purposes only. Writing to this register during normal operation may have unpredictable effects TCR—Timer Control Register H'FFC8...
Page 398 TCNT—Timer Counter H'FFCA PWM3 Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: Bit functions are the same as for PWM1. * Write function is for test purposes only. Writing to this register during normal operation may have unpredictable effects.
Page 399 TCR—Timer Control Register H'FFD0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value Read/Write Clock Select 0 0 0 No clock source; timer stops. 0 0 1 Internal clock source: ø8, counted on falling edge. 0 1 0 Internal clock source: ø64, counted on falling edge.
Page 400 TCSR—Timer Control/Status Register H'FFD1 CMFB CMFA — Initial value Read/Write R/(W) R/(W) R/(W) — Output Select 0 0 No change on compare-match A. 0 1 Output 0 on compare-match A. 1 0 Output 1 on compare-match A. 1 1 Invert (toggle) output on compare-match A. Output Select 0 0 No change on compare-match B.
Page 401 TCORA—Time Constant Register A H'FFD2 Initial value Read/Write The CMFA bit is set to 1 when TCORA = TCNT. TCORB—Time Constant Register B H'FFD3 Initial value Read/Write The CMFB bit is set to 1 when TCORB = TCNT. TCNT—Timer Counter H'FFD4 Initial value Read/Write...
Page 402 SMR—Serial Mode Register H'FFD8 STOP — CKS1 CKS0 Initial value Read/Write — Clock Select 0 0 ø clock 0 1 ø/4 clock 1 0 ø/16 clock 1 1 ø/64 clock Stop Bit Length 0 One stop bit 1 Two stop bits Parity Mode 0 Even parity 1 Odd parity...
Page 403 BRR—Bit Rate Register H'FFD9 Initial value Read/Write Constant that determines the baud rate SCR—Serial Control Register H'FFDA — — CKE1 CKE0 Initial value Read/Write — — Clock Enable 0 0 SCK pin is NOT USED. 1 SCK pin is used for output. Clock Enable 1 0 Internal clock 1 External clock, input at SCK pin...
Page 404 TDR—Transmit Data Register H'FFDB Initial value Read/Write Transmit data Downloaded from Elcodis.com electronic components distributor...
Page 405 SSR—Serial Status Register H'FFDC TDRE RDRF ORER — — — Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* — — — Parity Error 0 Cleared from 1 to 0 when: 1. CPU reads PER = 1, then writes 0 in PER. 2.
Page 406 RDR—Receive Data Register H'FFDD Initial value Read/Write Receive data ADDRn (H)—A/D Data Register n (High) H'FFE0, H'FFE2, H'FFE4, H'FFE6 (n = A, B, C, D) Initial value Read/Write Upper 8 bits of 10-bit A/D conversion result ADDRn (L)—A/D Data Register n (Low) H'FFE1, H'FFE3, H'FFE5, H'FFE7 (n = A, B, C, D) —...
Page 407 ADCSR—A/D Control/Status Register H'FFE8 ADIE ADST SCAN Initial value Read/Write R/(W)* Channel Select CH2 CH1 CH0 Single Mode Scan Mode , AN to AN to AN , AN to AN to AN Clock Select 0 Conversion time = 274 states 1 Conversion time = 138 states Scan Mode 0 Single mode...
Page 408 TCSR—Timer Status/Control Register H'FFEC , H'FFED WT/IT — — CKS2 CKS1 CKS0 Initial value Read/Write R/(W) — — Clock Select 0 0 0 ø/2 (51.2µs) 0 0 1 ø/32 (819.2µs) 0 1 0 ø/64 (1.6ms) 0 1 1 ø/128 (3.3ms) 1 0 0 ø/256 (6.6ms) 1 0 1 ø/512...
Page 409 TCNT—Timer Counter H'FFED Initial value Read/Write Count value IPRA—Interrupt Priority Register A H'FFF0 INTC — — Initial value Read/Write interrupt priority level (0 to 7) interrupt priority level (0 to 7) IPRB—Interrupt Priority Register B H'FFF1 INTC — — Initial value Read/Write 16-Bit FRT1 interrupt 16-Bit FRT2 interrupt...
Page 410 IPRC—Interrupt Priority Register C H'FFF2 INTC — — Initial value Read/Write 16-Bit FRT3 interrupt 8-Bit timer interrupt priority level (0 to 7) priority level (0 to 7) IPRD—Interrupt Priority Register D H'FFF3 INTC — — Initial value Read/Write SCI interrupt priority A/D interrupt priority level (0 to 7) level (0 to 7)
Page 411 DTEB—Data Transfer Enable Register B H'FFF5 INTC — — Initial value Read/Write 16-Bit FRT channel 1 16-Bit FRT channel 2 0 Served by CPU 1 Served by DTC OCIA 0 Served by CPU 1 Served by DTC OCIB 0 Served by CPU 1 Served by DTC 0 Served by CPU 1 Served by DTC...
Page 412 DTEC—Data Transfer Enable Register C H'FFF6 INTC — — — Initial value Read/Write 16-Bit FRT channel 3 8-Bit timer CMIA 0 Served by CPU 1 Served by DTC CMIB 0 Served by CPU 1 Served by DTC 0 Served by CPU 1 Served by DTC OCIA 0 Served by CPU...
Page 413 DTED—Data Transfer Enable Register D H'FFF7 INTC — — — — — Initial value Read/Write A/D converter 0 Served by CPU 1 Served by DTC 0 Served by CPU 1 Served by DTC 0 Served by CPU 1 Served by DTC Downloaded from Elcodis.com electronic components distributor...
Page 414 WCR—Wait-State Control Register H'FFF8 — — — — WMS1 WMS0 Initial value Read/Write — — — — Wait Count 1 and 0 0 0 No wait states (T are inserted. 0 1 1 Wait states are inserted. 1 0 2 Wait states are inserted. 1 1 3 Wait state is inserted.
Page 415 MDCR—Mode Control Register H'FFFA — — — — — MDS2 MDS1 MDS0 Initial value —* —* —* Read/Write — — — — — Mode Select Value input at mode pins * Initialized according to the inputs at pins MD , MD , and MD SBYCR—Software Standby Control Register H'FFFB...
Page 416: A) Schematic Diagram Of Port 1, Pin P1
Appendix C I/O Port Schematic Diagrams C.1 Schematic Diagram of Port 1 Figure C-1 (a) to (g) gives a schematic view of the port 1 input/output circuits. Reset WP1D: Write to P1DDR RP1: Read Port 1 P1 DDR WP1D ø Figure C-1 (a) Schematic Diagram of Port 1, Pin P1 Table C-1 (a) Port 1 Port Read (Pin P1 Setting...
Page 417: C) Schematic Diagram Of Port 1, Pin P1
Table C-1 (b) Port 1 Port Read (Pin P1 Setting Port Read Data DDR = 0 Pin value DDR = 1 WP1D: Write to P1DDR Reset WP1: Write to Port 1 RP1: Read Port 1 P1 DDR WP1D Reset P1 DR Port 1 control register, bit 3 Mode 1, 2, 3,...
Page 418: D) Schematic Diagram Of Port 1, Pin P1
WP1D: Write to P1DDR Reset WP1: Write to Port 1 RP1: Read Port 1 P1 DDR WP1D Reset P1 DR Port 1 control register, bit 3 Mode 1, 2, 3, BRLE or 4 BREQ to CPU Figure C-1 (d) Schematic Diagram of Port 1, Pin P1 Table C-1 (d) Port 1 Port Read (Pin P1 Mode Setting...
Page 419: E) Schematic Diagram Of Port 1, Pin P1
WP1D: Write to P1DDR Reset WP1: Write to Port 1 RP1: Read Port 1 P1 DDR WP1D Reset P1 DR Wait-state control register, bit 3 Mode 1, 2, 3, WMS1 or 4 WAIT to CPU Figure C-1 (e) Schematic Diagram of Port 1, Pin P1 Table C-1 (e) Port 1 Port Read (Pin P1 Mode Setting...
Page 420 Reset WP1D: Write to P1DDR WP1: Write to Port 1 RP1: Read Port 1 P1 DDR 5 or 6 WP1D Reset Port 1 control register, bits 5 and 6 P1 DR IRQ E IRQ E IRQ , IRQ to CPU Figure C-1 (f) Schematic Diagram of Port 1, Pins P1 and P1 Table C-1 (f) Port 1 Port Read (Pins P1...
Page 421 WP1D: Write to P1DDR Reset WP1: Write to Port 1 RP1: Read Port 1 P1 DDR WP1D Reset P1 DR 8-Bit timer module Output enable 8-Bit timer output Figure C-1 (g) Schematic Diagram of Port 1, Pin P1 Table C-1 (g) Port 1 Port Read (Pin P1 Setting Port Read Data 8-bit timer output enable...
Page 422: Port 2 Port Read
C.2 Schematic Diagram of Port 2 Figure C-2 gives a schematic view of the port 2 input/output circuits. Mode 1, 2, 3, or 4 Software standby WP2D: Write to P2DDR WP2: Write to Port 2 Bus release RP2: Read Port 2 Reset 0, 1, 2, 3, or 4 P2 DDR...
Page 423: Port 3 Port Read
C.3 Schematic Diagram of Port 3 Figure C-3 gives a schematic view of the port 3 input/output circuits. Data bus control WP3D: Write to P3DDR WP3: Write to Port 3 Mode 1, 2, 3, or 4 Reset RP3: Read Port 3 0 to 7 P3 DDR Mode 7...
Page 424: Port 4 Port Read
C.4 Schematic Diagram of Port 4 Figure C-4 gives a schematic view of the port 4 input/output circuits. Mode 1, 2, 3, or 4 Software standby WP4D: Write to P4DDR WP4: Write to Port 4 Bus release RP4: Read Port 4 Reset 0 to 7 P4 DDR...
Page 425: Port 5 Port Read
C.5 Schematic Diagram of Port 5 Figure C-5 gives a schematic view of the port 5 input/output circuits. Mode 1, 2, 3, or 4 Software standby WP5D: Write to P5DDR Mode 1 or 3 WP5: Write to Port 5 Bus release RP5: Read Port 5 Reset...
Page 426: Port 6 Port Read
C.6 Schematic Diagram of Port 6 Figure C-6 gives a schematic view of the port 6 input/output circuits. Mode 3 or 4 Software standby WP6D: Write to P6DDR Mode 3 WP6: Write to Port 6 Bus release RP6: Read Port 6 Reset 0 to 3 pull-up...
Page 427 C.7 Schematic Diagram of Port 7 Figure C-7 (a) to (e) gives a schematic view of the port 7 input/output circuits. WP7D: Write to P7DDR Reset WP7: Write to Port 7 RP7: Read Port 7 P7 DDR WP7D Reset P7 DR 8-Bit timer module Input clock Figure C-7 (a) Schematic Diagram of Port 7, Pin P7...
Page 428 Reset WP7D: Write to P7DDR WP7: Write to Port 7 RP7: Read Port 7 P7 DDR 1 or 2 WP7D Reset P7 DR Free-running timer module Input capture signal Figure C-7 (b) Schematic Diagram of Port 7, Pins P7 and P7 Table C-7 (b) Port 7 Port Read (Pins P7 , P7 Setting...
Page 429 WP7D: Write to P7DDR Reset WP7: Write to Port 7 RP7: Read Port 7 P7 DDR WP7D Reset P7 DR 8-Bit timer module Counter reset input Free-running timer module Input capture signal Figure C-7 (c) Schematic Diagram of Port 7, Pin P7 Table C-7 (c) Port 7 Port Read (Pin P7 Setting Port Read Data...
Page 430 Reset WP7D: Write to P7DDR WP7: Write to Port 7 RP7: Read Port 7 4, 5 or 6 P7 DDR WP7D Reset P7 DR Free-running timer module Output enable Output compare output Counter clock output Figure C-7 (d) Schematic Diagram of Port 7, Pins P7 , P7 and P7 Table C-7 (d) Port 7 Port Read (Pins P7...
Page 431 WP7D: Write to P7DDR Reset WP7: Write to Port 7 RP7: Read Port 7 P7 DDR WP7D Reset P7 DR Free-running timer module Output enable Output compare output Figure C-7 (e) Schematic Diagram of Port 7, Pin P7 Table C-7 (e) Port 7 Port Read (Pin P7 Setting Port Read Data Output enable...
Page 432 C.8 Schematic Diagram of Port 8 Figure C-8 gives a schematic view of the port 8 input circuits. RP8: Read Port 8 0 to 7 A/D converter module Input multiplexer Figure C-8 Schematic Diagram of Port 8 Downloaded from Elcodis.com electronic components distributor...
Page 433: And P9
C.9 Schematic Diagram of Port 9 Figure C-9 (a) to (e) gives a schematic view of the port 9 input/output circuits. Reset WP9D: Write to P9DDR WP9: Write to Port 9 RP9: Read Port 9 0 or 1 P9 DDR WP9D Reset P9 DR...
Page 434: And P9
Reset WP9D: Write to P9DDR WP9: Write to Port 9 RP9: Read Port 9 2, 3, or 4 P9 DDR WP9D Reset P9 DR PWM timer module Output enable PWM , PWM , or PWM output Figure C-9 (b) Schematic Diagram of Port 9, Pins P9 , P9 and P9 Table C-9 (b) Port 9 Port Read (Pins P9...
Page 435: C) Schematic Diagram Of Port 9, Pin P9
Reset WP9D: Write to P9DDR WP9: Write to Port 9 RP9: Read Port 9 P9 DDR WP9D Reset P9 DR SCI timer module Output enable Serial transfer data Figure C-9 (c) Schematic Diagram of Port 9, Pin P9 Table C-9 (c) Port 9 Port Read (Pin P9 Setting Port Read Data Output enable...
Page 436: D) Schematic Diagram Of Port 9, Pin P9
Reset WP9D: Write to P9DDR WP9: Write to Port 9 RP9: Read Port 9 P9 DDR WP9D Reset P9 DR SCI timer module Input enable Serial receive data Fig. C-9 (d) Figure C-9 (d) Schematic Diagram of Port 9, Pin P9 Table C-9 (d) Port 9 Port Read (Pin P9 Setting Port Read Data...
Page 437: E) Schematic Diagram Of Port 9, Pin P9
Reset WP9D: Write to P9DDR WP9: Write to Port 9 RP9: Read Port 9 P9 DDR WP9D Reset SCI timer module P9 DR Clock input enable Clock output enable Clock output Clock input Figure C-9 (e) Schematic Diagram of Port 9, Pin P9 Table C-9 (e) Port 9 Port Read (Pin P9 Setting Port Read Data...
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Page 439 Downloaded from Elcodis.com electronic components distributor...
Page 440 Appendix E Pin State E.1 Port State of Each Pin State Table E-1 Port State Hardware Port Standby Software Bus-right Program Execution Pin Name Mode Reset Mode Standby mode Sleep Mode Release Mode State (Normal Operation) to P1 Input/Output port or TMO, IRQ , IRQ Control signal Input/...
Page 441 Table E-1 Port State (cont) Hardware Port Standby Software Bus-right Program Execution Pin Name Mode Reset Mode Standby mode Sleep Mode Release Mode State (Normal Operation) to P6 keep keep keep Input/Output port to A to A Address/Input port keep keep Input/Output port to P7...
Page 442 Table E-2 Pull-Up MOS State Port Mode Reset Hardware Standby Mode Other Operating State* to P5 to A ON/OFF ON/OFF to P5 ON/OFF to A ON/OFF OFF: Pull-up MOS is always OFF. ON/OFF: Pull-up MOS holds on-state only when DDR = “0” and DR = 1. * Including Software Standby Mode Downloaded from Elcodis.com...
Page 443 E.2 Pin Status in the Reset State 1. Mode 1 Figures E-1 and E-2 show how the pin states change when the RES pin goes Low during external memory access in mode 1. As soon as RES goes Low, all ports are initialized to the input (high-impedance) state. The AS, DS, RD, and WR signals all go High.
Page 444: Reset During Memory Access (Mode 1)
ZTAT Versions External memory access P1 / ø* Internal reset signal H’0000 to A AS, RD and DS (read) WR and DS (write) High impedance D to D (write) High impedance I/O ports The dotted line indicates that P1 /ø is an input port if the corresponding DDR bit is 0, but a clock output pin if the DDR bit is 1.
Page 445: Reset During Memory Access (Mode 1)
Masked-ROM Versions External memory access P1 / ø* Internal reset signal to A H’0000 AS, RD and DS (read) WR and DS (write) High impedance D to D (write) High impedance I/O ports The dotted line indicates that P1 /ø is an input port if the corresponding DDR bit is 0, but a clock output pin if the DDR bit is 1.
Page 446 2. Mode 2 Figures E-3 and E-4 show how the pin states change when the RES pin goes Low during external memory access in mode 2. As soon as RES goes Low, all ports are initialized to the input (high-impedance) state. The AS, DS, RD, and WR signals all go High.
Page 447: Reset During Memory Access (Mode 2)
ZTAT Versions External memory access P1 / ø* Internal reset signal H’00 A to A High impedance P5 /A to P5 to A AS, RD and DS (read) WR and DS (write) High impedance D to D (write) High impedance I/O ports The dotted line indicates that P1 /ø...
Page 448: Reset During Memory Access (Mode 2)
Masked-ROM Versions External memory access P1 / ø* Internal reset signal H’00 A to A High impedance P5 /A to P5 /A AS, RD and DS (read) WR and DS (write) High impedance D to D (write) High impedance I/O ports The dotted line indicates that P1 /ø...
Page 449 3. Mode 3 Figures E-5 and E-6 show how the pin states change when the RES pin goes Low during external memory access in mode 3. As soon as RES goes Low, all ports are initialized to the input (high-impedance) state. The AS, DS, RD, and WR signals all go High.
Page 450: Reset During Memory Access (Mode 3)
ZTAT Version External memory access P1 / ø* Internal reset signal to A H’00000 AS, RD and DS (read) WR and DS (write) High impedance D to D (write) High impedance I/O ports The dotted line indicates that P1 /ø is an input port if the corresponding DDR bit is 0, but a clock output pin if the DDR bit is 1.
Page 451: Reset During Memory Access (Mode 3)
Masked-ROM Version External memory access P1 / ø* Internal reset signal to A H’0000 AS, RD and DS (read) WR and DS (write) High impedance D to D (write) High impedance I/O ports The dotted line indicates that P1 /ø is an input port if the corresponding DDR bit is 0, but a clock output pin if the DDR bit is 1.
Page 452 4. Mode 4 Figures E-7 and E-8 show how the pin states change when the RES pin goes Low during external memory access in mode 4. As soon as RES goes Low, all ports are initialized to the input (high-impedance) state. The AS, DS, RD, and WR signals all go High.
Page 453: Reset During Memory Access (Mode 4)
ZTAT Versions P1 / ø* Internal reset signal H’00 A to A High impedance P6 /A to P6 to A P5 /A to P5 /A AS, RD and DS (read) WR and DS (write) High impedance D to D (write) High impedance I/O ports The dotted line indicates that P1...
Page 454: Reset During Memory Access (Mode 4)
Masked-ROM Versions P1 / ø* Internal reset signal H’00 A to A P6 /A to P6 /A , High impedance P5 /A to P5 /A AS, RD and DS (read) WR and DS (write) High impedance D to D (write) High impedance I/O ports The dotted line indicates that P1...
Page 455: Reset During Memory Access (Mode 7)
5. Mode 7 Figures E-9 and E-10 show how the pin states change when the RES pin goes Low in mode 7. As soon as RES goes Low, all ports are initialized to the input (high-impedance) state. The clock output pins P1 /ø...
Page 456: Reset During Memory Access (Mode 7)
Masked-ROM Versions P1 / ø* P1 /E* Internal reset signal High impedance I/O ports The dotted line indicates that P1 /ø and P1 /E are input port if the corresponding DDR bit is 0, but clock output pins if the DDR bit is 1. Figure E-10 Reset during Memory Access (Mode 7) Downloaded from Elcodis.com...
Page 457 Appendix F Timing of Entry to and Recovery from Hardware Standby Mode Timing of Entry to Hardware Standby Mode (1) To preserve RAM contents, drive the RES signal line low 10 system clock cycles before the fall of the STBY signal. The RES signal can rise any time after STBY goes low.
Page 458: Package Dimensions
Appendix G Package Dimensions Figure G-1 shows the dimensions of the CP-84 package. Figure G-2 shows the dimensions of the CG-84 package. Figure G-3 shows the dimensions of the FP-80A package. Figure G-1 Package Dimensions (CP-84) Figure G-2 Package Dimensions (CG-84) Downloaded from Elcodis.com electronic components distributor...
Page 459: Package Dimensions
Figure G-3 Package Dimensions (FP-80A) Downloaded from Elcodis.com electronic components distributor...

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