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Hitachi Manuals
Computer Hardware
H8/500 Series
Hardware manual
Hitachi H8/500 Series Hardware Manual
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Contents
Table of Contents
Bookmarks
Table of Contents
Table of Contents
Section 1 Overview
Features
Addressing Modes
Block Diagram
Pin Arrangements and Functions
Pin Arrangement
Pin Arrangement (CP-84, Top View)
Section 2 MCU Operating Modes and Address Space
Overview
Operating Modes
Mode Descriptions
Address Space Map
Page Segmentation
Address Space in each Mode
Address Allocations
Mode Control Register (MDCR)
Mode Control Register
Section 3 CPU
Overview
Features
Address Space
CPU Operating Modes
Register Configuration
Registers in the CPU
CPU Register Descriptions
General Registers
Stack Pointer
Control Registers
Interrupt Mask Levels
Interrupt Mask Bits after an Interrupt Is Accepted
Combinations of Page Registers with Other Registers
Short Absolute Addressing Mode and Base Register
Initial Register Values
Data Formats
Data Formats in General Registers
Initial Values of Registers
Data Formats in Memory
General Register Data Formats
Data Formats in Memory
Instructions
Basic Instruction Formats
Data Formats on the Stack
Addressing Modes
Effective Address Calculation
Instruction Set
Overview
Instruction Classification
Data Transfer Instructions
Arithmetic Instructions
Logic Operations
Logic Operation Instructions
Shift Operations
Shift Instructions
Bit Manipulations
Bit-Manipulation Instructions
Branching Instructions
System Control Instructions
Operating Modes
Minimum Mode
Short-Format Instructions and Equivalent General Formats
Maximum Mode
Basic Operational Timing
Overview
On-Chip Memory Access Cycle
On-Chip Memory Access Timing
Pin States During On-Chip Memory Access
Pin States During Access to On-Chip Memory
Register Field Access Cycle (Addresses H'FF80 to H'FFFF)
Register Field Access Timing
Pin States During Register Field Access (Addresses H'FF80 to H'FFFF)
Pin States During Register Field Access
External Access Cycle
CPU States
Overview
Operating States
Power-Down State
Program Execution State
Exception-Handling State
State Transitions
Bus-Released State
Bus-Right Release Cycle (During On-Chip Memory Access Cycle)
Bus-Right Release Cycle (During External Access Cycle)
Bus-Right Release Cycle (During Internal CPU Operation)
Reset State
Power-Down State
Programming Notes
Restriction on Address Location
Note on MULXU Instruction
Section 4 Exception Handling
Overview
Types of Exception Handling and Their Priority
Hardware Exception-Handling Sequence
Exception Factors and Vector Table
Types of Factors Causing Exception Handling
Exception Vector Table
Reset
Overview
Reset Sequence
Stack Pointer Initialization
Reset Vector
Reset Sequence (Minimum Mode, On-Chip Memory)
Reset Sequence (Maximum Mode, External Memory)
Address Error
Illegal Instruction Prefetch
Word Data Access at Odd Address
Off-Chip Address Access in Single-Chip Mode
Trace
Interrupts
Interrupt Sources (and Number of Interrupt Types)
Invalid Instruction
Trap Instructions and Zero Divide
Cases in Which Exception Handling Is Deferred
Instructions that Disable Interrupts
Disabling of Exceptions Immediately after a Reset
Disabling of Interrupts after a Data Transfer Cycle
Stack Status after Completion of Exception Handling
Stack after Exception Handling Sequence
PC Value Pushed on Stack for Trace
Interrupts, Trap Instructions, and Zero Divide Exceptions
Instruction Exceptions
Notes on Use of the Stack
Section 5 Interrupt Controller
Overview
Features
Block Diagram
Interrupt Controller Block Diagram
Register Configuration
Interrupt Types
External Interrupts
Interrupt Controller Registers
Internal Interrupts
Interrupt Vector Table
Interrupts, Vectors, and Priorities
Register Descriptions
Interrupt Priority Registers a to D (IPRA to IPRD)
Assignment of Interrupt Priority Registers
Timing of Priority Setting
Interrupt Handling Sequence
Interrupt Handling Flow
Interrupt Handling Flowchart
Stack Status after Interrupt Handling Sequence
Timing of Interrupt Exception-Handling Sequence
Interrupts During Operation of the Data Transfer Controller
Interrupt Sequence (Minimum Mode, On-Chip Memory)
Interrupt Sequence (Maximum Mode, External Memory)
Interrupt Response Time
Number of States before Interrupt Service
Section 6 Data Transfer Controller
Overview
Features
Block Diagram
Register Configuration
Data Transfer Mode Register (DTMR)
Block Diagram of Data Transfer Controller
Internal Control Registers of the DTC
Data Transfer Enable Registers
Data Transfer Source Address Register (DTSR)
Data Transfer Destination Register (DTDR)
Data Transfer Count Register (DTCR)
Data Transfer Enable Registers a to D (DTEA to DTED)
Assignment of Data Transfer Enable Registers
Data Transfer Operation
Data Transfer Cycle
Flowchart of Data Transfer Cycle
DTC Vector Table
DTC Vector Table Entry
Addresses of DTC Vectors
Location of Register Information in Memory
Length of Data Transfer Cycle
Order of Register Information
Number of States Per Data Transfer
Procedure for Using the DTC
Number of States before Interrupt Service
Example
DTC Control Register Information Set in RAM
Use of DTC to Receive Data Via Serial Communication Interface
Section 7 Wait-State Controller
Overview
Features
Block Diagram
Register Configuration
Block Diagram of Wait-State Controller
Wait-State Control Register
Operation in each Wait Mode
Programmable Wait Mode
Wait Modes
Pin Wait Mode
Programmable Wait Mode
Pin Wait Mode
Pin Auto-Wait Mode
Section 8 Clock Pulse Generator
Overview
Block Diagram
Oscillator Circuit
Block Diagram of Clock Pulse Generator
Connection of Crystal Oscillator (Example)
Crystal Oscillator Equivalent Circuit
External Crystal Parameters
Notes on Board Design Around External Crystal
External Clock Input (Example)
System Clock Divider
Phase Relationship of Ø Clock and E Clock
Section 9 I/O Ports
Overview
Input/Output Port Summary
Port 1
Overview
Port 1 Registers
Pin Functions
And P1
Pin Functions in each Mode
Port 1 Pin Functions in Expanded Modes
Port 1 Pin Functions in Single-Chip Modes
Port 2
Port 2 Registers
Pin Functions in each Mode
Port 2 Pin Functions in Expanded Modes
Port 3
Overview
Port 2 Pin Functions in Single-Chip Mode
Port 3 Registers
Pin Functions in each Mode
Port 3 Pin Functions in Expanded Modes
Port 3 Pin Functions in Single-Chip Mode
Port 4
Port 4 Registers
Pin Functions in each Mode
Port 4 Pin Functions in Expanded Modes
Overview
Port 4 Pin Functions in Single-Chip Mode
Port 5 Registers
Pin Functions in each Mode
Port 5 Pin Functions in Single-Chip Mode
Built-In MOS Pull
Overview
Port 6 Registers
Port 7
Overview
Port 7 Registers
Pin Functions
Port 7 Pin Functions
Port 8
Overview
Port 8 Registers
Port 9
Overview
Port 9 Registers
Port 9 Pin Functions
Pin Functions
Section 10 16-Bit Free-Running Timers
Overview
Features
Block Diagram
Block Diagram of 16-Bit Free-Running Timer
Input and Output Pins
Input and Output Pins of Free-Running Timer Module
Register Configuration
Register Descriptions
Free-Running Counter (FRC)-H'FF92, H'FFA2, H'FFB2
Input Capture Register (ICR)-H'FF98, H'FFA8, H'FFB8
Timer Control Register (TCR)
Timer Control/Status Register (TCSR)
CPU Interface
Operation
FRC Incrementation Timing
Output Compare Timing
Increment Timing for External Clock Input
Setting of Output Compare Flags
Timing of Output Compare
Input Capture Timing
Clearing of FRC by Compare-Match
Input Capture Timing (Usual Case)
Input Capture Timing (1-State Delay)
Setting of Input Capture Flag
Setting of FRC Overflow Flag (OVF)
CPU Interrupts and DTC Interrupts
Setting of Overflow Flag (OVF)
Free-Running Timer Interrupts
Synchronization of Free-Running Timers 1
Synchronization after a Reset
Synchronization by Writing to Frcs
Sample Application
Application Notes
Contention between OCR Write and Compare-Match
Effect of Changing Internal Clock Sources
Effect of Changing Internal Clock Sources
Section 11 8-Bit Timer
Overview
Features
Block Diagram
Block Diagram of 8-Bit Timer
Input and Output Pins
Register Configuration
Register Descriptions
Timer Counter (TCNT)-H'FFD4
Input and Output Pins of 8-Bit Timer
Time Constant Registers a and B
Timer Control Register (TCR)-H'FFD0
Timer Control/Status Register (TCSR)
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