Hitachi H8S/2199 Hardware Manual page 577

Single-chip microcomputer

Table of Contents

Bit 1    Video FF Counter Set (VST): Selects whether the REF30 counter register value is set on

or off by the Video FF signal when the drum phase is in FIX on in the PB mode.

Counter set off by Video FF signal

Counter set on by Video FF signal

Bit 0    Video FF Edge Selection Bit (VEG): Selects the edge at which REF30 counter is set

(VST = 1) by the Video FF signal.

Set at the rising edge of Video FF signal

Set at the falling edge of Video FF signal

Reference Period Register 1 (RFD)

Initial value :

The reference period register 1 (RFD) is a buffer register which generates the reference signal

(REF30) for playback, VD compensation for recording, and the reference signals for free-running.

It is an 16-bit write-only register accessible in word units only. If a read is attempted, an

undetermined value is read out.

The value set in RFD should be 1/2 of the desired reference signal period. Care is required when

VD is unstable, such as when the field is weak (synchronization with VD cannot be acquired if a

value less than 1/2 is set in REC). When data is written in RFD, it is stored in the buffer once, and

then fetched into RFD by a match signal of the comparator. (The data which generates the

reference signal is updated by the match signal.) A forcible write, such as initial setting, etc.,

should be done by a dummy read of RFD.

If a byte-write in RFD is attempted, correct operation is not guaranteed. RFD is initialized to

H'FFFF by a reset, and in stand-by and module stop modes.

Use bit 7 (ASM) and bit 6 (REC/PB) in the CTL mode register (CTLM) in the CTL circuit to

switch between record and playback modes. Use bit 4 (CR/RF bit) in the capstan phase error

detection control register (CPGCR) to switch between REF30 and CREF for capstan phase

Rev. 1.0, 02/00, page 571 of 1141

(Initial value)