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Duty I/O Register (DI/O)
Bit :
VCTR2
Initial value :
R/W :
Note: * Only 0 can be written
DI/O is an 8-bit register that confirms and determines the operating status of the CTL circuit.
It is initialized to H'F1 by a reset, and in standby mode, module stop mode, and CTL stop mode.
Bits 7 to 5 VISS Interrupt Setting Bit (VCTR2 to VCTR0): Combination of VCTR2, VCTR1
and VCTR0 sets number of 1 pulse detection in VISS detection mode. Detecting the set number
of pulse detection is considered as VISS detection, and an interrupt request is generated.
Note: When changing the detection pulse number during VISS detection, initialize VISS first,
then resume the VISS detection setting.
Bit 7
Bit 6
VCTR2
VCTR1
0
0
1
1
0
1
Bit 4 Reserved: Cannot be modified and is always read as 1.
7
6
VCTR1
VCTR0
1
1
W
W
Bit 5
VCTR0
0
1
0
1
0
1
0
1
5
4
—
BPON
1
1
—
W
Number of 1-Pulse for Detection
2
4 (SYNC mark)
6
8 (mark A, short)
12 (mark A, long)
16
24 (mark B)
32
3
2
BPS
BPF
0
0
W
W
R/(W)*
Rev. 1.0, 02/00, page 697 of 1141
1
0
DI/O
0
1
R/W
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