Operation - Hitachi H8S/2199 Hardware Manual

Single-chip microcomputer
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26.6.5

Operation

The drum speed error detector detects the speed error based on the reference value set in the DFG
specified speed preset register (DFPR). The reference value set in DFPR is preset in the counter
by NCDFG signal, and the counter decrements the count by the selected clock. The timing of the
counter presetting and the error data latching can be selected between the rising or falling edge of
NCDFG signal. See section 26.14.4, FG Control Register (FGCR) in 26.14.4 DFG Noise
Removal Circuit. The error data detected is sent to the digital filter circuit. The error data is
signed binaries. The data takes a positive number (+) if the speed is slower than the specified
speed, a negative number (-) if the speed is faster, or 0 if it had no error (revolving at the specified
speed). Figure 26.28 shows an example of operation to detect the drum speed.
• Setting the error data limit
A limit can be set to the error data sent to the digital filter circuit using the DFG lock data
register (DFRUDR, DFRLDR). Set the upper limit of the error data in DFRUDR and the
lower limit in DFRLDR, and write 1 in DFRFON bit. If the error data is outside the limit
range, the DFRLDR value is sent to the digital filter circuit if a negative number is latched, or
the DFRUDR value if a positive number is latched, as a limit value. Be sure to turn off the
limit setting (DFRFON = 0) when you set the limit value. If the limit was set with the limit
setting on (DFRFON = 1), result of computation is not assured.
• Lock detection
If an error data is detected within the lock range set in the lock data register, the drum lock flag
(DF-R/UNR) is set by the number of the times of locking set by DFRCS1 and DFRCS0 bits,
and an interrupt is requested (IRRDRM2) at the same time. The number of the occurrence of
locking (once to 4 times) before the flag is set can be specified. Use DFRCS1 and DFRCS0
bits for this purpose. The on/off status of the phase system digital filter computation can be
controlled automatically by the status of lock detection when bit 5 (DPHA bit) of the drum
system digital filter control register (DFIC) is 0 (phased system digital filter computation off)
and DPCNT bit is 1.
• Drum system speed error detection counter
The drum system speed error detection counter stops the counter and sets the overflow flag
(DFOVF) when an overflow occurs. At the same time, it generates an interrupt request
(IRRDRM1). To clear DFOVF, write 0 after reading 1. If setting the flag and writing 0 take
place simultaneously, the latter is invalid.
Rev. 1.0, 02/00, page 626 of 1141

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